INFOOP2R.WIX.

COM/OP2R

RIPPLE CARRY ADDER VHDL CODE USING STRUCTURAL MODELING

Library declaration
library IEEE;
Std_logic_1164. package for std_logic (predefined data type).
use IEEE.STD_LOGIC_1164.ALL;
---------------------------------------------------------------------

Entity declaration: -

entity RCA_1 is
Port ( ain,bin : in STD_LOGIC_VECTOR (3 downto 0);
sum: out std_logic_vector(3 downto 0);
carry: out std_logic);
end RCA_1;

ain, bin:- two input bit which will be

added by rillple carry adder.
Sum: - result of two number
additions will be stored in sum.
Carry: - output carry will be stored in
carry.

---------------------------------------------------------------------architecture Behavioral_rca of rca_1 is

--------------------------------------------------------------
Architecture declaration part.
component full_adder is

Component full adder is declared in

Port ( a,b,c : in STD_LOGIC;
declarative part of architecture.
sumf,carryf : out STD_LOGIC);

Signal carry0 is initialized as 0 value.

Signal carry1, carry2, carry3, carry4

end component;
declared as inout port, holds the value of
signal carry1, carry2,carry3: std_logic;
carry generated from each bit.
signal carry0: std_logic:='0';
----------------------------------------------------------------------------------begin

Statement parts of
l1: full_adder port map (ain(0),bin(0),carry0,sum(0),carry1);
architecture.
l2: full_adder port map (ain(1),bin(1),carry1,sum(1),carry2);

Full adder component is

l3: full_adder port map (ain(2),bin(2),carry2,sum(2),carry3);
port mapped to perform
the circuit operation.
l4: full_adder port map (ain(3),bin(3),carry3,sum(3),carry);
----------------------------------------------------------------------------------end Behavioral_rca;

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INFOOP2R.WIX.COM/OP2R

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