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2-bit ripple binary counter using JK flip flops (asynchronous counters)

J J

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1 Q0 Q1

CP K Q0 CP Q0 Q0 Q1 K

J 0 0 1 1

K 0 1 0 1

Q(t+1) Q(t) 0 1 Q(t)

Q1

0 0

1 0

0 1
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1 1

0 0

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1 J CP

3-bit ripple binary counter using JK flip flops (asynchronous counters)

Q0 J Q1 J Q2

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K Q0 CP Q0 Q0 Q1 Q2

Q1

Q2

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Simple Registers
No external gates. Example: A 4 !it register. A ne" 4 !it #ata is loa#e# on e$er% &lo&' &%&le.
A4 A3 A2 A1

! CP I4

I3
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I2

I1

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((ontrol Signal) Load I1

4-bit register with parallel load

" # A1

I2

" #

A2

I3

" #

A3

I4

" #

A4

CP Clear
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Register "it) *arallel +oa# ,sing - .lip Load .lops $oa% A & $oa% I
1 1

! I1

A1

! I2

A2

I3

A3

I4 CP Clear
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A4

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'sing #egisters to i(ple(ent "e)uential Circuits

/ A se01ential &ir&1it ma% &onsist o2 a register (memor%) an# a &om!inational &ir&1it. Next state $al1e Register
Inputs

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Clock Pulse

Combinational Circuit

Outputs

/ 3)e external inp1ts an# present states o2 t)e register #etermine t)e next states o2 t)e register an# t)e external o1tp1ts4 t)ro1g) t)e &om!inational &ir&1it. / 3)e &om!inational &ir&1it ma% !e implemente# !% an% o2 t)e met)o#s &o$ere# in 5S6 &omponents an# *rogramma!le +ogi& -e$i&es.
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,sing Registers to implement Se01ential (ir&1its

/ *+a(ple 1: -esign a Se01ential (ir&1it ")ose state ta!le is gi$en !elo"
A1+ 7 8 m(449) 7 A1. x: A;+ 7 8 m(14;4<49) 7 A;.x: + A:; .x 7 A; x % 7 8 m(=4>) 7 A;.x Present State A1 A2 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1
1sing t"o 2lip 2lops.

"tate ,able
Input x 0 1 0 1 0 1 0 1

Next State A1+ A2+ 0 0 0 0 0 1 0 1 0 1 1 0 0 1 1 0

$ogic !iagra(
Output y 0 0 0 1 0 0 0 1 x y

A1 - +. A2 +

A1 A2

"e)uential Circuit I(ple(entation www.jntuworld.com

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,sing Registers to implement Se01ential (ir&1its

/
A%%ress /utputs 1 2 3 1 2 3 A1 A2 + A1 A 2 y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 0 0 1 R?5 tr1t) ta!le

Example ;: Repeat example 14 !1t 1se a R?5 @Register.

A1 A2

1 2 3

8X3 ROM

1 2 3 !

Sequential circuit using a register and a ROM

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Serial 6NASerial ?1t S)i2t Registers

" Accepts #ata seriall! $ one bit at a time an# also pro#uces output seriall!%
"erial Input ("I) !
0

"erial /utput ("/)

C$K

"hift #egister
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"erial In1"erial /ut "hift #egisters

/ Appli&ation: Serial trans2er o2 #ata 2rom one register to anot)er.

S6 (lo&' S)i2t (ontrol (lo&' S)i2t (ontrol (*

1011 S)i2t register A (*

S?

S6

0010 S)i2t register B

S?

&or#time

31

3;

3=

34

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"erial In1"erial /ut "hift #egisters

Serial trans2er example.

3iming *1lse 6nitial $al1e A2ter 31 A2ter 32 A2ter 3= A2ter 34

S)i2t Register A 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 0 1 1

S)i2t Register B 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1

Serial o1tp1t o2 B 0 1 0 0 1

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2i%irectional "hift #egisters

4-bit bi%irectional shift register 3ith parallel loa%
*arallel o1tp1ts A4 A= A;

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A1

(lear

Q -

Q -

Q -

Q -

(+K

S1 S0

' 1 ()* 3 2 1 0

' 1 ()* 3 2 1 0

' 1 ()* 3 2 1 0

' 1 ()* 3 2 1 0

Serial inp1t 2or s)i2t rig)t

64

6= *arallel inp1ts

6;

61

Serial inp1t 2or s)i2t le2t

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Bi#ire&tional S)i2t Registers

/ 4 !it !i#ire&tional s)i2t register "it) parallel loa#. 5o#e (ontrol s1 s0 Register ?peration 0 0 No &)ange 0 1 S)i2t rig)t 1 0 S)i2t le2t 1 1 *arallel loa#
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An Application-"erial A%%ition
/ 5ost operations in #igital &omp1ters are #one in parallel. Serial operations are slo"er !1t re01ire less e01ipment. / A serial a##er is s)o"n !elo". A A+B.
S6 1010 S)i2t register A S6 0111 S)i2t register B S? S? x % .A C Q S (

S)i2t rig)t (* External inp1t

(lear

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*+citation table for a serial a%%er

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Example: -esign a serial a##er 1sing a se01ential logi& pro&e#1re Q(t) Q(t+1) J K "it) JK 2lip 2lops.
*resent State Q 0 0 0 0 1 1 1 1 6np1ts x 0 0 1 1 0 0 1 1 % 0 1 0 1 0 1 0 1 Next State Q 0 0 0 1 0 1 1 1 ?1tp1t S 0 1 1 0 1 0 0 1 .lip 2lop inp1ts JQ 0 0 0 1 D D D D KQ D D D D 1 0 0 0 0 0 1 1 0 1 0 1 0 1 D D

D 1 D 0

S7x+% + Q JQ 7 x% KQ 7 x% 7(x+%)

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S)i2t rig)t (* External inp1t

S)i2t register A

S?7x

S)i2t register B S?7%

J Q

(lear

Second form of a serial adder

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S7x+% + Q JQ 7 x% KQ 7 x% 7(x+%)

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4-bit binary ripple counter

J 0 K 0 1 0 1
J 1

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Q(t+1) Q(t) 0 1 Q(t)

A4

A=

A;

A1

0 1 1

Q 3o next stage

(o1nt p1lses K 1 K 1 K 1 K 1

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Count se)uence for a binary ripple counter

(o1nt se01en&e A4 A= A; A1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 (on#ition 2or &omplementing 2lip 2lops (omplement A1 (omplement A1 (omplement A1 (omplement A1 (omplement A1 (omplement A1 (omplement A1 (omplement A1 A1 "ill go 2rom 1 to 0 an# &omplement A;F A; "ill go 2rom 1 to 0 an# &omplement A=F 1 0 0 0 A= "ill go 2rom 1 to 0 an# &omplement A4 An# so onEE
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A1 "ill go 2rom 1 to 0 an# &omplement A; A1 "ill go 2rom 1 to 0 an# &omplement A; A; "ill go 2rom 1 to 0 an# &omplement A= A1 "ill go 2rom 1 to 0 an# &omplement A;

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"tate %iagra( of a %eci(al 2C! counter

0000

0001

0010

0011

0100

1001

1000

0111

0110

0101

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$ogic %iagra( of a 2C! ripple counter

0 Q4 0 Q; 0 Q1

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0 QG

1 Q J

0 Q J

0 Q J

1 Q J 1 (o1nt p1lses

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J 0 0 1 1

K 0 1 0 1

Q(t+1) Q(t) 0 1 Q(t)

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Timing diagram for the decimal counter

(o1nt p1lses

Q1 Q; 0 Q= 0 Q4 0 Q< 0
1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0

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Block diagram of a 3-decade decimal BCD counter

QG Q4 Q; Q1

QG Q4 Q; Q1

QG Q4 Q; Q1

B((o1nter
10; #igit 0 HHH

B((o1nter
101 #igit 0 HH

B((o1nter
100 #igit 0H

(o1nt p1lses

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J 0 0 1 1

K 0 1 0 1

Q(t+1) Q(t) 0 1 Q(t)

4-bit synchronous binary counter

A4

A3

A2

A1

J (*

3o next stage
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(o1nt ena!le

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3 0 1

Q(t+1) Q(t) Q(t)

4-bit up-down binary counter

A4 A3 A2 A1

, CP

3o Next stage

'P

!o3n
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!esign a 2C! counter using , flip-flops

*+citation table for a 2C! counter

(o1nt Se01en&e
QG
0 0 0 0 0 0 0 0 1 1

.lip 2lop inp1ts

Q1
0 1 0 1 0 1 0 1 0 1

?1tp1t (arr%
%
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1

Q4
0 0 0 0 1 1 1 1 0 0

Q;
0 0 1 1 0 0 1 1 0 0

3QG
0 0 0 0 0 0 0 1 0 1

3Q4
0 0 0 1 0 0 0 1 0 0

3Q;
0 1 0 1 0 1 0 1 0 0

3Q1

,sing K maps4 "e get 3Q1 71 3Q; 7 QAGQ1 3Q4 7 Q;Q1 3QG 7 QGQ1 + Q4Q;Q1 % 7 QGQ1 4o3 logic %iagra( can be %ra3n for 2C! synchronous counter www.jntuworld.com

Q(t) Q(t+1) 0 0 1 1 0 1 0 1

3 0 1 1 0

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QG QG
, CP

Q4 Q4
,

Q; Q;

Q1 Q1

y
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3Q1 71 3Q; 7 QAGQ1 3Q4 7 Q;Q1 3QG 7 QGQ1 + Q4Q;Q1 % 7 QGQ1

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Counters 3ith Parallel $oa% 4 !it &o1nter "it) parallel loa#.

Clear 0 1 1 1 CP * * +oa# * 0 1 0 Count * 0 * 1 1unction Clear to 0 ,o C0ange +oa# inputs ,e t -tate .counting/

Count +oa# I1

J K

A1

I2

J K

A2

I3

J K

A3

J 0 0 1 1

K 0 1 0 1

Q(t+1) Q(t) 0 1 Q(t)

I4

J K

A4

Clear CP

4 !it !inar% &o1nter "it) parallel loa# www.jntuworld.com

Carr! out

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Counters 3ith Parallel $oa% -i22erent "a%s o2 getting a 5?- 9 &o1nter

A4 A3 A2 A1 +oa# I ' I 3 I2 I1 Inputs 2 0 Count 2 1 Clear 2 1 CP Clear I ' I 3 I2 I1 A4 A3 A2 A1 Count 2 1 +oa# 2 0 CP

(a) 2inary states 05152535456

A4 A3 A2 A1 Carr!3out +oa# I' I 3 I2 I 1 1 0 1 0 Count 2 1 Clear 2 1 CP

(b) 2inary states 05152535456

A4 A3 A2 A1 +oa# I' I 3 I2 I 1 0 0 1 1 Count 2 1 Clear 2 1 CP

(c) 2inary states 10511512513514516 (%) 2inary states 35456575859

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,i(ing "e)uences
-tart CP -top # " &or#3time control

CP

33bit counter

Count enable

(a) (ir&1it -iagram

CP -tart -top Q &or#3time 2 4 pulses

(!) Ieneration o2 a "or# time &ontrol 2or serial operations

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-0i6t rig0t

50

51

52

53

(a) ring &o1nter (initial $al1e 7 1000)

50 51 52 53 CP 50 51 52 53

2*' #eco#er
Count enable

23bit counter

(!) (o1nter an# -e&o#er

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(&) Se01en&e o2 2o1r timing signals

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A1

21

C1

*1

CP

(a) 4-stage s3itch tail ring counter "e)uence nu(ber

1 2 3 4 6 7 8 9

:lip-flop outputs A 2 C *
0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1

An% gate re)uire% for outputs

A1 *1 A 21 2 C1 C *1 A* A1 2 21 C C1 *

b! Count se"uence and re"uired decoding

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