Experiment:......................................................................................... Expt. No. :..............................

Date: ....................................
............................................................................................................. Page No: ..............................
Project 19: Binary to Gray Conversion
--------------------------------------------------------------------------- Company: DBCET
-- Engineer: Santanu Nath
-- ID:DC2011BTE0059
-- Create Date: 21:35:49 18/02/2014
-- Module Name: bintogray Behavioral
---------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entitybintogray is
Port ( B3 : in STD_LOGIC;
B2 : in STD_LOGIC;
B1 : in STD_LOGIC;
B0 : in STD_LOGIC;
G3 : out STD_LOGIC;
G2 : out STD_LOGIC;
G1 : out STD_LOGIC;
G0 : out STD_LOGIC);
endbintogray;
architectureBehavioral of bintogray is
begin
process(B3,B2,B1,B0)
begin
G3<=B3;
G2<=B3 xor B2;
G1<=B2 xor B1;
G0<=B1 xor B0;
end process;
endBehavioral;

Experiment:......................................................................................... Expt. No. :..............................

Date: ....................................
............................................................................................................. Page No: ..............................

Project 19: Gray to Binary Conversion

--------------------------------------------------------------------------- Company: DBCET
-- Engineer: Santanu Nath
-- ID:DC2011BTE0059
-- Create Date: 21:39:29 18/02/2014
-- Module Name: graytobin - Behavioral
---------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entitygraytobin is
Port ( G3 : in STD_LOGIC;
G2 : in STD_LOGIC;
G1 : in STD_LOGIC;
G0 : in STD_LOGIC;
B3 :inout STD_LOGIC;
B2 :inout STD_LOGIC;
B1 :inout STD_LOGIC;
B0 :inout STD_LOGIC);
endgraytobin;
architectureBehavioral of graytobin is
begin
process(G3,G2,G1,G0,B3,B2,B1,B0)
begin
B3<=G3;
B2<=B3 xor G2;
B1<=B2 xor G1;
B0<=B1 xor G0;
end process;
endBehavioral;