Digital Systems Design

Dr.Mudathir Fagiri 1

D flip-flop
E

D Q

E
Q

0 0 1 1

D 0 1 0 1

D 1 0 1 0

Q
no change no change 0 1

Q no change no change 1 0

Q follows D when the flip-flop is enabled

1

0 1 0 1 0 1 0

D
D

Q
Timing diagram
Dr.Mudathir Fagiri

Edge triggered SR flip-flop

Two gated SR flip-flops with the second enable line inverted with respect to the first
S Q E

Q
R

Dr.Mudathir Fagiri

Edge triggered SR flip-flop

Timing diagram
1

E
0 1

S R

0 1 0 1

Q
0 time

Falling edge of the enable line triggers change of flip-flop!

Dr.Mudathir Fagiri 4

JK flip-flop
The outputs Q and Q are feed back to the input gates
J E K Q

Edge triggered flip-flop with no invalid state!

Dr.Mudathir Fagiri 5

JK flip-flop
Timing diagram
1

E
0 1

J
K

0 1

0 1

Q
0 time

Dr.Mudathir Fagiri

Flip-flop symbols
SR flip-flop
Enable/clock input S R Q Q

Circle & triangle indicates high-to-low edge triggered version

JK flip-flop

J K

Q Q

Triangle indicates low-to-high edge triggered version

D flip-flop

Q Q

Round input indicates that the clock-level causes the transition

Dr.Mudathir Fagiri

Flip-flop applications
Switch debouncing:
+5 V
1k S Q

Q R +5 V
Dr.Mudathir Fagiri 8

Flip-flop applications
1 J Q Q LSB E - clock A B C A 1 J Q Q B 1 J K Q

Asynchronous counter (ripple counter)

1 J K C Q Q MSB D

1 1 0

D
Dr.Mudathir Fagiri

1 0 1 1 = 1110
9

Flip-flop applications
Frequency divider
1 J Q Q LSB E clock A B C A 1 J Q Q B 1 J K Q 1 J K C f f/2 f/4 f/8 Q Q MSB D

D
Dr.Mudathir Fagiri

f/16
10