/ * Los vectores de interrupcin * / / * Solicitud de interrupcin externa 0 * / # Define INT0_vect _VECTOR (1) # Define SIG_INTERRUPT0 _VECTOR (1) / * Solicitud

de interrupcin externa 1 * / # Define INT1_vect _VECTOR (2) # Define SIG_INTERRUPT1 _VECTOR (2) / * Compara Timer/Counter2 Match * / # Define TIMER2_COMP_vect _VECTOR (3) # Define SIG_OUTPUT_COMPARE2 _VECTOR (3) / * Timer/Counter2 desbordamiento * / # Define TIMER2_OVF_vect _VECTOR (4) # Define SIG_OVERFLOW2 _VECTOR (4) / * Timer/Counter1 evento de captura * / # Define TIMER1_CAPT_vect _VECTOR (5) # Define SIG_INPUT_CAPTURE1 _VECTOR (5) / * Compara Timer/Counter1 Coincidir A * / # Define TIMER1_COMPA_vect _VECTOR (6) # Define SIG_OUTPUT_COMPARE1A _VECTOR (6) / * Compara Timer/Counter1 partido B * / # Define TIMER1_COMPB_vect _VECTOR (7) # Define SIG_OUTPUT_COMPARE1B _VECTOR (7) / * Timer/Counter1 desbordamiento * / # Define TIMER1_OVF_vect _VECTOR (8) # Define SIG_OVERFLOW1 _VECTOR (8) / * Timer/Counter0 desbordamiento * / # Define TIMER0_OVF_vect _VECTOR (9) # Define SIG_OVERFLOW0 _VECTOR (9) / * De transferencia en serie completa * / # Define SPI_STC_vect _VECTOR (10) # Define SIG_SPI _VECTOR (10) / * USART, Rx completo * / # Define USART_RXC_vect _VECTOR (11) # Define SIG_UART_RECV _VECTOR (11)

/ * Datos USART Registro * / vaco # Define USART_UDRE_vect _VECTOR (12) # Define SIG_UART_DATA _VECTOR (12) / * USART, Tx completo * / # Define USART_TXC_vect _VECTOR (13) # Define SIG_UART_TRANS _VECTOR (13) / * Complete la conversin ADC * / # Define ADC_vect _VECTOR (14) # Define SIG_ADC _VECTOR (14) / * EEPROM listo * / # Define EE_RDY_vect _VECTOR (15) # Define SIG_EEPROM_READY _VECTOR (15) / * Comparador analgico * / # Define ANA_COMP_vect _VECTOR (16) # Define _VECTOR SIG_COMPARATOR (16) / * 2-hilos interfaz en serie * / # Define TWI_vect _VECTOR (17) # Define SIG_2WIRE_SERIAL _VECTOR (17) / * Programa Memoria Tienda Listo * / # Define SPM_RDY_vect _VECTOR (18) # Define SIG_SPM_READY _VECTOR (18)