EXPT NO:1(3-8 DECODER) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.

ALL; entity dec is Port ( x : in std_logic_vector(2 downto 0); en : in std_logic; y : out std_logic_vector(7 downto 0)); end dec; architecture Behavioral of dec is begin process(x,en) begin if(en='1')then case(x)is when"000"=>y<="10000000"; when"001"=>y<="01000000"; when"010"=>y<="00100000"; when"011"=>y<="00010000"; when"100"=>y<="00001000"; when"101"=>y<="00000100"; when"110"=>y<="00000010"; when others=> null; end case; else y<="00000000"; end if; end process; end Behavioral;

EXPT NO:2(4-16 DECODER) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decode is Port ( x : in std_logic_vector(3 downto 0); y : out std_logic_vector(9 downto 0); en : in std_logic); end decode; architecture Behavioral of decode is begin process(x,en) begin if(en='1') then case(x) is when "0000"=>y<="1000000000";

when "0001"=>y<="0100000000"; when "0010"=>y<="0010000000"; when "0011"=>y<="0001000000"; when "0100"=>y<="0000100000"; when "0101"=>y<="0000010000"; when "0110"=>y<="0000001000"; when "0111"=>y<="0000000100"; when "1000"=>y<="0000000010"; when "1001"=>y<="0000000001"; when others =>null; end case; else y<="0000000000"; end if; end process; end Behavioral;

EXPT NO:3(MUX) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity multiplexer is Port ( a,b,c,d : in std_logic_vector(2 downto 0); sel : in std_logic_vector(1 downto 0); en : in std_logic; z : out std_logic_vector(2 downto 0)); end multiplexer; architecture Behavioral of multiplexer is begin process(en,sel) begin if(en='1')then case(sel) is when "00"=>z<= a; when "01"=>z<= b; when "10"=>z<= c; when "11"=>z<= d; when others => null; end case; else z<="000"; end if; end process; end Behavioral; EXPT NO:4(MANCHESTER CODE) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nrztoman is

Port ( clk : in std_logic; a : in std_logic; b : out std_logic); end nrztoman; architecture Behavioral of nrztoman is begin process(clk) begin if rising_edge(clk) then b<= end end end a xor clk; if; process; Behavioral;

EXPT NO:5(GRAY TO BINARY CONVERTER) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gtob is Port ( g : in std_logic_vector(3 downto 0); b : out std_logic_vector(3 downto 0)); end gtob; architecture Behavioral of gtob is begin b(3)<=g(3); b(2)<=g(2) xor g(3); b(1)<=g(1) xor g(2) xor g(3); b(0)<=g(0) xor g(1)xor g(2) xor g(3); end Behavioral;