TESTING OF VLSI Cprps ° DETER A SLLECON WAKER LS PROCESSEP THROUGH THE PAERZATIOW LENE, ZT MUST BE TESTEp TO VPETERMINE + )) LP THE PROCESSING STEPS WERE PERFORMED CORRECTLY, RESULTING EN GO0P FETs, VIA, METAL Lines, ETe, 2) WHEE}) CHEPs, OR "pie", CONTAEN PROCESS DEFECT s 3) WHICH CHEPs ARE GROSSLY PUNETIONAL ) WHICH CMLP SEVERAL. SITES ON THE WAFER ARE VEPLCATEP TO "PROP-INs", OR “WAT Keys” (WAT 2 Wager Accepryce Test") > EACH OF THESE TEST SITES CONTAIN SAMPLE PMOS ANP NMOS FETs OF VARZOVS SEBES , AS WELL AS SPECIAL TEST STRVCTRES TO CHECK FOR BAV METAL, VZAS, CONTACTS, ETC, > THE PRoP-INs ARE OFTEN BVLLT INTO THE "SCRIBE LINES” BETWEEN APINCENT CMEPs —% VARLOVS ELECTRICAL PARAMETERS ARE MEASIREP, SUCH AT MoeSPET vray PPATA, ETE, GPAT = Lp zm Ves = vas = Ver) ONCE A Copp PReckss LOT HAS BEEN VERIFIER, THE WAFER ZS RELEASEP FOR PURTHER TES TineWager soRT” SSeS eae —_——, Figure 16.1 Visualization of wafer testing ° AFIER A GbOP PROCESS HAS BEEN VERIPEP, EACH INPLVIPVAL CHIP MUST BE CHECKEP | > A “TEST PROBE” LS VSEP To MAKE CONTACT ‘Jo Ech CHEP, ONE AT A TIME —> A FEW SIMPLE ELECTRICAL TESTs ARE RUM, (w3TLy PE eR Low SPEEP SESNALs) TO CHECK POR GROSS DEFECTs (66s, PROCESS PEFECE) —> BAP PLE ARE MARKEY WITH AN INE VOT CIN KEP” 5 > SOMETIMES SIMPLE JRIMs ARE PERFERMEP PURING WAFER SORT (6.61, BANPSAP TRIM) ° AFTER BAP CHIPs HAVE BEEN ZPENTIFIEP AT PROBE, THE WAFER IS “SCRIBE” OR “Saylép” INTO LNVLVZPUAL VLE, ANP THE G00P CAL Ps SEPARATE FOR FURTHER TESTING * S0mME TIMES A WAFER MAP” IS CREATEP) SpO0 TIC THE LOCATIONS OF All. BAP PLE) OR EVEN UNZQVELY LPENTIEYENE ALL pre > CAN ASSISS BW PERGCHEP TESTING ° AFTER WAFER SORT, THE RESVLTING GooP CHEPs PRE PACKACEP ° THE PACKAGE? CHIPS ARE THEN TESTE? Te SEE LP THEY MEET ALL SPeLPE CATIONS , YSING HIGH SPEEP “ATE” (*Avioarze Test Eavipnens) —?+ A KEY PART oF THE COST OF A CHFP ZS THE FEST cost —+> Lets OF EFFORT OFTEN GOES INTO REPVCLNS TEST TIME , To REPUCE COST © “TEST VECTORS” ARE INPUT To THE CPEP, ANP THE OUTPUTS ARE CHECKEP TO VERIFY THAT THE CHIP LS FUNCTIONAL ANP MEETS PILL. SPECLPL CATIONS —> "TEST VECTORs” ARE ARRAYS OF BENARY INPUTS —» “TEST VECTOR GENERATLON” TS THE TASK OF CREATING A SET OF VECTORS 70 CHECK THE OPERATION OF THE CHIP —» “FUNCTLINAL TESTING” PLRECTLY CHECKS THE FUNCTZONS OF THE CHIP (TEST COVERAGE” [Convene] bor Vectors ‘noe OF > Wh LS outputs PESEREP ( >90% ome ae OF ALL GATES — VERIPLEV soe?) responses} Figure 16,5 Overview of the testing problem