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Preface

Notebook Computer E4120 / E4121-C / E4125-C / E4121D-C Service Manual


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Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent vendor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication. This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publication, except for copies kept by the user for backup purposes. Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement of that product or its manufacturer. Version 1.0 March 2010

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Trademarks
Intel, Celeron and Intel Core are trademarks of Intel Corporation. Windows is a registered trademark of Microsoft Corporation. Other brand and product names are trademarks and/or registered trademarks of their respective companies.

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About this Manual


This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and inspection of personal computers. It is organized to allow you to look up basic information for servicing and/or upgrading components of the E4120 / E4121-C / E4125-C / E4121D-C series notebook PC. The following information is included: Chapter 1, Introduction, provides general information about the location of system elements and their specifications. Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade elements of the system. Appendix A, Part Lists Appendix B, Schematic Diagrams

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IMPORTANT SAFETY INSTRUCTIONS


Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to persons when using any electrical equipment:
1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet basement or near a swimming pool. 2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of electrical shock from lightning. 3. Do not use the telephone to report a gas leak in the vicinity of the leak. 4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may explode. Check with local codes for possible special disposal instructions. 5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output of 19V, 3.42A OR 18.5V, 3.5A (65 Watts) minimum AC/DC Adapter.

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CAUTION
Always disconnect all telephone lines from the wall outlet before servicing or disassembling this equipment.

TO REDUCE THE RISK OF FIRE, USE ONLY NO. 26 AWG OR LARGER, TELECOMMUNICATION LINE CORD
This Computers Optical Device is a Laser Class 1 Product

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Instructions for Care and Operation


The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:
1. Dont drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer to any shock or vibration. Do not place it on an unstable surface. Do not place anything heavy on the computer.

2.

Keep it dry, and dont overheat it. Keep the computer and power supply away from any kind of heating element. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not expose it to excessive heat or direct sunlight. Do not leave it in a place where foreign matter or moisture may affect the system. Dont use or store the computer in a humid environment. Do not place the computer on any surface which will block the vents.

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3.

Follow the proper working procedures for the computer. Shut the computer down properly and dont forget to save your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power until you properly shut down all programs. Do not turn off any peripheral devices when the computer is on. Do not disassemble the computer by yourself. Perform routine maintenance on your computer.

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4. 5. Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage your data. Take care when using peripheral devices.
Use only approved brands of peripherals. Unplug the power cord before attaching peripheral devices.

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Power Safety
The computer has specific power requirements:
Only use a power adapter approved for use with this computer. Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are unsure of your local power specifications, consult your service representative or local power company. The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one. When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire. Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices. Before cleaning the computer, make sure it is disconnected from any external power supplies.
Do not plug in the power cord if you are wet. Do not use the power cord if it is broken. Do not place heavy objects on the power cord.

Power Safety Warning Before you undertake any upgrade procedures, make sure that you have turned off the power, and disconnected all peripherals and cables (including telephone lines). It is advisable to also remove your battery in order to prevent accidentally turning the machine on.

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Battery Precautions
Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer. Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire. Recharge the batteries using the notebooks system. Incorrect recharging may make the battery explode. Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service personnel. Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode or leak if exposed to fire, or improperly handled or discarded. Keep the battery away from metal appliances. Affix tape to the battery contacts before disposing of the battery. Do not touch the battery contacts with your hands or metal objects.

Battery Guidelines
The following can also apply to any backup batteries you may have. If you do not use the battery for an extended period, then remove the battery from the computer for storage. Before removing the battery for storage charge it to 60% - 70%. Check stored batteries at least every 3 months and charge them to 60% - 70%.

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Battery Disposal The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under various state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste officials for details in your area for recycling options or proper disposal. Caution Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer. Discard used battery according to the manufacturers instructions.

Battery Level
Click the battery icon in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10% will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.

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Related Documents
You may also need to consult the following manual for additional information: Users Manual on CD This describes the notebook PCs features and the procedures for operating the computer and its ROM-based setup program. It also describes the installation and operation of the utility programs provided with the notebook PC.

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Contents
Introduction ..............................................1-1
Overview .........................................................................................1-1 System Specifications .....................................................................1-2 External Locator - Top View with LCD Panel Open ......................1-4 External Locator - Front & Right side Views .................................1-5 External Locator - Left Side & Rear View .....................................1-6 External Locator - Bottom View .....................................................1-7 Mainboard Overview - Top (Key Parts) .........................................1-8 Mainboard Overview - Bottom (Key Parts) ....................................1-9 Mainboard Overview - Top (Connectors) .....................................1-10 Mainboard Overview - Bottom (Connectors) ...............................1-11

Part Lists ..................................................A-1


Part List Illustration Location ........................................................ A-2 Top (E4120 / E4121-C / E4121D-C) ............................................. A-3 Top (E4125) ................................................................................... A-4 Bottom ........................................................................................... A-5 LCD (E4120 / E4121-C) ................................................................ A-6 LCD (E4125) ................................................................................. A-7 LCD (E4121D-C) .......................................................................... A-8 HDD ............................................................................................... A-9 Blu-Ray Combo ........................................................................... A-10 DVD-Super Multi Drive .............................................................. A-11

Disassembly ...............................................2-1
Overview .........................................................................................2-1 Maintenance Tools ..........................................................................2-2 Connections .....................................................................................2-2 Maintenance Precautions .................................................................2-3 Disassembly Steps ...........................................................................2-4 Removing the Battery ......................................................................2-5 Removing the Hard Disk Drive .......................................................2-6 Removing the Optical (CD/DVD) Device ......................................2-8 Removing the System Memory (RAM) ..........................................2-9 Removing and Installing the Processor .........................................2-11 Removing the Wireless LAN Module ...........................................2-14 Removing the 3.75G Module ........................................................2-15 Removing the Modem ...................................................................2-16 Removing the Bluetooth Module ..................................................2-17 Removing the LCD Back Cover (for E4121D-C only) .................2-18 Removing the LCD Front Cover ...................................................2-20 Removing the Keyboard ................................................................2-21

Schematic Diagrams................................. B-1


System Block Diagram ...................................................................B-2 Clock Generator ..............................................................................B-3 Processor 1/7 ...................................................................................B-4 Processor 2/7 ...................................................................................B-5 Processor 3/7 ...................................................................................B-6 Processor 4/7 ...................................................................................B-7 Processor 5/7 ...................................................................................B-8 Processor 6/7 ...................................................................................B-9 Processor 7/7 .................................................................................B-10 DDRIII SO-DIMM_0 ...................................................................B-11 DDRIII SO-DIMM_1 ...................................................................B-12 LVDS, Inverter .............................................................................B-13 HDMI, CRT ..................................................................................B-14 IBEXPEAK - M 1/9 ......................................................................B-15 IBEXPEAK - M 2/9 ......................................................................B-16 IBEXPEAK - M 3/9 ......................................................................B-17 IBEXPEAK - M 4/9 ......................................................................B-18 IX

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Preface IBEXPEAK - M 5/9 ..................................................................... B-19 IBEXPEAK - M 6/9 ..................................................................... B-20 IBEXPEAK - M 7/9 ..................................................................... B-21 IBEXPEAK - M 8/9 ..................................................................... B-22 IBEXPEAK - M 9/9 ..................................................................... B-23 New Card, Mini PCIE .................................................................. B-24 CCD, 3G, TPM ............................................................................. B-25 Card Reader, LAN (JMB251) ...................................................... B-26 LAN (JMC251), SATA HDD, ODD ........................................... B-27 Audio Codec VIA 1812 ................................................................ B-28 KBC-ITE IT8502E ....................................................................... B-29 LED, MDC, BT ............................................................................ B-30 USB, Fan, TP, Multi Con1 ........................................................... B-31 5VS, 3VS, 1.05VS ........................................................................ B-32 Power 3.3V/5V ............................................................................. B-33 Power 1.5V/0.75V/1.8VS ............................................................. B-34 Power 1.1VS_VTT ....................................................................... B-35 Power VGFX_CORE ................................................................... B-36 V-Core .......................................................................................... B-37 DC-In, Charger ............................................................................. B-38 Click Board .................................................................................. B-39 Audio / USB / RJ11 Board ........................................................... B-40 Power Switch & LID Board ......................................................... B-41

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Introduction

Chapter 1: Introduction
Overview
This manual covers the information you need to service or upgrade the E4120 / E4121-C / E4125-C / E4121D-C series notebook computer. Information about operating the computer (e.g. getting started, and the Setup utility) is in the Users Manual. Information about drivers (e.g. VGA & audio) is also found in Users Manual. That manual is shipped with the computer. Operating systems (e.g. Windows 7, Windows Vista, etc.) have their own manuals as do application software (e.g. word processing and database programs). If you have questions about those programs, you should consult those manuals.

1.Introduction

The E4120 / E4121-C / E4125-C / E4121D-C series notebook is designed to be upgradeable. See Disassembly on page 2 - 1 for a detailed description of the upgrade procedures for each specific component. Please note the warning and safety information indicated by the symbol. The balance of this chapter reviews the computers technical specifications and features.

Overview 1 - 1

Introduction

System Specifications
Processor
Intel Core i7-620M Processor: (2.66GHz) 32nm (32 Nanometer) Process Technology, 4MB L2 Cache & 1066MHz FSB - TDP 35W rPGA988A Socket P Package Intel Core i5-540M Processor: (2.53GHz) 32nm (32 Nanometer) Process Technology, 3MB L2 Cache & 1066MHz FSB - TDP 35W rPGA988A Socket P Package

Core Logic
Intel HM55 Chipset

Keyboard & Pointing Device


Isolated WinKey Keyboard Built-in TouchPad with Multi-Gesture Functionality

Display
14.0 / 35.56cm 16:9 HD (1366 * 768)

Interface
Three USB 2.0 Ports One External Monitor Port One HDMI Out Port One Headphone-Out Jack One Microphone-In Jack One RJ-45 LAN Jack One RJ-11 Modem Jack One DC-In Jack

Memory
Dual Channel DDRIII (DDR3) Two 204 Pin SO-DIMM sockets supporting DDR3 1066 MHz Memory Expandable up to 4GB (using 2GB SO-DIMM Modules)

1.Introduction

Intel Core i5-520M Processor: (2.4GHz) 32nm (32 Nanometer) Process Technology, 3MB L2 Cache & 1066MHz FSB - TDP 35W rPGA988A Socket P Package Intel Core i5-430M Processor: (2.26GHz) 32nm (32 Nanometer) Process Technology, 3MB L2 Cache & 1066MHz FSB, - TDP 35W rPGA988A Socket P Package Intel Core i3-350M Processor: (2.26GHz) 32nm (32 Nanometer) Process Technology, 3MB L2 Cache & 1066MHz FSB - TDP 35W rPGA988A Socket P Package Intel Core i3-330M Processor: (2.13GHz) 32nm (32 Nanometer) Process Technology, 3MB L2 Cache & 1066MHz FSB - TDP 35W rPGA988A Socket P Package

Video
Intel HM55 Integrated Video: High Preference 3D/2D Graphic Accelerator Shared Memory Architecture of up to 1748MB Supports Microsoft DirectX10 Compatible

Card Reader
Embedded 7-in-1 Card Reader (MS/ MS Pro/ SD/ Mini SD/ MMC/ RS MMC/ MS Duo) Note: MS Duo/ Mini SD/ RS MMC Cards require a PC adapter

BIOS
One 32Mbit SPI Flash ROM Phoenix BIOS

Slots
One ExpressCard 34 Slot Supporting USB & PCIe Interfaces Two Mini-Card Slots with PCIe (Slot 1) & USB (Slot 2) interface: Slot 1 for WLAN Module (Factory Option) Slot 2 for 3.75G Module (Factory Option)

Storage
One Changeable 12.7mm(h) Super Multi/Blu-

ray Combo Optical Device Drive with SATA Interface One Changeable 2.5" / 9.5 mm (h) HDD with SATA (Serial) Interface

Audio
High Definition Audio Interface 3D Enhanced Stereo System Built-In Microphone 2 * Built-In Speakers

1 - 2 System Specifications

Introduction
Communication
56K Fax/Modem Built-In 10/100/1000Mb Base-TX Ethernet LAN Intel WiFi Link 1000 (802.11 b/g/n) Half MiniCard PCIe WLAN Module (Factory Option) 3rd Party WLAN 802.11b/g/n Half Mini-Card Module with PCIe Interface(Option) Bluetooth 2.1 + EDR (Enhanced Data Rate) Module (Factory Option) 1.3M Pixel PC Camera Module with USB interface (Factory Option) UMTS/HSPDA-based 3.75G Module with USB Half Mini-Card Interface (Factory Option) Quad-band GSM/GPRS (850 MHz, 900 MHz, 1800 MHz, 1900 MHz) UMTS WCDMA FDD (2100 MHz) Note that UMTS modes CAN NOT be used in North America

Security
Security (Kensington Type) Lock Slot BIOS Password

Operating System
Windows Vista (with Service Pack 2) Windows 7

Design Feature
IMR Changeable LCD Back Covers (Factory Option)

Environmental Spec

1.Introduction

Temperature Operating: Non-Operating: Relative Humidity Operating: Non-Operating:

5C - 35C -20C - 60C 20% - 80% 10% - 90%

Power Management
Supports Wake on LAN Supports Wake on USB

Dimensions & Weight


340mm (w) * 238mm (d) * 15.6 - 35.2mm (h) 2.2 kg with 6 Cell Battery & ODD

Power
Full Range AC/DC Adapter AC input 100 - 240V, 50 - 60Hz, DC Output 19V, 3.42A or 18.5V, 3.5A (65 Watts) Removable 6 Cell Smart Lithium Ion Battery Pack 48.84WH (Factory Option) Removable 6 Cell Smart Lithium Ion Battery Pack 62.16WH

System Specifications 1 - 3

Introduction Figure 1
Top View 1. Optional Built-In PC Camera 2. LCD 3. Power Button 4. Hot Key Buttons 5. LED Status Indicators 6. Keyboard 7. Built-In Microphone 8. Touchpad & Buttons 1

External Locator - Top View with LCD Panel Open

1.Introduction

7 8

1 - 4 External Locator - Top View with LCD Panel Open

Introduction

External Locator - Front & Right side Views

Figure 2
Front Views 1. LED Power Indicators

1.Introduction

Figure 3
Right Side Views 1. Microphone-In Jack 2. Headphone-Out Jack 3. USB 2.0 Port 4. RJ-11 Phone Jack 5. Optical Device Drive Bay 6. Security Lock Slot

External Locator - Front & Right side Views 1 - 5

Introduction

External Locator - Left Side & Rear View


Figure 4
Left Side View 1. DC-In Jack 2. External Monitor Port 3. RJ-45 LAN Jack 4. HDMI-Out Port 5. Vent/Fan Intake/ Outlet 6. 2 * USB 2.0 Ports 7. ExpressCard Slot 8. 7-in-1 Card Reader

7 8

1.Introduction

Figure 5
Rear View 1. Battery 1

1 - 6 External Locator - Left Side & Rear View

Introduction

External Locator - Bottom View


Figure 6
Bottom View 1. Battery 2. Component Bay Cover 3. Vent/Fan Intake/ Outlet 4. Hard Disk Bay Cover 5. 3.75G/HSPA USIM Card Cover (optional)

1 3

1.Introduction

2 3

2 3

WITHOUT 3G

WITH 3G

Overheating To prevent your computer from overheating make sure nothing blocks the vent/fan intakes while the computer is in use.

External Locator - Bottom View 1 - 7

Introduction Figure 7
Mainboard Top Key Parts 1. ExpressCard Connector 2. JMC251 3. KBC ITE IT8512E 1

Mainboard Overview - Top (Key Parts)

1.Introduction

3 3

1 - 8 Mainboard Overview - Top (Key Parts)

Introduction

Mainboard Overview - Bottom (Key Parts)

Figure 8
Mainboard Bottom Key Parts 1. CPU Socket (no CPU installed) 2. Memory Slots DDR3 SO-DIMM 3. Intel HM55 4. Mini-Card Connector (3G Module) 5. Audio Codec 6. Mini-Card Connector (WLAN Module) 7. Card Reader Socket

1.Introduction

1 3

2 4

Mainboard Overview - Bottom (Key Parts) 1 - 9

Introduction Figure 9
Mainboard Top Connectors 1. USB Port 2. Microphone Cable Connector 3. Audio Cable Connector 4. TouchPad Cable Connector 5. Keyboard Cable Connector 1 1

Mainboard Overview - Top (Connectors)

1.Introduction

9 2 10

5 4

11

7 3

1 - 10 Mainboard Overview - Top (Connectors)

Introduction

Mainboard Overview - Bottom (Connectors)

Figure 10
Mainboard Bottom Connectors 1. CCD Connector 2. LCD Cable Connector 3. CMOS Cable Connector 4. BT Cable Connector 5. ODD Connector 6. HDD Connector 7. MDC Cable Connector 8. Fan Cable Connector 7

1 2 8

1.Introduction

4 5 6

Mainboard Overview - Bottom (Connectors) 1 - 11

Introduction

1.Introduction
1 - 12

Disassembly

Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the E4120 / E4121-C / E4125-C / E4121D-C series notebooks parts and subsystems. When it comes to reassembly, reverse the procedures (unless otherwise indicated). We suggest you completely review any procedure before you take the computer apart. Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the Users Manual but are repeated here for your convenience. To make the disassembly process easier each section may have a box in the page margin. Information contained under the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the disassembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previous disassembly procedure. The amount of screws you should be left with will be listed here also. A box with a will also provide any possible helpful information. A box with a contains warnings. An example of these types of boxes are shown in the sidebar.

2.Disassembly

Information

Warning

Overview 2 - 1

Disassembly NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the battery is removed too).

Maintenance Tools
The following tools are recommended when working on the notebook PC:
M3 Philips-head screwdriver M2.5 Philips-head screwdriver (magnetized) M2 Philips-head screwdriver Small flat-head screwdriver Pair of needle-nose pliers Anti-static wrist-strap

2.Disassembly

Connections
Connections within the computer are one of four types:
Locking collar sockets for ribbon connectors To release these connectors, use a small flat-head screwdriver to gently pry the locking collar away from its base. When replacing the connection, make sure the connector is oriented in the same way. The pin1 side is usually not indicated. To release this connector type, grasp it at its head and gently rock it from side to side as you pull it out. Do not pull on the wires themselves. When replacing the connection, do not try to force it. The socket only fits one way. To release these connectors, use a small pair of needle-nose pliers to gently lift the connector away from its socket. When replacing the connection, make sure the connector is oriented in the same way. The pin1 side is usually not indicated. To separate the boards, gently rock them from side to side as you pull them apart. If the connection is very tight, use a small flat-head screwdriver - use just enough force to start.

Pressure sockets for multi-wire connectors

Pressure sockets for ribbon connectors

Board-to-board or multi-pin sockets

2 - 2 Overview

Disassembly

Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a removal and/or replacement job, take the following precautions:
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other components could be damaged. 2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. 3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage components and/or data. You should also monitor the position of magnetized tools (i.e. screwdrivers). 4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged. 5. Be careful with power. Avoid accidental shocks, discharges or explosions. Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire. 6. Peripherals Turn off and detach any peripherals. 7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity. Before handling any part in the computer, discharge any static electricity inside the computer. When handling a printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that you use an anti-static wrist strap instead. 8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands produce oils which can attract corrosive elements. 9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted to charged surfaces, reducing performance. 10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as screws, loose inside the computer.

Power Safety Warning Before you undertake any upgrade procedures, make sure that you have turned off the power, and disconnected all peripherals and cables (including telephone lines). It is advisable to also remove your battery in order to prevent accidentally turning the machine on.

2.Disassembly

Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth. Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.

Overview 2 - 3

Disassembly

Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM THE DISASSEMBLY STEPS IN THE ORDER INDICATED.

To remove the Battery:


1. Remove the battery page 2 - 5 page 2 - 5 page 2 - 6 page 2 - 5 page 2 - 8 page 2 - 5 page 2 - 9 page 2 - 5 page 2 - 11 page 2 - 13 page 2 - 5 page 2 - 14 page 2 - 5 page 2 - 15

To remove the Modem:


1. Remove the battery 2. Remove the modem page 2 - 5 page 2 - 16 page 2 - 5 page 2 - 17 page 2 - 5 page 2 - 18 page 2 - 5 page 2 - 20 page 2 - 5 page 2 - 21

To remove the HDD:


1. Remove the battery 2. Remove the HDD

To remove the Bluetooth Module:


1. Remove the battery 2. Remove the Bluetooth 1. Remove the battery 2. Remove the LCD Back Cover

2.Disassembly

To remove the Optical Device:


1. Remove the battery 2. Remove the Optical device

To remove the LCD Back Cover (E4121D-C):

To remove the System Memory:


1. Remove the battery 2. Remove the system memory 1. Remove the battery 2. Remove the processor 3. Install the processor

To remove the LCD Front Cover:


1. Remove the battery 2. Remove the LCD Front Cover

To remove and install a Processor:

To remove the Keyboard:


1. Remove the battery 2. Remove the keyboard

To remove the WLAN Module:


1. Remove the battery 2. Remove the wireless LAN

To remove the 3.75G Module:


1. Remove the battery 2. Remove the 3.75G

2 - 4 Disassembly Steps

Disassembly

Removing the Battery


1. 2. 3. 4. Turn the computer off, and turn it over. Slide the latch 1 in the direction of the arrow. Slide the latch 2 in the direction of the arrow, and hold it in place. 3 in the direction of the arrow 4 . Slide the battery 6

Figure 1
Battery Removal
a. Slide the latch and hold in place. b. Slide the battery in the direction of the arrow.

a. 2 1

2.Disassembly

b. 3

3. Battery

Removing the Battery 2 - 5

Disassembly

Removing the Hard Disk Drive


Figure 2
HDD Assembly Removal
a. Locate the HDD bay cover and remove the screw(s).

The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm (h). Follow your operating systems installation instructions, and install all necessary drivers and utilities (as outlined in Chapter 4 of the Users Manual) when setting up a new hard disk.

Hard Disk Upgrade Process


1. Turn off the computer, and remove the battery (page 2 - 5). 2. Locate the hard disk bay cover and remove screws 1 & 2 . a.

2.Disassembly

HDD System Warning

2 Screws

New HDDs are blank. Before you begin make sure: You have backed up any data you want to keep from your old HDD. You have all the CD-ROMs and FDDs required to install your operating system and programs. If you have access to the internet, download the latest application and hardware driver updates for the operating system you plan to install. Copy these to a removable medium.

2 - 6 Removing the Hard Disk Drive

Disassembly
3. 4. 5. 6. 7.
3. Remove the hard disk bay cover 6 Grip the tab and slide the hard disk in the direction of arrow 4 . Lift the hard disk out of the bay 5 . Remove the screw 6 - 9 and the adhesive cover 10 from the hard disk 11 . Reverse the process to install a new hard disk (do not forget to replace all the screws and covers).

Figure 3
HDD Assembly Removal (contd.)
b. Remove the HDD bay cover. c. Grip the tab and slide the HDD in the direction of the arrow. d. Lift the HDD assembly out of the bay. e. Remove the screw and adhesive cover.

b.

d.

2.Disassembly

5 3

e. c. 8 4

9 6 10 7

11
3. HDD Bay Cover 10. Adhesive Cover 11. HDD

4 Screws

Removing the Hard Disk Drive 2 - 7

Disassembly Figure 4
Optical Device Removal
a. Remove the screws. b. Remove the cover. c. Remove the screw and push the optical device out off the computer at point 8.

Removing the Optical (CD/DVD) Device


1. 2. 3. 4. 5. 6. Turn off the computer, and remove the battery (page 2 - 5). Locate the RAM & CPU bay cover 1 , and remove screws 2 - 5 . Carefully (a fan and cable are attached to the under side of the cover) lift up the bay cover. Carefully disconnect the fan cable 6 , and remove the cover 1 . Remove the screw at point 7 , and use a screwdriver to carefully push out the optical device 9 at point 8 . Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The screw holes should line up). 7. Restart the computer to allow it to automatically detect the new device. a. 2 3 1 4 5 7 8 c.

2.Disassembly

b.

1. Component Bay Cover 9. Optical Device

1 9 6

5 Screws

2 - 8 Removing the Optical (CD/DVD) Device

Disassembly

Removing the System Memory (RAM)


The computer has two memory sockets for 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting DDR3 1066MHz. The main memory can be expanded up to 8GB. The SO-DIMM modules supported are 1GB, 2GB and 4GB and DDRIII Modules. The total memory size is automatically detected by the POST routine once you turn on your computer.

Figure 5
RAM Module Removal
a. Locare the memory socket. b. Pull the release latch(es). c. Remove the module(s).

Memory Upgrade Process


1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 8). 2. The RAM module (s) will be visible at point 1 on the main board. 3. Gently pull the two release latches ( 2 & 3 ) on the sides of the memory socket in the direction indicated by the arrows (Figure 6c). a. b. 2 1 4 c.

Contact Warning Be careful not to touch the metal pins on the modules connecting edge. Even the cleanest hands have oils which can attract particles, and degrade the modules performance.

2.Disassembly

The RAM module(s) 4 will pop-up (Figure 6d), and you can then remove it. Pull the latches to release the second module if necessary. Insert a new module holding it at about a 30 angle and fit the connectors firmly into the memory slot. The modules pin alignment will allow it to only fit one way. Make sure the module is seated as far into the slot as it will go. DO NOT FORCE the module; it should fit without much pressure. 8. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.

4. 5. 6. 7.

4. RAM Module

Removing the System Memory (RAM) 2 - 9

Disassembly
9. Replace the bay cover and screws (make sure you reconnect the fan cable before screwing down the bay cover). Note that there are four 5 - 8 cover pins which need to be aligned with slots in the case, to insure a proper cover fit, before screwing down the bay cover. d.
5

Figure 6
RAM Module Removal (contd.)
d. Properly re-insert bay cover pins. the

2.Disassembly

10. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.

2 - 10 Removing the System Memory (RAM)

Disassembly

Removing and Installing the Processor


Processor Removal Procedure
1. Turn off the computer, remove the battery (page 2 - 5), and the component bay cover (page 2 - 9). 2. Loosen the CPU heat sink screws in the order 3 , 2 & 1 (the reverse order as indicated on the label). 3. Carefully lift up the heat sink 4 (Figure 7c) off the computer.
a.

Figure 7
Processor Removal
a. Remove the cover and Iocate the heat sink. b. Loosen the screws in the order indicated. c. Remove the heat sink.

2.Disassembly

CPU Warning In order to prevent damaging the contact pins when removing the CPU, it is necessary to first remove the WLAN module from the computer.

b.

c.

1 4 2 3

4. Heat Sink

Note: Loosen the screws in the reverse order 3, 2, 1 as indicated on the label.

3 Screws

Removing and Installing the Processor 2 - 11

Disassembly
4. 5. 6. 7. Turn the release latch 6 towards the unlock symbol , to release the CPU (Figure 8a). Carefully (it may be hot) lift the CPU 7 up out of the socket (Figure 8b). See page 2 - 13 for information on inserting a new CPU. When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!). d.

Figure 8
Processor Removal (contd)
d. Turn the release latch to unlock the CPU. e. Lift the CPU out of the socket.

6 6

2.Disassembly

Unlock e.

Lock

7
Caution The heat sink, and CPU area in general, contains parts which are subject to high temperatures. Allow the area time to cool before removing these parts.

7. CPU

2 - 12 Removing and Installing the Processor

Disassembly

Processor Installation Procedure


1. Insert the CPU A , pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!), and turn the release latch B towards the lock symbol (Figure 9b). 2. Remove the sticker C (Figure 9c) from the heat sink. 3. Insert the heat sink D as indicated in Figure 9c. 4. Tighten the CPU heat sink screws in the order 1 , 2 & 3 (the order as indicated on the label and Figure 9d). 5. Replace the component bay cover and tighten the screws (page 2 - 11). a. A c.

Figure 9
Processor Installation
a. Insert the CPU. b. Turn the release latch towards the lock symbol. c. Remove the sticker from the heat sink and insert the heat sink. d. Tighten the screws.

2.Disassembly

b.

d. 1 2 B 3

Note: Tighten the screws in the order 1, 2, 3 as indicated on the label.

A. CPU D. Heat Sink

3 Screws

Removing and Installing the Processor 2 - 13

Disassembly

Figure 10
Wireless LAN Module Removal
a. Remove the cover. b. Disconnect the cables and remove the screw. c. Lift the WLAN module out.

Removing the Wireless LAN Module


1. 2. 3. 4. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 9). The Wireless LAN module will be visible at point 1 on the mainboard. Carefully disconnect cables 2 - 3 , then remove screw 4 from the module socket. Lift the Wireless LAN module 5 (Figure 11d) up and off the computer. a. c.

2.Disassembly

b. 4 3

5. WLAN Module.

2 1 Screw

2 - 14 Removing the Wireless LAN Module

Disassembly

Removing the 3.75G Module


1. 2. 3. 4. 5. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 9). The 3.75G module will be visible at point 1 on the mainboard. Carefully disconnect the cable 2 , then remove the screw 3 from the module socket. The 3.75G module 4 will pop-up. Lift the 3.75G module (Figure 11d) up and off the computer. a.

Figure 11
3.75G Module Removal
a. Remove the cover. b. Disconnect the cable and remove the screw. c. The 3.75G module will pop up. d. Lift the 3.75G module out.

2.Disassembly

d. 1

b.

c.

4 2 3 4 1 Screw
4. 3.75G Module.

Removing the 3.75G Module 2 - 15

Disassembly

Figure 12
Modem Removal
a. Locate the modem. b. Remove the screws and disconnect the cable. c. Lift the modem up and off the sockets.

Removing the Modem


1. 2. 3. 4. Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 9). The modem will be visible at point 1 on the mainboard. Remove the screws 2 - 3 and disconnect the cable 4 . Carefully lift the modem 6 up and off the socket 5 . a. c.

2.Disassembly

b. 2

6. Modem

6 4 3

2 Screws

2 - 16 Removing the Modem

Disassembly

Removing the Bluetooth Module


1. 2. 3. 4. 5. Turn off the computer, remove the battery (page 2 - 5), and component bay cover (page 2 - 9). The Bluetooth module will be visible at point 1 on the mainboard. Remove the screw 2 and turn the module over. Carefully disconnect the cable 3 and separate the connector 4 (Figure 13b) from the Bluetooth Module. Lift the Bluetooth module 5 (Figure 13c) up and off the computer. a. d.

Figure 13
Bluetooth Module Removal
a. Locate the Bluetooth module. b. Remove the screw. c. Disconnect the cable and the connector from the Bluetooth module. d. Lift the Bluetooth module out.

2.Disassembly

b.

c. 4

3 2

5. Bluetooth Module

1 Screw

Removing the Bluetooth Module 2 - 17

Disassembly

Removing the LCD Back Cover (for E4121D-C only)


Figure 14
LCD Back Cover Removal
a. Remove the rubber covers and screws. b. Slide the cover forward. c. Remove the LCD back cover.

1. Turn off the computer, and turn the computer over to remove the battery (page 2 - 5). 2. Open the LCD and carefully remove the rubber screw covers 1 & 2 (2 corner rubber screw covers only) and set them aside. 3. Remove screws 3 & 4 from the front cover. 4. Carefully slide the cover forward in the direction of the arrows 5 & 6 as illustrated below. 5. Remove the LCD back cover 7 . a. b. 5 6

1 3

2 4

2.Disassembly

c.

7. LCD Back Cover

Rubber Screw Covers After removing the rubber screw covers, place them on a clean dry surface (or attach them to the front cover itself) in order to prevent loss of adhesive.

2 Screws

2 - 18 Removing the LCD Back Cover (for E4121D-C only)

Disassembly
6. Align the replacement cover with the dotted line 8 as illustrated below (and as marked on the cover).

Figure 15
LCD Back Cover Removal (contd)

d. 8

d. Align the replacement cover and slide forward to click firmly into place.

10 9

10

2.Disassembly

10 7. Slide the back cover forward until it clicks firmly into place 9 . 8. Run your hands around the sides and front of the cover 10 to make sure it is firmly aligned in place (carefully press down to make sure the fit is secure). 9. Replace the screws and rubber covers.

Removing the LCD Back Cover (for E4121D-C only) 2 - 19

Disassembly Figure 16
LCD Front Cover Removal
a. Remove the screws and unsnap the LCD front cover from the LCD panel. b. Slide the LCD panel cover in the direction of the arrow.

Removing the LCD Front Cover


1. Turn off the computer, and remove the battery (page 2 - 5), and remove the LCD back cover (page 2 - 18). 2. Remove the rubber covers and screws 1 - 4 (Figure 16a), then run your finger around the middle of the frame to carefully unsnap the LCD front cover 5 from the LCD panel. 3. After unsnapping all four sides of the LCD front cover, carefully slide the LCD front cover downwards in the direction of the arrow 6 (be careful of the LCD hinges at point 7 ). 4. You can now remove the LCD front cover. a. b. 5

2.Disassembly

6 1 5 4 7 7

5. LCD Front Cover

Rubber Screw Covers After removing the rubber screw covers, place them on a clean dry surface (or attach them to the front cover itself) in order to prevent loss of adhesive.

4 Screws

2 - 20 Removing the LCD Front Cover

Disassembly

Removing the Keyboard


1. Turn off the computer, and remove the battery (page 2 - 5). 2. Press the four keyboard latches at the top of the keyboard to elevate the keyboard from its normal position (you may need to use a small screwdriver to do this). 3. Carefully lift the keyboard up, being careful not to bend the keyboard ribbon cable (Figure 17b). 4. Disconnect the keyboard ribbon cable 5 from the locking collar socket 6 . 5. Carefully lift up the keyboard 7 (Figure 17c) off the computer. a. 1 2 3 4 c.

Figure 17
Keyboard Removal
a. Press the four latches to release the keyboard. b. Lift the keyboard up and disconnect the cable from the locking collar. c. Remove the keyboard.

2.Disassembly

Re-Inserting the Keyboard

b. 5 6

When re-inserting the keyboard firstly align the four keyboard tabs at the bottom of the keyboard with the slots in the case.

Keyboard Tabs
7. Keyboard

Removing the Keyboard 2 - 21

Disassembly

2.Disassembly
2 - 22

Part Lists

Appendix A: Part Lists


This appendix breaks down the E4120 / E4121-C / E4125-C / E4121D-C series notebooks construction into a series of illustrations. The component part numbers are indicated in the tables opposite the drawings. Note: This section indicates the manufacturers part numbers. Your organization may use a different system, so be sure to cross-check any relevant documentation. Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the total number of duplicated parts used. Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.

A.Part Lists

A - 1

Part Lists

Part List Illustration Location


The following table indicates where to find the appropriate part list illustration. Table A- 1
Part List Illustration Location
Parts Top Bottom E4120 page A - 3 page A - 5 page A - 7 page A - 9 page A - 10 page A - 11 page A - 7 page A - 8 E4121-C E4125-C page A - 4 E4121D-C page A - 3

A.Part Lists

LCD HDD Blu-Ray Combo DVD-Super Multi Drive

A - 2 Part List Illustration Location

Part Lists

Top (E4120 / E4121-C / E4121D-C)

Figure A - 1
Top (E4120 / E4121-C)

A.Part Lists

()

Top (E4120 / E4121-C / E4121D-C) A - 3

Part Lists

Top (E4125)

Figure A - 2

A.Part Lists

Top (E4125)

()

A - 4 Top (E4125)

Part Lists

Bottom

Figure A - 3
Bottom

A.Part Lists

Bottom A - 5

Part Lists

LCD (E4120 / E4121-C)

Figure A - 4

A.Part Lists

LCD (E4120 / E4121-C)



/

()
()

()

A - 6 LCD (E4120 / E4121-C)

Part Lists

LCD (E4125)

Figure A - 5

LCD (E4125)

A.Part Lists

()
()

/
/

()

FOR C4801M
FOR C4801M-C FOR E4121D-C

FOR MOFA
FOR C4801M-C FOR E4121D-C

FOR E4121D-C
FOR E4121M/D-C FOR C4801M/-C

LCD (E4125) A - 7

Part Lists

LCD (E4121D-C)

Figure A - 6

A.Part Lists

LCD (E4121D-C)

()
()

/
/

()

FOR C4801M
FOR C4801M-C FOR E4121D-C

FOR MOFA
FOR C4801M-C FOR E4121D-C

FOR E4121D-C
FOR E4121M/D-C FOR C4801M/-C

A - 8 LCD (E4121D-C)

Part Lists

HDD

Figure A - 7
HDD

A.Part Lists

()

HDD A - 9

Part Lists

Blu-Ray Combo

Figure A - 8

A.Part Lists

Blu-Ray Combo

*()

A - 10 Blu-Ray Combo

Part Lists

DVD-Super Multi Drive

Figure A - 9
DVD-Super Multi Drive

A.Part Lists

*()

DVD-Super Multi Drive A - 11

Part Lists

A.Part Lists
A - 12

Schematic Diagrams

Appendix B: Schematic Diagrams


This appendix has circuit diagrams of the E412P-C notebooks PCBs. The following table indicates where to find the appropriate schematic diagram.
Diagram - Page
System Block Diagram - Page B - 2 Clock Generator - Page B - 3 Processor 1/7 - Page B - 4 Processor 2/7 - Page B - 5 Processor 3/7 - Page B - 6 Processor 4/7 - Page B - 7 Processor 5/7 - Page B - 8 Processor 6/7 - Page B - 9 Processor 7/7 - Page B - 10 DDRIII SO-DIMM_0 - Page B - 11 DDRIII SO-DIMM_1 - Page B - 12 LVDS, Inverter - Page B - 13 HDMI, CRT - Page B - 14 IBEXPEAK - M 1/9 - Page B - 15

Diagram - Page
IBEXPEAK - M 2/9 - Page B - 16 IBEXPEAK - M 3/9 - Page B - 17 IBEXPEAK - M 4/9 - Page B - 18 IBEXPEAK - M 5/9 - Page B - 19 IBEXPEAK - M 6/9 - Page B - 20 IBEXPEAK - M 7/9 - Page B - 21 IBEXPEAK - M 8/9 - Page B - 22 IBEXPEAK - M 9/9 - Page B - 23 New Card, Mini PCIE - Page B - 24 CCD, 3G, TPM - Page B - 25 Card Reader, LAN (JMB251) - Page B - 26 LAN (JMC251), SATA HDD, ODD - Page B - 27 Audio Codec VIA 1812 - Page B - 28 KBC-ITE IT8502E - Page B - 29

Diagram - Page
LED, MDC, BT - Page B - 30 USB, Fan, TP, Multi Con1 - Page B - 31 5VS, 3VS, 1.05VS - Page B - 32 Power 3.3V/5V - Page B - 33 Power 1.5V/0.75V/1.8VS - Page B - 34 Power 1.1VS_VTT - Page B - 35 Power VGFX_CORE - Page B - 36 V-Core - Page B - 37 DC-In, Charger - Page B - 38 Click Board - Page B - 39 Audio / USB / RJ11 Board - Page B - 40 Power Switch & LID Board - Page B - 41

Table B - 1
Schematic Diagrams

B.Schematic Diagrams

Version Note The schematic diagrams in this chapter are based upon version 6-7P-E4124-002. If your mainboard (or other boards) are a later version, please check with the Service Center for updated diagrams (if required).

B - 1

Schematic Diagrams

System Block Diagram


CLICK BOARD
6-71-C4502-D02

Calpella System Block Diagram


14.318 MHz

VDD3,VDD5 POWER GPU 1.8VS

POWER SWITCH BOARD


POWER SWITCH+HOTKEY X 3 6-71-C450S-D02

Clock Generator SLG8SP585V

AUDIO BOARD
PJ11+USB+EARPHONE+EXT.MIC 6-71-C410A-D01

Arrandale PROCESSOR rPGA989/988


FDI DMI*4
<=8"

Memory Termination 800/1067 MHz DDR3 / 1.5V DDRIII SO-DIMM0 SYSTEM SMBUS
0.1"~13

5V,3V,5VS,3VS,1.5VS,

1.5V,0.75VS(VTT_MEM) VCORE 1.1VS_VTT

DDRIII SO-DIMM1

B.Schematic Diagrams

HDMI

0.5"~6.5" <15"

Sheet 1 of 40 System Block Diagram

CLICK BOAR D

AUDIO BOARD
INTERNAL GRAPHICS

TOUCH PAD Synaptic


810602-170 3

CRT CONNECTOR
CR T SW IT CH

LCD CONNECTOR,

<8"
L VD S SW IT CH

INTERNAL GRAPHICS

Ibex Peak-M Platform Controller Hub (PCH)

RJ-11

MIC IN

HP OUT

32.768 KHz

EC ITE 8502E
128pins LQFP 1 4*1 4*1. 6mm

SPI

TPM

AZALIA MDC MODULE


MDC CON

INT SPK R

Azalia Codec VIA VT1812

AMP N7101 INT SPK L

33 MHz LPC
0.5"~11" BIOS SPI

27x27mm 1071 Ball FCBGA

INT MIC

AZALIA LINK PCIE 100 MHz

24 MHz
<12"

INT. K/B

EC SMBUS
THERMAL SENSOR W83L771AWG SMART FAN SMART BATTERY

32.7 68KHz

SATA I/II 3.0Gb/s

<12"

USB2.0 480 Mbps


1"~16"

New Card SOCKET (USB3)

3G CARD (USB9)
(Optional)

Mini PCIE SOCKET (USB2)

JMICRO

JMC251 LAN CARD READER 25


MHz 7IN1 SOCKET

RJ-45

SATA HDD

SATA ODD

USB0

USB1

USB4

Bluetooth (USB11)

CCD (USB5)

AUDIO BOARD

B - 2 System Block Diagram

Schematic Diagrams

Clock Generator
CLOCK GENERATOR
C LK _V C C 1 U7 1 5 17 24 29 15 18 C 21 3 3 4 6 7 10 11 13 14 C L K _B U F _ D OT 9 6 _P 1 5 C L K _B U F _ D OT 9 6 _N 15 0 . 1 u_ 1 0 V _X 7 R _ 0 4 C2 0 5 0. 1 u _ 10 V _ X 7R _0 4 C2 1 5 1 u _6 . 3 V _ X5 R _ 0 4 CL K _ V CC2 CL K _ V CC 1 V DD V DD V DD V DD V DD _ D OT _ 27 _ S RC _ CP U _ RE F V D D _ S R C _I / O V D D _ C P U _I / O D OT _9 6 D OT _ 96 # 2 7M 2 7 M_ S S X TA L _ OU T X TA L _ I N S RC_ 1 /S A T A S R C _ 1# / S A T A # S RC_ 2 S R C _2 #

CLKGEN POWER

3 .3 V S

L 15

*1 5 m li _ sh o rt _ 06

Sheet 2 of 40 Clock Generator

X OU T XIN

27 28

0 .1 u F n e a r t h e e v er y p ow e r p i n
C L K _S A T A 1 5 C L K _S A T A # 1 5 C L K _P C I E _ I C H 1 5 C L K _P C I E _ I C H # 1 5

15 C LK _ B U F _R E F 1 4

R1 3 0

3 3 _0 4

R E F _0 / C P U _ S E L

30

B.Schematic Diagrams

RE F _ 0 /CP U _ S E L

CL K _ S DA T A CL K _ S CL K

31 32 2 8 9 12 21 26 33

S DA S CL V S S _ DO T VSS_ 2 7 VSS_ SATA V S S _ S RC V S S _ CP U V S S _ RE F GN D S L G8 S P 5 85

16 C P U _ S T OP # CP U_ 1 C P U _1 # CP U_ 0 C P U _0 # C K P W R GD / P D # 20 19 23 22 25

C P U _ S T OP #

R 1 44

2. 2 1 K _1 % _ 04

3 .3 V S CL K _ V CC 2

1 . 1V S _V T T

C L K _B U F _ B C L K _ P 15 C L K _B U F _ B C L K _ N 1 5 C L K _P W R GD

L14 C2 1 4 0 . 1 u_ 1 0V _ X 7 R _ 04 C 2 04 1 u _ 6. 3 V _ X 5R _0 4

*1 5m i l _s h ort _0 6

V D D_ I / O c a n b e r a ng i n g f r om 1 . 05 V to 3 .3 V

3 .3 VS

I C S 9 L RS 3 1 97 R e al t e k R T M8 7 5 N6 3 2 -V B

R 14 5

0 . 1 uF n ea r th e ev e r y p o we r pi n
1 0 K _0 4

D Q 12 Q1 1 A MT D N 7 00 2 Z H S 6 R D 2 S C L K _S C L K 1 S

R 14 2 1 M_ 0 4

SMBus
15 S MB _ C L K 6 G C L K _S C L K 10 , 1 1 3 .3 V S

36

CL K E N#

G M T N 7 00 2 Z H S 3

EMI

X1 5 VS 1 2 G 3 4 4 R N1 5 3 2 . 2 K _ 4P 2 R _0 4 X IN 2

F S X8 L _ 14 . 3 1 81 8 MH z 1 X OU T R E F _ 0 / C P U _S E L C2 0 2 * 1 0p _ 50 V _ N P O _0 6

C 2 07 C L K _S D A T A C L K _S D A T A 1 0, 1 1 3 3 p _5 0 V _ N P O_ 0 4

C 20 8 3 3 p_ 5 0 V _N P O_ 0 4

15

S MB _ D A T A D 5 S

E M I C a p ac t i or

Q1 1 B MT D N 7 00 2 Z H S 6 R

CPU_SEL_During

CK_PEWGD Latch Pinl

3 .3 VS

PI N _ 30
R1 3 2 R1 3 3 * 4. 7 K _ 0 4 1 0 K _0 4 R E F _ 0/ C P U _ S E L

C PU _ 0 1 33 M H z 1 00 M H z

C P U_ 1 1 3 3M H z 1 0 0M H z
5 VS 13 , 1 7 , 20 , 2 1 , 26 , 2 7, 3 0 , 3 1, 3 5 , 3 6 3 .3 V 3, 4 , 1 2 , 14 , 1 5 , 16 , 1 8, 19 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 9 , 3 0, 3 1 , 33 , 3 4 , 35 3 .3 VS 10 , 1 1 , 12 , 1 3 , 14 , 1 5, 1 6 , 1 7, 1 8 , 1 9, 2 0 , 2 1, 2 3 , 2 4, 2 5 , 26 , 2 7 , 28 , 2 9 , 30 , 3 1 , 35 , 3 6 1 . 1 V S _V TT 4 , 6, 7, 1 4 , 15 , 1 6 , 19 , 2 0 , 21 , 3 4 , 35 , 3 6

0 ( de f a ul t ) 1 ( 0. 7 V -1 . 5 V)

Clock Generator B - 3

Schematic Diagrams

Processor 1/7
PROCESSOR 1/7
U 16 A P E G_ I C OM P I P E G_ I C O MP O P E G _R C O MP O P E G_ R B I A S P E G_ R X# [ 0 ] P E G_ R X# [ 1 ] P E G_ R X# [ 2 ] P E G_ R X# [ 3 ] P E G_ R X# [ 4 ] P E G_ R X# [ 5 ] P E G_ R X# [ 6 ] P E G_ R X# [ 7 ] P E G_ R X# [ 8 ] P E G_ R X# [ 9 ] P E G_ R X #[ 1 0 ] P E G_ R X #[ 1 1 ] P E G_ R X #[ 1 2 ] P E G_ R X #[ 1 3 ] P E G_ R X #[ 1 4 ] P E G_ R X #[ 1 5 ] P E G_ R X [ 0 ] P E G_ R X [ 1 ] P E G_ R X [ 2 ] P E G_ R X [ 3 ] P E G_ R X [ 4 ] P E G_ R X [ 5 ] P E G_ R X [ 6 ] P E G_ R X [ 7 ] P E G_ R X [ 8 ] P E G_ R X [ 9 ] P E G_ R X[ 1 0 ] P E G_ R X[ 1 1 ] P E G_ R X[ 1 2 ] P E G_ R X[ 1 3 ] P E G_ R X[ 1 4 ] P E G_ R X[ 1 5 ] P E G _ T X# [ 0 ] P E G _ T X# [ 1 ] P E G _ T X# [ 2 ] P E G _ T X# [ 3 ] P E G _ T X# [ 4 ] P E G _ T X# [ 5 ] P E G _ T X# [ 6 ] P E G _ T X# [ 7 ] P E G _ T X# [ 8 ] P E G _ T X# [ 9 ] P E G_ T X #[ 1 0 ] P E G_ T X #[ 1 1 ] P E G_ T X #[ 1 2 ] P E G_ T X #[ 1 3 ] P E G_ T X #[ 1 4 ] P E G_ T X #[ 1 5 ] P E G _ TX [ 0 ] P E G _ TX [ 1 ] P E G _ TX [ 2 ] P E G _ TX [ 3 ] P E G _ TX [ 4 ] P E G _ TX [ 5 ] P E G _ TX [ 6 ] P E G _ TX [ 7 ] P E G _ TX [ 8 ] P E G _ TX [ 9 ] P E G _ T X[ 1 0 ] P E G _ T X[ 1 1 ] P E G _ T X[ 1 2 ] P E G _ T X[ 1 3 ] P E G _ T X[ 1 4 ] P E G _ T X[ 1 5 ] B2 6 A2 6 B2 7 A2 5 K3 5 J34 J33 G 35 G 32 F3 4 F3 1 D 35 E3 3 C 33 D 32 B3 2 C 31 B2 8 B3 0 A3 1 J35 H 34 H 33 F3 5 G 33 E3 4 F3 2 D 34 F3 3 B3 3 D 31 A3 2 C 30 A2 8 B2 9 A3 0 L33 M 35 M 33 M 30 L31 K3 2 M 29 J31 K2 9 H 30 H 29 F2 9 E2 8 D 29 D 27 C 26 L34 M 34 M 32 L30 M 31 K3 1 M 28 H 31 K2 8 G 30 G 29 F2 8 E2 7 D 28 C 27 C 25

( DMI,PEG,FDI )
20 mil

P E G _I R C OM P _R

R 2 06 R 2 05

4 9 . 9 _ 1% _ 0 4 7 5 0 _1 % _ 0 4

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

D D D D D D D D D D D D D D D D

MI _ T X N 0 MI _ T X N 1 MI _ T X N 2 MI _ T X N 3 MI _ T X P 0 MI _ T X P 1 MI _ T X P 2 MI _ T X P 3 MI _ R X N MI _ R X N MI _ R X N MI _ R X N 0 1 2 3

A2 4 C 23 B2 2 A2 1 B2 4 D 23 B2 3 A2 2 D 24 G 24 F23 H 23 D 25 F24 E2 3 G 23

DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM DM

I_ RX # [0 ] I_ RX # [1 ] I_ RX # [2 ] I_ RX # [3 ] I_ RX [0 ] I_ RX [1 ] I_ RX [2 ] I_ RX [3 ] I _ TX # [ 0 ] I _ TX # [ 1 ] I _ TX # [ 2 ] I _ TX # [ 3 ] I _ TX [ 0 ] I _ TX [ 1 ] I _ TX [ 2 ] I _ TX [ 3 ]

EX P _ RBIA S

DMI

B.Schematic Diagrams

MI _ R X P 0 MI _ R X P 1 MI _ R X P 2 MI _ R X P 3

Sheet 3 of 40 Processor 1/7

16 16 16 16 16 16 16 16 It appli es t o Aub urnda le a nd Cl arksf ield disc rete graph ic d esign s. If discr ete graph ic ch ip i s use d for Aubu rnda le, V AXG ( GFX core) rail can be c onnec ted to GND i f mo therb oard only supp orts discr ete graph ics a nd a lso i n a c ommo n mot herbo ard desig n if GFX VR is not stuff ed. On th e oth er h and, if th e VR is s tuffe d, VAX G can be left float ing in a commo n mot herb oard desig n (G fx VR keep s VA XG fr om flo ating ). In addit ion, FDI_ RXN_[ 7:0] and FDI_R XP_[7 :0] can b e lef t fl oatin g on the PCH. FDI _TX[7 :0] and F DI_TX #[7: 0] ca n be left floa ting on th e Au burnd ale. The GFX_ IMON , FDI _FSYN C[0] , FDI _FSYN C[1], FDI _LSYN C[0], FDI _LSYN C[1], and FDI _INT sign als s hould be tied to GN D (th roug h 1K ? % r esis tors) in t he c ommon mot herbo ard desig n cas e. P lease not that if t hese signa ls a re le ft fl oati ng, t here are no fun ction al i mpact s but a s mall amoun t of powe r (~1 5 mW) may be wa sted. VAX G_SEN SE and VSSA XG_S ENSE on Au burn dale can b e lef t as no c onnec t. DPL L_REF _SSC LK an d DPL L_RE F_SSC LK# c an be con necte d to GND on Au burnd ale dir ectly if mothe rboar d on ly su pport s dis cret e gra phics . In a co mmon moth erboa rd des ign, thes e pin s are dri ven v ia PC H (ev en i f Gra phics is disab led b y BI OS) t hus n o ext ernal ter minat ion i s re quire d. 16 16 16 16 16

FD FD FD FD FD FD FD FD

I _ TX P 0 I _ TX P 1 I _ TX P 2 I _ TX P 3 I _ TX P 4 I _ TX P 5 I _ TX P 6 I _ TX P 7

D 22 C 21 D 20 C 18 G 22 E2 0 F20 G 19 F17 E1 7 C 17 F18 D 17

F DI F DI F DI F DI F DI F DI F DI F DI

_T X [ 0 ] _T X [ 1 ] _T X [ 2 ] _T X [ 3 ] _T X [ 4 ] _T X [ 5 ] _T X [ 6 ] _T X [ 7 ]

F D I_ F S Y NC 0 F D I_ F S Y NC 1 F D I_ INT F D I_ L S Y N C0 F D I_ L S Y N C1

F D I _F S Y N C [ 0 ] F D I _F S Y N C [ 1 ] F D I _I N T F D I _L S Y N C [ 0 ] F D I _L S Y N C [ 1 ]

On Board DDR3 Thermal Sensor

P Z 9 8 9 27 -3 6 4 1- 01 F

3 .3 V

Analog Thermal Sensor


C 36 4 * 0. 1 u _ 1 0V _X 5 R _ 0 4 U 18 C 1 2 B Q 10 *2 N 3 9 0 4 E 3 5 DGN D SD ATA SC L K 7 8 S MD _ C P U _T H E R M S MC _ C P U _T H E R M 1 5 , 28 1 5 , 28 VDD D+ T H ERM A LE R T 4 6 C D1 5 * RB7 5 1 V A T H E R M_ A L E R T# 2 8 P M_ E X T T S #_ E C 4 C 3 66 0 . 1 u _ 10 V _ X 7 R _ 0 4 3 GN D G7 1 1 S T 9U C3 6 7 0 . 1u _ 1 0 V _ X7 R _0 4 R2 2 5 *1 0 m i _ l s h ort 3 . 3V C R I T _T E M P _ R E P # 1 9 2 Q 16 VC C OU T 1

PCI EXPRESS -- GRAPHICS

16 16 16 16 16 16 16 16

FD FD FD FD FD FD FD FD

I _ TX N I _ TX N I _ TX N I _ TX N I _ TX N I _ TX N I _ TX N I _ TX N

0 1 2 3 4 5 6 7

E2 2 D 21 D 19 D 18 G 21 E1 9 F21 G 18

F DI F DI F DI F DI F DI F DI F DI F DI

_T X # [ 0 ] _T X # [ 1 ] _T X # [ 2 ] _T X # [ 3 ] _T X # [ 4 ] _T X # [ 5 ] _T X # [ 6 ] _T X # [ 7 ]

*W 83 L 7 7 1A W G

PLACE NEAR U3

Intel(R) FDI

1: 2 (4 mi ls :8 mi ls )

T H E R M _V OL T 2 8 4, 1 2 , 1 4 , 15 , 1 6 , 1 8 , 19 , 2 0 , 2 1, 23 , 2 4 , 2 5, 29 , 3 0 , 3 1, 3 3 , 3 4 , 3 5 3 . 3 V

B - 4 Processor 1/7

Schematic Diagrams

Processor 2/7
PROCESSOR
Processor Compensation Signals
R2 3 6 R2 1 2 4 9 . 9 _ 1% _ 0 4 4 9 . 9 _ 1% _ 0 4 H _C OM P 0 H _C OM P 1 R 2 01 0_04

2/7

( CLK,MISC,JTAG )
1 .5 V R 20 0 * 1K _0 4

DDR3 Compensation Signals


S M _R C O MP _ 0 S M _R C O MP _ 1 R2 2 6 R2 2 7 R2 2 8 1 0 0 _ 1% _ 0 4 2 4 . 9 _ 1% _ 0 4 1 3 0 _ 1% _ 0 4 S M _D R A M R S T#

BSS1 38 ( VGS 1.5V ) Q 15 * R J U 00 3 N 0 3 T 1 06 S D

R2 3 4 R2 3 3

2 0 _ 1 %_ 0 4 2 0 _ 1 %_ 0 4

H _C OM P 2 S M _R C O MP _ 2 H _C OM P 3 R 2 02 * 10 0 K _ 0 4 G

D D R 3 _ D R A MR S T # 1 0, 1 1

T RACE WIDT H 10M IL, LENGT H <5 00MIL S C3 1 8 *4 7 n_ 5 0 V _ 04 U 16 B H _ C O MP 3 AT2 3 AT2 4 G1 6 AT2 6 C O MP 3 C O MP 2 C O MP 1 C O MP 0 B CL K B CL K # B CL K _ IT P B C LK _I T P # P E G _ CL K P E G_ C L K # D P LL _ R E F _S S C L K D P L L_ R E F _ S S C L K # H _ C O MP 2 H _ C O MP 1 1 .1 V S _ V T T H _ C O MP 0 H _C A T E R R # H _P R OC H O T #_ D H _ C A TE R R # R2 4 5 * 6 8_ 0 4 H _C P U R S T # AK1 4 C A TE R R # A1 6 B1 6 AR 3 0 AT3 0 E1 6 D 16 A1 8 A1 7 C LK _E X P _ P 1 5 C LK _E X P _ N 1 5 C LK _D P _ P 1 5 C LK _D P _ N 1 5 B C L K _C P U _P B C L K _C P U _N 19 19

D R A MR S T _C T R L 9 , 1 9 ? ? I BEX CONTR OL

B.Schematic Diagrams

MISC

Processor Pullups

R2 1 6 R2 3 7

4 9 . 9 _ 1% _ 0 4 68_04

A H2 4

S K T OC C #

CLOCKS

Sheet 4 of 40 Processor 2/7


1 .1 V S _ V T T R 2 30 R 54 R 53 R 2 29 R 2 31 1 0 K _ 04 1 0 K _ 04 * 0_ 0 4 * 0_ 0 4 * 12 . 4 K _ 1 % _0 4 P M_ E X T T S # _E C 3 T S #_ D I MM 0 _1 1 0 , 1 1

THERMAL

1 9 ,2 8 H _ P E CI

AT1 5 PEC I

S M_ D R A M R S T # S M_ R C O MP [ 0 ] S M_ R C O MP [ 1 ] S M_ R C O MP [ 2 ] P M_ E X T _T S # [ 0 ] P M_ E X T _T S # [ 1 ]

F6 AL 1 AM 1 AN 1 AN 1 5 A P 15

S M_ D R A M R S T # S M_ R C O MP _ 0 S M_ R C O MP _ 1 S M_ R C O MP _ 2 P M_ E X T T S #[ 0] P M_ E X T T S #[ 1]

3 6 H _ P R OC H O T #

P R OC H OT #

I f PRO CHOT # is not used, the n it must be t ermi nated w ith a 50O pul l-up resi stor to V TT_1 .1 ra il. 1 9 H _ TH R M T R I P # AK1 5 T H E R MT R I P #

DDR3 MISC

R2 4 6

0 _0 4

H _ P R OC H O T# _ D

A N2 6

P RD Y # P R E Q# H _ C P U R S T# AP2 6 AL 1 5 P M _S Y N C S Y S _ A G E N T _ P W R OK A N 1 4 V C C P W R GO OD _ 1 TC K TM S T RS T #

AT2 8 A P 27 AN 2 8 A P 28 AT2 7 AT2 9 AR 2 7 AR 2 9 A P 29 AN 2 5

XD P _ P R E Q# XD P _ T C L K XD P _ T MS XD P _ T R S T # XD XD XD XD P _ T DI_ R P _ T D O _R P _ T DI_ M P _ T D O _M X DP X DP X DP X DP X DP _T M S _T D O_ M _T D I _R _P R E Q # _T D O_ R R R R R R 2 50 2 42 2 49 2 40 2 39 * 51 _ 0 4 5 1 _ 04 * 51 _ 0 4 * 51 _ 0 4 * 51 _ 0 4

R E S E T _O B S #

PWR MANAGEMENT

JTAG & BPM

1 6 H _ P M_ S Y N C R 24 7 R 24 8 1 9 H _ C P U P W R GD R 52 * 1 0m i l _s h o rt V D D P W R GO OD _R *0 _ 0 4 * 1 0m i l _s h o rt

1 6 , 3 6 D E L A Y _ P W R GD

TD I TD O T D I_ M T DO _ M D B R#

1 .1 V S _ V T T

A N2 7 AK1 3

V C C P W R GO OD _ 0

1 6 P M _ D R A M_ P W R GD

S M _D R A M P W R OK A M1 5 H _ P W R GD _ XD P V T T P W R G OO D

1 6 H _ V T TP W R G D Conne ct t o the Pro cesso r (V TTPW RGOOD ) VT T_1.1 VR power good sign al to pro cesso r. S igna l vol tage leve l is 1.1 V.

A M2 6 AL 1 4

T A P P W R GO OD

B P M# [ 0 ] B P M# [ 1 ] B P M# [ 2 ] B P M# [ 3 ] B P M# [ 4 ] B P M# [ 5 ] B P M# [ 6 ] B P M# [ 7 ]

AJ 2 2 A K 22 A K 24 AJ 2 4 AJ 2 5 AH 2 2 A K 23 AH 2 3

X D P _T C LK X D P _T R S T #

R 2 43 R 2 38

* 51 _ 0 4 5 1 _ 04

1 8 , 2 3, 2 5 , 2 8 B U F _P L T _ R S T #

R 60

1 . 5 K _ 1% _ 0 4

P L T_ R S T #_ R

R S TI N # Si gnal from PCH to P roces sor Co nnect to PCH ( PLT_ RST#) (n eeds to b e lev el t ransl ated fr om 3. 3 V to 1. 1 V) . R6 1 7 50 _ 1 % _0 4

P Z 9 8 9 2 7-3 6 4 1- 01 F X D P _T D O_ M R 2 41 *1 0 mi l _ sh o rt XD P _ T D I _ M

1 .5 V S _ CP U

3 .3 V R 50 1 . 1 K _ 1% _ 0 4 V D D P W R G OO D _ R U1 7 R 62 3 K _ 1% _ 0 4 3 *M C 7 4 V H C 1 G0 8 D F T 1 G R2 4 4 * 1 . 5K _ 1 % _ 04 D R A MP W R G D _ C P U 4 2 1 . 1 V S _ V T T _P W R G D 1 6 , 3 3, 3 4 5 1 IN3 .3 V R2 3 2 * 8 . 2K _ 0 4 3 .3 V 3, 12 , 1 4 , 1 5, 1 6 , 1 8 , 19 , 2 0 , 2 1, 2 3 , 2 4 , 25 , 2 9 , 3 0, 31 , 3 3 , 3 4, 3 5 1 .5 V 9, 10 , 1 1 , 2 1, 2 3 , 2 7 , 29 , 3 1 , 3 3, 3 6 1 .5 V S _ C P U 7 ,3 1 1 . 1 V S _ V T T 2 , 6 , 7, 1 4 , 1 5 , 16 , 1 9 , 2 0, 21 , 3 4 , 3 5, 3 6

Int el ch ange 4.7 5K ->1.1 K 12K -->3 K

Processor 2/7 B - 5

Schematic Diagrams

Processor 3/7
PROCESSOR
U16C U16D

3/7

( DDR3 )

10 M _A _DQ[63:0] M _A _DQ0 M _A _DQ1 M _A _DQ2 M _A _DQ3 M _A _DQ4 M _A _DQ5 M _A _DQ6 M _A _DQ7 M _A _DQ8 M _A _DQ9 M _A _DQ10 M _A _DQ11 M _A _DQ12 M _A _DQ13 M _A _DQ14 M _A _DQ15 M _A _DQ16 M _A _DQ17 M _A _DQ18 M _A _DQ19 M _A _DQ20 M _A _DQ21 M _A _DQ22 M _A _DQ23 M _A _DQ24 M _A _DQ25 M _A _DQ26 M _A _DQ27 M _A _DQ28 M _A _DQ29 M _A _DQ30 M _A _DQ31 M _A _DQ32 M _A _DQ33 M _A _DQ34 M _A _DQ35 M _A _DQ36 M _A _DQ37 M _A _DQ38 M _A _DQ39 M _A _DQ40 M _A _DQ41 M _A _DQ42 M _A _DQ43 M _A _DQ44 M _A _DQ45 M _A _DQ46 M _A _DQ47 M _A _DQ48 M _A _DQ49 M _A _DQ50 M _A _DQ51 M _A _DQ52 M _A _DQ53 M _A _DQ54 M _A _DQ55 M _A _DQ56 M _A _DQ57 M _A _DQ58 M _A _DQ59 M _A _DQ60 M _A _DQ61 M _A _DQ62 M _A _DQ63 A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M 6 M 8 L9 L6 K8 N8 P9 A H5 A F5 A K6 A K7 A F6 A G5 AJ7 AJ6 A J10 AJ9 A L10 A K12 A K8 AL7 A K11 AL8 A N8 A M 10 A R11 A L11 A M 9 A N9 A T 11 A P12 A M 12 A N12 A M 13 A T 14 A T 12 A L13 A R14 A P14 SA _DQ [0] SA _DQ [1] SA _DQ [2] SA _DQ [3] SA _DQ [4] SA _DQ [5] SA _DQ [6] SA _DQ [7] SA _DQ [8] SA _DQ [9] SA _DQ [10] SA _DQ [11] SA _DQ [12] SA _DQ [13] SA _DQ [14] SA _DQ [15] SA _DQ [16] SA _DQ [17] SA _DQ [18] SA _DQ [19] SA _DQ [20] SA _DQ [21] SA _DQ [22] SA _DQ [23] SA _DQ [24] SA _DQ [25] SA _DQ [26] SA _DQ [27] SA _DQ [28] SA _DQ [29] SA _DQ [30] SA _DQ [31] SA _DQ [32] SA _DQ [33] SA _DQ [34] SA _DQ [35] SA _DQ [36] SA _DQ [37] SA _DQ [38] SA _DQ [39] SA _DQ [40] SA _DQ [41] SA _DQ [42] SA _DQ [43] SA _DQ [44] SA _DQ [45] SA _DQ [46] SA _DQ [47] SA _DQ [48] SA _DQ [49] SA _DQ [50] SA _DQ [51] SA _DQ [52] SA _DQ [53] SA _DQ [54] SA _DQ [55] SA _DQ [56] SA _DQ [57] SA _DQ [58] SA _DQ [59] SA _DQ [60] SA _DQ [61] SA _DQ [62] SA _DQ [63]

S A _CK [0] S A _CK #[0] SA _CK E [0]

A A6 A A7 P 7

M _CLK _DD R0 10 M _CLK _DD R#0 10 M _CK E 0 1 0

11 M _B _DQ [ 63:0] M _B _DQ 0 M _B _DQ 1 M _B _DQ 2 M _B _DQ 3 M _B _DQ 4 M _B _DQ 5 M _B _DQ 6 M _B _DQ 7 M _B _DQ 8 M _B _DQ 9 M _B _DQ 10 M _B _DQ 11 M _B _DQ 12 M _B _DQ 13 M _B _DQ 14 M _B _DQ 15 M _B _DQ 16 M _B _DQ 17 M _B _DQ 18 M _B _DQ 19 M _B _DQ 20 M _B _DQ 21 M _B _DQ 22 M _B _DQ 23 M _B _DQ 24 M _B _DQ 25 M _B _DQ 26 M _B _DQ 27 M _B _DQ 28 M _B _DQ 29 M _B _DQ 30 M _B _DQ 31 M _B _DQ 32 M _B _DQ 33 M _B _DQ 34 M _B _DQ 35 M _B _DQ 36 M _B _DQ 37 M _B _DQ 38 M _B _DQ 39 M _B _DQ 40 M _B _DQ 41 M _B _DQ 42 M _B _DQ 43 M _B _DQ 44 M _B _DQ 45 M _B _DQ 46 M _B _DQ 47 M _B _DQ 48 M _B _DQ 49 M _B _DQ 50 M _B _DQ 51 M _B _DQ 52 M _B _DQ 53 M _B _DQ 54 M _B _DQ 55 M _B _DQ 56 M _B _DQ 57 M _B _DQ 58 M _B _DQ 59 M _B _DQ 60 M _B _DQ 61 M _B _DQ 62 M _B _DQ 63 B 5 A 5 C 3 B 3 E 4 A 6 A 4 C 4 D 1 D 2 F 2 F 1 C 2 F 5 F 3 G 4 H 6 G 2 J 6 J 3 G 1 G 5 J 2 J 1 J 5 K 2 L 3 M 1 K 5 K 4 M 4 N 5 A F 3 AG 1 AJ 3 A K 1 AG 4 AG 3 AJ 4 AH 4 A K 3 A K 4 AM 6 AN 2 A K 5 A K 2 AM 4 AM 3 A P 3 AN 5 AT 4 AN 6 AN 4 AN 3 AT 5 AT 6 AN 7 A P 6 A P 8 AT 9 AT 7 A P 9 AR1 0 AT 1 0 S B_D Q[0] S B_D Q[1] S B_D Q[2] S B_D Q[3] S B_D Q[4] S B_D Q[5] S B_D Q[6] S B_D Q[7] S B_D Q[8] S B_D Q[9] S B_D Q[10] S B_D Q[11] S B_D Q[12] S B_D Q[13] S B_D Q[14] S B_D Q[15] S B_D Q[16] S B_D Q[17] S B_D Q[18] S B_D Q[19] S B_D Q[20] S B_D Q[21] S B_D Q[22] S B_D Q[23] S B_D Q[24] S B_D Q[25] S B_D Q[26] S B_D Q[27] S B_D Q[28] S B_D Q[29] S B_D Q[30] S B_D Q[31] S B_D Q[32] S B_D Q[33] S B_D Q[34] S B_D Q[35] S B_D Q[36] S B_D Q[37] S B_D Q[38] S B_D Q[39] S B_D Q[40] S B_D Q[41] S B_D Q[42] S B_D Q[43] S B_D Q[44] S B_D Q[45] S B_D Q[46] S B_D Q[47] S B_D Q[48] S B_D Q[49] S B_D Q[50] S B_D Q[51] S B_D Q[52] S B_D Q[53] S B_D Q[54] S B_D Q[55] S B_D Q[56] S B_D Q[57] S B_D Q[58] S B_D Q[59] S B_D Q[60] S B_D Q[61] S B_D Q[62] S B_D Q[63]

SB _CK [0] SB _CK #[0] S B_C KE [0]

W 8 W 9 M 3

M _C LK_D DR2 11 M _C LK_D DR#2 11 M _C KE 2 11

S A _CK [1] S A _CK #[1] SA _CK E [1]

Y6 Y5 P 6

M _CLK _DD R1 10 M _CLK _DD R#1 10 M _CK E 1 1 0

SB _CK [1] SB _CK #[1] S B_C KE [1]

V 7 V 6 M 2

M _C LK_D DR3 11 M _C LK_D DR#3 11 M _C KE 3 11

S A _CS #[0] S A _CS #[1]

A E2 A E8

M _CS #0 10 M _CS #1 10

B.Schematic Diagrams

SB _CS #[0] SB _CS #[1]

A B 8 A D6

M _C S#2 11 M _C S#3 11

SA _OD T [0] SA _OD T [1]

A D8 A F9

M _OD T 0 1 0 M _OD T 1 1 0

S B_O DT [0] S B_O DT [1]

A C7 A D1

M _O DT 2 11 M _O DT 3 11

Sheet 5 of 40 Processor 3/7

SA _DM [0] SA _DM [1] SA _DM [2] SA _DM [3] SA _DM [4] SA _DM [5] SA _DM [6] SA _DM [7]

B 9 D7 H7 M 7 A G6 A M 7 A N10 A N13

M _A_ DM 0 M _A_ DM 1 M _A_ DM 2 M _A_ DM 3 M _A_ DM 4 M _A_ DM 5 M _A_ DM 6 M _A_ DM 7

M _A _DM [7: 0 ] 10

S B_D M [0] S B_D M [1] S B_D M [2] S B_D M [3] S B_D M [4] S B_D M [5] S B_D M [6] S B_D M [7]

D4 E 1 H3 K 1 A H1 A L2 A R4 A T 8

M _B _DM 0 M _B _DM 1 M _B _DM 2 M _B _DM 3 M _B _DM 4 M _B _DM 5 M _B _DM 6 M _B _DM 7

M _B_D M [7:0] 11

DDR SY STEM MEM ORY A

S A_ DQS [0] S A_ DQS [1] S A_ DQS [2] S A_ DQS [3] S A_ DQS [4] S A_ DQS [5] S A_ DQS [6] S A_ DQS [7]

C8 F 9 H9 M 9 A H8 A K10 A N11 A R13

M _A_ DQS 0 M _A_ DQS 1 M _A_ DQS 2 M _A_ DQS 3 M _A_ DQS 4 M _A_ DQS 5 M _A_ DQS 6 M _A_ DQS 7

M _A _D QS[7:0] 10

DDR SYS TEM MEMO RY - B

S A_D QS #[0] S A_D QS #[1] S A_D QS #[2] S A_D QS #[3] S A_D QS #[4] S A_D QS #[5] S A_D QS #[6] S A_D QS #[7]

C9 F 8 J9 N9 A H7 A K9 A P11 A T 13

M _A_ DQS #0 M _A_ DQS #1 M _A_ DQS #2 M _A_ DQS #3 M _A_ DQS #4 M _A_ DQS #5 M _A_ DQS #6 M _A_ DQS #7

M _A _D QS# [ 7:0] 10

S B _DQS #[0] S B _DQS #[1] S B _DQS #[2] S B _DQS #[3] S B _DQS #[4] S B _DQS #[5] S B _DQS #[6] S B _DQS #[7]

D5 F 4 J4 L4 A H2 A L4 A R5 A R8

M _B _DQS #0 M _B _DQS #1 M _B _DQS #2 M _B _DQS #3 M _B _DQS #4 M _B _DQS #5 M _B _DQS #6 M _B _DQS #7

M _B_ DQS #[7:0] 11

S B _DQS [0] S B _DQS [1] S B _DQS [2] S B _DQS [3] S B _DQS [4] S B _DQS [5] S B _DQS [6] S B _DQS [7]

C5 E 3 H4 M 5 A G2 A L5 A P 5 A R7

M _B _DQS 0 M _B _DQS 1 M _B _DQS 2 M _B _DQS 3 M _B _DQS 4 M _B _DQS 5 M _B _DQS 6 M _B _DQS 7

M _B_ DQS [7:0] 11

10 10 10

M _A _B S0 M _A _B S1 M _A _B S2

A C3 A B2 U7

SA _B S[0] SA _B S[1] SA _B S[2]

10 10 10

M _A _CA S # M _A _RA S # M _A _W E#

A E1 A B3 A E9

SA _CA S # SA _RA S # SA _W E#

S A _M A [0] S A _M A [1] S A _M A [2] S A _M A [3] S A _M A [4] S A _M A [5] S A _M A [6] S A _M A [7] S A _M A [8] S A _M A [9] S A _M A [10] S A _M A [11] S A _M A [12] S A _M A [13] S A _M A [14] S A _M A [15]

Y3 W1 A A8 A A3 V 1 A A9 V 8 T 1 Y9 U6 A D4 T 2 U3 A G8 T 3 V 9

M _A_ A0 M _A_ A1 M _A_ A2 M _A_ A3 M _A_ A4 M _A_ A5 M _A_ A6 M _A_ A7 M _A_ A8 M _A_ A9 M _A_ A10 M _A_ A11 M _A_ A12 M _A_ A13 M _A_ A14 M _A_ A15

M _A _A [15:0] 10

11 11 11

M _B _BS 0 M _B _BS 1 M _B _BS 2

A B 1 W 5 R 7

S B_B S [0] S B_B S [1] S B_B S [2]

11 11 11

M _B _CA S# M _B _RA S# M _B _WE #

AC 5 Y 7 AC 6

S B_C AS # S B_R AS # S B_W E #

SB _M A [0] SB _M A [1] SB _M A [2] SB _M A [3] SB _M A [4] SB _M A [5] SB _M A [6] SB _M A [7] SB _M A [8] SB _M A [9] SB _M A [10] SB _M A [11] SB _M A [12] SB _M A [13] SB _M A [14] SB _M A [15]

U5 V 2 T 5 V 3 R1 T 8 R2 R6 R4 R5 A B 5 P 3 R3 A F 7 P 5 N1

M _B _A 0 M _B _A 1 M _B _A 2 M _B _A 3 M _B _A 4 M _B _A 5 M _B _A 6 M _B _A 7 M _B _A 8 M _B _A 9 M _B _A 10 M _B _A 11 M _B _A 12 M _B _A 13 M _B _A 14 M _B _A 15

M _B_A [15:0] 1 1

PZ 98927-3641-01F

P Z9892 7- 36 41-01F

B - 6 Processor 3/7

Schematic Diagrams

Processor 4/7
PROCESSOR
U1 6 F

4/7

( POWER )
PROCE SSOR UNCO RE POWER
1 .1 V S _ V T T

P ROCESSOR CORE POWE R


VCO R E

48A
A G3 5 A G3 4 A G3 3 A G3 2 A G3 1 A G3 0 A G2 9 A G2 8 A G2 7 A G2 6 AF3 5 AF3 4 AF3 3 AF3 2 AF3 1 AF3 0 AF2 9 AF2 8 AF2 7 AF2 6 A D3 5 A D3 4 A D3 3 A D3 2 A D3 1 A D3 0 A D2 9 A D2 8 A D2 7 A D2 6 A C3 5 A C3 4 A C3 3 A C3 2 A C3 1 A C3 0 A C2 9 A C2 8 A C2 7 A C2 6 AA3 5 AA3 4 AA3 3 AA3 2 AA3 1 AA3 0 AA2 9 AA2 8 AA2 7 AA2 6 Y3 5 Y3 4 Y3 3 Y3 2 Y3 1 Y3 0 Y2 9 Y2 8 Y2 7 Y2 6 V3 5 V3 4 V3 3 V3 2 V3 1 V3 0 V2 9 V2 8 V2 7 V2 6 U3 5 U3 4 U3 3 U3 2 U3 1 U3 0 U2 9 U2 8 U2 7 U2 6 R3 5 R3 4 R3 3 R3 2 R3 1 R3 0 R2 9 R2 8 R2 7 R2 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 P2 9 P2 8 P2 7 P2 6 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VTT0 _ 1 VTT0 _ 2 VTT0 _ 3 VTT0 _ 4 VTT0 _ 5 VTT0 _ 6 VTT0 _ 7 VTT0 _ 8 VTT0 _ 9 VT T 0 _ 1 0 VT T 0 _ 1 1 VT T 0 _ 1 2 VT T 0 _ 1 3 VT T 0 _ 1 4 VT T 0 _ 1 5 VT T 0 _ 1 6 VT T 0 _ 1 7 VT T 0 _ 1 8 VT T 0 _ 1 9 VT T 0 _ 2 0 VT T 0 _ 2 1 VT T 0 _ 2 2 VT T 0 _ 2 3 VT T 0 _ 2 4 VT T 0 _ 2 5 VT T 0 _ 2 6 VT T 0 _ 2 7 VT T 0 _ 2 8 VT T 0 _ 2 9 VT T 0 _ 3 0 VT T 0 _ 3 1 VT T 0 _ 3 2 AH 1 4 AH 1 2 AH 1 1 AH 1 0 J14 J13 H 14 H 12 G 14 G 13 G 12 G 11 F14 F13 F12 F11 E1 4 E1 2 D 14 D 13 D 12 D 11 C 14 C 13 C 12 C 11 B1 4 B1 2 A1 4 A1 3 A1 2 A1 1 C 28 1 0 u _ 6. 3V _ X5 R _ 0 6 C2 9 *1 0 u _ 6 . 3 V _ X 5R _ 0 6 C 331 1 0 u _ 6 .3 V_ X 5 R_ 0 6 C 34 * 10 u _ 6 . 3 V _ X 5 R _ 0 6

VTT T OTAL 21A


C 32 * 1 0 u _6 . 3 V _X 5 R _ 06 C3 0 8 2 2 u_ 6 . 3 V _ X 5 R _ 08 C 341 2 2 u _ 6 . 3 V _ X 5R _ 0 8

I C CM AX Ma xi m um Pr oc e ss or

S V 48

V CO R E C3 3 0 2 2u _ 6 . 3 V _ X 5 R _ 0 8 C3 3 8 2 2u _ 6 . 3 V _ X 5 R _ 0 8 C3 4 2 *2 2 u _ 6. 3V _ X 5 R _ 0 8 C3 4 4 22 u _ 6 . 3 V _ X 5 R _ 08

C 36 1 0 u _ 6. 3V _ X5 R _ 0 6

C3 1 0 10 u _ 6 . 3 V _ X 5 R _ 0 6

C 33 1 0 u _6 . 3 V _ X 5 R _ 06

C 335 * 1 0 u_ 6 . 3 V _ X 5 R _0 6

I CC MAX _VT T Max C urr ent f or VT T R ai l SV 18

B.Schematic Diagrams

C3 4 9 *2 2 u _ 6 . 3 V _ X 5 R _ 0 8

C3 5 9 2 2u _ 6 . 3 V _ X 5 R _ 0 8

C3 3 6 *2 2 u _ 6. 3V _ X 5 R _ 0 8

C3 2 5 22 u _ 6 . 3 V _ X 5 R _ 08

1.1V RAIL POWER

1 .1 VS _ V T T VT T 0 _ 3 3 VT T 0 _ 3 4 VT T 0 _ 3 5 VT T 0 _ 3 6 VT T 0 _ 3 7 VT T 0 _ 3 8 VT T 0 _ 3 9 VT T 0 _ 4 0 VT T 0 _ 4 1 VT T 0 _ 4 2 VT T 0 _ 4 3 VT T 0 _ 4 4 A F 10 A E 10 AC 1 0 A B 10 Y 10 W 10 U 10 T10 J12 J11 J16 J15

The decoupling capacitors, filter recommendations and sense resistors on the CPU/PCH Rails are specific to the CRB Implementation. Customers need to follow the recommendations in the Calpella Platform Design Guide

Sheet 6 of 40 Processor 4/7

C3 3 9 2 2u _ 6 . 3 V _ X 5 R _ 0 8

C3 6 3 2 2u _ 6 . 3 V _ X 5 R _ 0 8

C3 6 2 *2 2 u _ 6. 3V _ X 5 R _ 0 8

C3 6 1 *2 2 u _ 6. 3V _ X 5 R _ 0 8

C 311 2 2 u _ 6 .3 V _ X 5 R_ 0 8

C3 1 2 2 2u _ 6 . 3 V _ X 5 R _0 8

C 319 2 2 u _ 6 . 3 V _ X 5R _ 0 8

CPU CORE SUPPLY

1.1VS_VTT
+ V T T _4 3 + V T T _4 4 R 209 R 211 *1 0 m i _ l s h o rt _ 0 4 *1 0 m i _ l s h o rt _ 0 4

Please note that the VTT Rail Values are Auburndale VTT=1.05V

1 . 1 V S _ V TT

V CO R E

C3 5 5 *1 0 u _ 6 . 3 V _ X 5 R _ 0 6

C3 5 3 *1 0 u _ 6. 3V _ X 5 R _ 0 6

C3 5 2 10 u _ 6 . 3 V _ X 5 R _ 0 6

C3 5 1 10 u _ 6 . 3 V _ X 5 R _ 06

1K PU t o V TT an d 1 K P D t o GN D fo r P OC
VC ORE AN 3 3 P S I# PSI #

R 222 * 1 K_ 0 4 P S I# R 223 1 K _0 4 R 220 1 K_ 0 4 P M _D P R S L P V R R 219 36 36 1 .1 V S_ V T T

POWER

C3 3 3 1 0u _ 6 . 3 V _ X 5 R _ 0 6

C3 3 2 *1 0 u _ 6. 3V _ X 5 R _ 0 6

C3 3 4 *1 0 u _ 6. 3V _ X 5 R _ 0 6

C3 5 4 10 u _ 6 . 3 V _ X 5 R _ 06

CPU VIDS

V ID [0 ] V ID [1 ] V ID [2 ] V ID [3 ] V ID [4 ] V ID [5 ] V ID [6 ] P R OC _ D P R S L P V R

A K 35 A K 33 A K 34 AL 3 5 AL 3 3 AM 3 3 AM 3 5 AM 3 4

H H H H H H H

_V _V _V _V _V _V _V

ID0 ID1 ID2 ID3 ID4 ID5 ID6

36 36 36 36 36 36 36

VT T _ SEL EC T

G 15

H _V T TV I D 1 * 1 K_ 0 4

TO V CORE POW ER CONT ROL AN 3 5 IS E NS E IM O N 36

C3 4 7 0 . 1 u_ 1 0 V _ X 7 R _ 0 4

C3 4 6 1 0u _ 6 . 3 V _ X 5 R _ 0 6

C3 4 5 0. 01 u _ 5 0 V _ X 7 R _ 04

C3 4 0 10 u _ 6 . 3 V _ X 5 R _ 06

SENSE LINES

V C C_ S E NS E V S S _ S E NS E

AJ 3 4 AJ 3 5

VC C _ SEN SE 3 6 V S S _ S E N S E 36

V T T _ S E NS E V S S _ S E NS E _ V T T

B1 5 A1 5

V T T _ S E NSE

34

V CO RE 36 1 . 1 V S _ V T T 2 , 4 , 7 , 1 4, 15 , 1 6 , 1 9 , 2 0 , 2 1 , 3 4 , 3 5, 36

P Z 9 8 9 2 7- 36 4 1 -0 1 F

Processor 4/7 B - 7

Schematic Diagrams

Processor 5/7

PROCESSOR
V G F X _ CO R E A T 21 A T 19 A T 18 A T 16 A R 21 A R 19 A R 18 A R 16 A P 21 A P 19 A P 18 A P 16 A N 21 A N 19 A N 18 A N 16 A M 21 A M 19 A M 18 A M 16 A L 21 A L 19 A L 18 A L 16 A K 21 A K 19 A K 18 A K 16 A J 21 A J 19 A J 18 A J 16 A H 21 A H 19 A H 18 A H 16 U1 6 G VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

5/7

( GRAPHICS POWER )

10 u _ 6 . 3 V _ X 5 R _ 0 6

1 0 u _ 6 . 3 V _ X 5R _ 0 6

SE NSE LINES

C3 7 3

C 356

VAXG _ SEN SE VSSAXG _ SEN SE

A R 22 AT 2 2

G P U V C C S E N S E 35 G P UV S S S E NS E 3 5

B.Schematic Diagrams

C3 5 7 C 37 1 + 2 2 0 u_ 4 V _ V _ A 22 u _ 6 . 3 V _ X 5 R _ 0 8

C 369 2 2 u _ 6 . 3 V _ X 5R _ 0 8

Sheet 7 of 40 Processor 5/7


Please note that the VTT Rail Values are Auburndale VTT=1.05V Clarksfield VTT=1.1V

GRAPHICS VIDs

GF GF GF GF GF GF GF

X_ V I X_ V I X_ V I X_ V I X_ V I X_ V I X_ V I

D[0 ] D[1 ] D[2 ] D[3 ] D[4 ] D[5 ] D[6 ]

A M 22 AP2 2 A N 22 AP2 3 A M 23 AP2 4 A N 24

D D D D D D D

F GT _ V I D F GT _ V I D F GT _ V I D F GT _ V I D F GT _ V I D F GT _ V I D F GT _ V I D

_0 _1 _2 _3 _4 _5 _6

35 35 35 35 35 35 35 1 .1 VS _ VT T

- 1.5V RAILS

POWER

1 .1 VS _ VT T C 32 1 2 2 u _6 . 3 V _ X 5 R _0 8 C 3 15 2 2 u _ 6. 3V _X 5 R _ 08

J 24 J 23 H 25

V T T 1_ 4 5 V T T 1_ 4 6 V T T 1_ 4 7

DDR3

1 .1 VS _ VT T C 31 3 2 2 u _6 . 3 V _ X 5 R _0 8 1 .1 V S _ V T T C 3 14 2 2 u _ 6. 3V _X 5 R _ 08

C 31 6 C4 0 3 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4 C3 5 8 0 . 0 1u _ 5 0 V _ X 7 R _ 0 4 2 2 u _6 . 3 V _ X 5 R _0 8

C 3 09 2 2 u _ 6. 3V _X 5 R _ 08

K 26 J 27 J 26 J 25 H 27 G 28 G 27 G 26 F 26 E 26 E 25

1.8V

V T T 1_ 4 8 V T T 1_ 4 9 V T T 1_ 5 0 V T T 1_ 5 1 V T T 1_ 5 2 V T T 1_ 5 3 V T T 1_ 5 4 V T T 1_ 5 5 V T T 1_ 5 6 V T T 1_ 5 7 V T T 1_ 5 8

1.1V

GRAPHICS
FDI PEG & DMI

G F X _ V R _E N G F X _ DP RS L P V R GF X_ I M O N

A R 25 AT 2 5 A M 24

GF XV R _ D P R S L P V R T P _ GF X_ I M O N

D F G T _ VR_ EN R2 3 5 R4 5 * 1K _ 04 1 0 0 _ 1% _ 0 4 G F X _ I M ON

35 35

1 . 5 V S _C P U

VD DQ 6A
V D D Q1 V D D Q2 V D D Q3 V D D Q4 V D D Q5 V D D Q6 V D D Q7 V D D Q8 V D D Q9 V D D Q 10 V D D Q 11 V D D Q 12 V D D Q 13 V D D Q 14 V D D Q 15 V D D Q 16 V D D Q 17 V D D Q 18 AJ 1 AF 1 AE7 AE4 AC 1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 C4 5 1 u _6 . 3 V _ X 5 R _ 04 C 343 2 2 u _ 6 . 3 V _ X5 R _ 0 8 C3 3 7 2 2u _ 6 . 3 V _ X 5 R _ 0 8 C 58 1 0 u _ 6. 3V _X 5 R _ 0 6 C5 1 10 u _ 6 . 3 V _ X 5 R _ 0 6

C3 4 8 1 u _6 . 3 V _ X 5 R _ 04

C 350 1 u _ 6 . 3 V _ X 5R _ 0 4

C3 9 1 u_ 6 . 3 V _ X 5 R _0 4

C 57 1 u _ 6 . 3 V _ X5 R _ 0 4

+C 4 3 1 0 0 u _ 6. 3V _ B _ A

1 .1 VS _ VT T

V T T 0 _ 59 V T T 0 _ 60 V T T 0 _ 61 V T T 0 _ 62

P1 0 N1 0 L 10 K1 0

C3 2 8 1 0 u_ 6 . 3 V _ X 5 R _0 6

C 65 1 0 u _ 6 . 3 V _ X5 R _ 0 6

1 .1 V S_ V T T V T T 1 _ 63 V T T 1 _ 64 V T T 1 _ 65 V T T 1 _ 66 V T T 1 _ 67 V T T 1 _ 68 J 22 J 20 J 18 H2 1 H2 0 H1 9

C3 2 2 2 2 u_ 6 . 3 V _ X 5 R _0 8

C 320 2 2 u _ 6 . 3 V _ X5 R _ 0 8

1 .8 V S V C C P L L1 V C C P L L2 V C C P L L3 L 26 L 27 M2 6

V CC PLL 0 .6A
C4 1 1 u _6 . 3 V _ X 5 R _ 04 C 37 1 u _ 6 . 3 V _ X 5R _ 0 4 C3 8 2 . 2 u_ 1 6 V _ X 5 R _ 0 6 C4 2 4 . 7 u _6 . 3 V _ X 5 R _0 6 C 46 1 0 u _6 . 3 V _X 5 R _ 06 C 44 1 0 u _ 6 .3 V _ X 5 R_ 0 6

P Z 9 8 9 2 7 -3 64 1 -0 1 F

1 .5 V S _ C P U 4 ,3 1 1 .8 V S 20 , 3 3 VG F X_ CO R E 3 5 1 . 1 V S _ V T T 2 , 4 , 6 , 1 4 , 1 5 , 1 6 , 1 9, 20 , 2 1 , 3 4 , 3 5 , 3 6 1 .5 V 4, 9, 10 , 1 1 , 2 1 , 2 3 , 2 7 , 2 9, 31 , 3 3 , 3 6

B - 8 Processor 5/7

Schematic Diagrams

Processor 6/7

PROCESSOR
U 16H AT2 0 AT1 7 AR3 1 AR2 8 AR2 6 AR2 4 AR2 3 AR2 0 AR1 7 AR1 5 AR1 2 AR 9 AR 6 AR 3 AP2 0 AP1 7 AP1 3 AP1 0 AP7 AP4 AP2 AN3 4 AN3 1 AN2 3 AN2 0 AN1 7 AM 29 AM 27 AM 25 AM 20 AM 17 AM 14 AM 11 AM8 AM5 AM2 AL3 4 AL3 1 AL2 3 AL2 0 AL1 7 AL1 2 AL 9 AL 6 AL 3 AK2 9 AK2 7 AK2 5 AK2 0 AK1 7 AJ3 1 AJ2 3 AJ2 0 AJ1 7 AJ1 4 AJ1 1 AJ 8 AJ 5 AJ 2 AH3 5 AH3 4 AH3 3 AH3 2 AH3 1 AH3 0 AH2 9 AH2 8 AH2 7 AH2 6 AH2 0 AH1 7 AH1 3 AH 9 AH 6 AH 3 AG1 0 AF8 AF4 AF2 AE3 5 VS S1 VS S2 VS S3 VS S4 VS S5 VS S6 VS S7 VS S8 VS S9 VS S1 0 VS S1 1 VS S1 2 VS S1 3 VS S1 4 VS S1 5 VS S1 6 VS S1 7 VS S1 8 VS S1 9 VS S2 0 VS S2 1 VS S2 2 VS S2 3 VS S2 4 VS S2 5 VS S2 6 VS S2 7 VS S2 8 VS S2 9 VS S3 0 VS S3 1 VS S3 2 VS S3 3 VS S3 4 VS S3 5 VS S3 6 VS S3 7 VS S3 8 VS S3 9 VS S4 0 VS S4 1 VS S4 2 VS S4 3 VS S4 4 VS S4 5 VS S4 6 VS S4 7 VS S4 8 VS S4 9 VS S5 0 VS S5 1 VS S5 2 VS S5 3 VS S5 4 VS S5 5 VS S5 6 VS S5 7 VS S5 8 VS S5 9 VS S6 0 VS S6 1 VS S6 2 VS S6 3 VS S6 4 VS S6 5 VS S6 6 VS S6 7 VS S6 8 VS S6 9 VS S7 0 VS S7 1 VS S7 2 VS S7 3 VS S7 4 VS S7 5 VS S7 6 VS S7 7 VS S7 8 VS S7 9 VS S8 0 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 V SS1 00 V SS1 01 V SS1 02 V SS1 03 V SS1 04 V SS1 05 V SS1 06 V SS1 07 V SS1 08 V SS1 09 V SS1 10 V SS1 11 V SS1 12 V SS1 13 V SS1 14 V SS1 15 V SS1 16 V SS1 17 V SS1 18 V SS1 19 V SS1 20 V SS1 21 V SS1 22 V SS1 23 V SS1 24 V SS1 25 V SS1 26 V SS1 27 V SS1 28 V SS1 29 V SS1 30 V SS1 31 V SS1 32 V SS1 33 V SS1 34 V SS1 35 V SS1 36 V SS1 37 V SS1 38 V SS1 39 V SS1 40 V SS1 41 V SS1 42 V SS1 43 V SS1 44 V SS1 45 V SS1 46 V SS1 47 V SS1 48 V SS1 49 V SS1 50 V SS1 51 V SS1 52 V SS1 53 V SS1 54 V SS1 55 V SS1 56 V SS1 57 V SS1 58 V SS1 59 V SS1 60 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD1 0 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W3 5 W3 4 W3 3 W3 2 W3 1 W3 0 W2 9 W2 8 W2 7 W2 6 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R 10 P8 P4 P2 N 35 N 34 N 33 N 32 N 31 N 30 N 29 N 28 N 27 N 26 N6 M10 L 35 L 32 L 29 L8 L5 L2 K34 K33 K30

6/7

( GND )
U1 6I

VSS

K27 K9 K6 K3 J 32 J 30 J 21 J 19 H 35 H 32 H 28 H 26 H 24 H 22 H 18 H 15 H 13 H 11 H8 H5 H2 G 34 G 31 G 20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D 33 D 30 D 26 D9 D6 D3 C 34 C 32 C 29 C 28 C 24 C 22 C 20 C 19 C 16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9

VSS16 1 VSS16 2 VSS16 3 VSS16 4 VSS16 5 VSS16 6 VSS16 7 VSS16 8 VSS16 9 VSS17 0 VSS17 1 VSS17 2 VSS17 3 VSS17 4 VSS17 5 VSS17 6 VSS17 7 VSS17 8 VSS17 9 VSS18 0 VSS18 1 VSS18 2 VSS18 3 VSS18 4 VSS18 5 VSS18 6 VSS18 7 VSS18 8 VSS18 9 VSS19 0 VSS19 1 VSS19 2 VSS19 3 VSS19 4 VSS19 5 VSS19 6 VSS19 7 VSS19 8 VSS19 9 VSS20 0 VSS20 1 VSS20 2 VSS20 3 VSS20 4 VSS20 5 VSS20 6 VSS20 7 VSS20 8 VSS20 9 VSS21 0 VSS21 1 VSS21 2 VSS21 3 VSS21 4 VSS21 5 VSS21 6 VSS21 7 VSS21 8 VSS21 9 VSS22 0 VSS22 1 VSS22 2 VSS22 3 VSS22 4 VSS22 5 VSS22 6 VSS22 7 VSS22 8 VSS22 9 VSS23 0 VSS23 1 VSS23 2 VSS23 3

B.Schematic Diagrams

Sheet 8 of 40 Processor 6/7

VSS
AT35 AT1 AR34 B34 B2 B1 A35

PZ98 92 7- 364 1- 01F

PZ989 27 -36 41 -01 F

NCTF

VSS_N CTF1 VSS_N CTF2 VSS_N CTF3 VSS_N CTF4 VSS_N CTF5 VSS_N CTF6 VSS_N CTF7

Processor 6/7 B - 9

Schematic Diagrams

Processor 7/7
PROCESSOR 7/7
U 16E AP230 2GN R S V D 32 R S V D 33 AP2 5 AL 2 5 AL 2 4 AL 2 2 AJ 3 3 A G9 M2 7 L28 J17 H1 7 G2 5 G1 7 E3 1 E3 0 R R R R R R R R R R R R R R SVD SVD SVD SVD SVD SVD SVD SVD SVD SVD SVD SVD SVD SVD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A J 13 A J 12 V R E F _ C H _ A _ D I MM Q8 * A O 34 0 2 L S D M V R E F _ D Q _D I M 0 R 36 * 1 K _ 1% _ 0 4

( RESERVED )
1 .5 V

PCI-Expre ss Configuration Sele ct

CFG0

1 : Single PE G 0 : Bifurcati on enable


R 2 24 * 3 . 0 1K _0 4 R3 5 R3 9 * 0 _0 4 * 0 _0 4 V R E F _ CH _ A _ DIM M V R E F _ CH _ B _ DIM M

R S V D 34 R S V D 35 R S V D 36 R S V D _ N C T F _ 37 R S V D 38 R S V D 39

A H2 5 AK2 6 A L 26 A R2 A J 26 A J 27

R2 1 0 *1 0 0 K _ 0 4

R 37 * 1 K _ 1% _ 0 4 D R A MR S T _ C T R L 4 , 1 9 ? ? IBEX CONTRO L

B.Schematic Diagrams

CF G 0

1 0 M V R E F _ D Q _D I M 0 1 1 M V R E F _ D Q _D I M 1

Sheet 9 of 40 Processor 7/7

CFG3 - PC I-Express Static Lane Reversal 1 : Normal Op eration 0 : Lane Numb ers Reverse d 15 -> 0, 14 > 1, ...

R S V D _ N C T F _ 40 R S V D _ N C T F _ 41 R S V D _ N C T F _ 42 R S V D _ N C T F _ 43

AP1 AT2 1 .5 V AT3 A R1 AP2 302GN R 38 * 1 K _ 1% _ 0 4 M V R E F _ D Q _D I M 1

CFG3

CF G 3

R 2 18

* 3 . 0 1K _0 4

C F G0

CFG4 - Di splay Port Presence


1 : Di sa b ll ed ; No p h ys ic al D is p la y Po rt a tt ac he d t o Em be dd e d Di sp la y P or t

C F G3 C F G4

C F G7

0 : En ab l ed ; An e xt e rn al D is pl a y Po rt de vi ce i s c on ne ct ed to t he E mb e dd ed is pl ay P o rt
? ?? ? ,? ?? ?

RESERVED

CFG4

CF G 4

R 2 17

* 3 . 0 1K _0 4

R 20 8

* 0 _ 04

RS V D8 6

A M3 0 A M2 8 AP3 1 AL 3 2 AL 3 0 A M3 1 A N2 9 A M3 2 AK3 2 AK3 1 AK2 8 AJ 2 8 A N3 0 A N3 2 AJ 3 2 AJ 2 9 AJ 3 0 AK3 0 H1 6

C C C C C C C C C C C C C C C C C C R

F G [ 0] F G [ 1] F G [ 2] F G [ 3] F G [ 4] F G [ 5] F G [ 6] F G [ 7] F G [ 8] F G [ 9] F G [ 10 ] F G [ 11 ] F G [ 12 ] F G [ 13 ] F G [ 14 ] F G [ 15 ] F G [ 16 ] F G [ 17 ] S V D _ TP _8 6

R S V D 45 R S V D 46 R S V D 47 R S V D 48 R S V D 49 R S V D 50 R S V D 51 R S V D 52 R S V D 53 R S V D _ N C T F _ 54 R S V D _ N C T F _ 55 R S V D _ N C T F _ 56 R S V D _ N C T F _ 57 R S V D 58

A L 28 A L 29 AP3 0 AP3 2 A L 27 A T 31 A T 32 AP3 3 A R3 3 A T 33 A T 34 AP3 5 A R3 5 A R3 2

V R E F _ C H _ B _ D I MM

Q9 * A O 34 0 2 L S D

R2 1 3 *1 0 0 K _ 0 4

R 40 * 1 K _ 1% _ 0 4 D R A MR S T _ C T R L 4 , 1 9 ? ? IBEX CONTRO L

RSV D86 Con nect t o GND B1 9 A1 9 CF G 7 R 2 21 * 3 . 0 1K _0 4 R2 0 4 R2 0 3 * 1 0 mi l _ s ho rt _ 0 4 * 1 0 mi l _ s ho rt _ 0 4 H _ R S V D 17 _ R H _ R S V D 18 _ R A2 0 B2 0 U9 T9 A C9 AB9

R S V D _ T P _ 59 R S V D _ T P _ 60 K EY R S V D 62 R S V D 63 R S V D 64 R S V D 65

E1 5 F15 A2 D1 5 C1 5 A J 15 A H1 5

RS V D6 4 _ R RS V D6 5 _ R

R2 1 4 R2 1 5

* 1 0 mi l _ s ho rt _ 0 4 * 1 0 mi l _ s ho rt _ 0 4

R SVD 1 5 R SVD 1 6 R SVD 1 7 R SVD 1 8 R SVD 1 9 R SVD 2 0 R SVD 2 1 R SVD 2 2 RS V D RS V D RS V D RS V D RS V D RS V D RS V D RS V D RS V D RS V D _ T P _ 66 _ T P _ 67 _ T P _ 68 _ T P _ 69 _ T P _ 70 _ T P _ 71 _ T P _ 72 _ T P _ 73 _ T P _ 74 _ T P _ 75

CFG7 Clar ksf ield (on ly f or earl y sa mpl es pre- ES1 ) - Conn ect to GND with 3. 01K Ohm/ 5% resi sto r

C1 A3

R S V D _ N C TF _2 3 R S V D _ N C TF _2 4

AA5 AA4 R8 A D3 A D2 AA2 AA1 R9 A G7 AE3

J29 J28 A3 4 A3 3 C3 5 B3 5

R SVD 2 6 R SVD 2 7 R S V D _ N C TF _2 8 R S V D _ N C TF _2 9 R S V D _ N C TF _3 0 R S V D _ N C TF _3 1

RS V D RS V D RS V D RS V D RS V D RS V D RS V D RS V D RS V D RS V D

_ T P _ 76 _ T P _ 77 _ T P _ 78 _ T P _ 79 _ T P _ 80 _ T P _ 81 _ T P _ 82 _ T P _ 83 _ T P _ 84 _ T P _ 85

V4 V5 N2 A D5 A D7 W3 W2 N3 AE5 A D9 T P _ RS V D8 6

VSS

AP3 4

VSS (AP3 4) can be left NC is CRB impl ementation ; EDS/DG recommen dation to GND

P Z 9 89 2 7 -3 6 41 -0 1 F

1. 5V

4 , 1 0 , 1 1, 2 1 , 2 3 , 2 7 , 29 , 3 1 , 3 3 , 3 6

B - 10 Processor 7/7

Schematic Diagrams

DDRIII SO-DIMM_0
SO-DIMM A
5 M_ A _ A [ 1 5 : 0 ] M_ A _ A 0 M_ A _ A 1 M_ A _ A 2 M_ A _ A 3 M_ A _ A 4 M_ A _ A 5 M_ A _ A 6 M_ A _ A 7 M_ A _ A 8 M_ A _ A 9 M_ A _ A 1 0 M_ A _ A 1 1 M_ A _ A 1 2 M_ A _ A 1 3 M_ A _ A 1 4 M_ A _ A 1 5

CHANGE TO STANDARD

JD I M M2 A 98 97 96 95 92 91 90 86 89 85 1 07 84 83 1 19 80 78 1 09 1 08 79 1 14 1 21 1 01 1 03 1 02 1 04 73 74 1 15 1 10 1 13 1 97 2 01 2 02 2 00 1 16 1 20 M_ A _ D M M_ A _ D M M_ A _ D M M_ A _ D M M_ A _ D M M_ A _ D M M_ A _ D M M_ A _ D M M_ A _ D Q M_ A _ D Q M_ A _ D Q M_ A _ D Q M_ A _ D Q M_ A _ D Q M_ A _ D Q M_ A _ D Q M_ A _ D Q M_ A _ D Q M_ A _ D Q M_ A _ D Q M_ A _ D Q M_ A _ D Q M_ A _ D Q M_ A _ D Q 0 1 2 3 4 5 6 7 S0 S1 S2 S3 S4 S5 S6 S7 S# 0 S# 1 S# 2 S# 3 S# 4 S# 5 S# 6 S# 7 11 28 46 63 1 36 1 53 1 70 1 87 12 29 47 64 1 37 1 54 1 71 1 88 10 27 45 62 1 35 1 52 1 69 1 86 A A A A A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 / A P 11 12 / B C # 13 14 15 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 DQ 9 DQ 1 0 DQ 1 1 DQ 1 2 DQ 1 3 DQ 1 4 DQ 1 5 DQ 1 6 DQ 1 7 DQ 1 8 DQ 1 9 DQ 2 0 DQ 2 1 DQ 2 2 DQ 2 3 DQ 2 4 DQ 2 5 DQ 2 6 DQ 2 7 DQ 2 8 DQ 2 9 DQ 3 0 DQ 3 1 DQ 3 2 DQ 3 3 DQ 3 4 DQ 3 5 DQ 3 6 DQ 3 7 DQ 3 8 DQ 3 9 DQ 4 0 DQ 4 1 DQ 4 2 DQ 4 3 DQ 4 4 DQ 4 5 DQ 4 6 DQ 4 7 DQ 4 8 DQ 4 9 DQ 5 0 DQ 5 1 DQ 5 2 DQ 5 3 DQ 5 4 DQ 5 5 DQ 5 6 DQ 5 7 DQ 5 8 DQ 5 9 DQ 6 0 DQ 6 1 DQ 6 2 DQ 6 3 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 1 29 1 31 1 41 1 43 1 30 1 32 1 40 1 42 1 47 1 49 1 57 1 59 1 46 1 48 1 58 1 60 1 63 1 65 1 75 1 77 1 64 1 66 1 74 1 76 1 81 1 83 1 91 1 93 1 80 1 82 1 92 1 94 M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D M_ A _ D Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q1 0 Q1 1 Q1 2 Q1 3 Q1 4 Q1 5 Q1 6 Q1 7 Q1 8 Q1 9 Q2 0 Q2 1 Q2 2 Q2 3 Q2 4 Q2 5 Q2 6 Q2 7 Q2 8 Q2 9 Q3 0 Q3 1 Q3 2 Q3 3 Q3 4 Q3 5 Q3 6 Q3 7 Q3 8 Q3 9 Q4 0 Q4 1 Q4 2 Q4 3 Q4 4 Q4 5 Q4 6 Q4 7 Q4 8 Q4 9 Q5 0 Q5 1 Q5 2 Q5 3 Q5 4 Q5 5 Q5 6 Q5 7 Q5 8 Q5 9 Q6 0 Q6 1 Q6 2 Q6 3

M_ A _ D Q [ 6 3 : 0]

J D I MM 2 B 1 .5 V 75 76 81 82 87 88 93 94 99 10 0 10 5 10 6 11 1 11 2 11 7 11 8 12 3 12 4 19 9 3 .3 VS R 72 4 , 11 T S # _ D I MM 0_ 1 4 , 11 D D R 3 _ D R A MR S T # C1 7 C1 8 201 0/01/ 08 2 . 2u _ 6 . 3 V _ X5 R _ 04 0 . 1u _ 1 0 V _ X7 R _0 4 10 K _ 0 4 77 12 2 12 5 19 8 30 VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD VD D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 0 D1 1 D1 2 D1 3 D1 4 D1 5 D1 6 D1 7 D1 8 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

La yout Note : si gna l /spa c e/ signa l : 8/4/8

3 .3 V S

B.Schematic Diagrams

2 0mils
C1 0 1 1u _ 6 . 3 V _ X5 R _ 04 C 10 2 0 . 1 u_ 1 0 V _ X 7R _ 04

5 5 5 5 5 5 5 5 5 5 5 5 5 5

M _ A _B S 0 M _ A _B S 1 M _ A _B S 2 M _ CS # 0 M _ CS # 1 M_ C L K _ D D R 0 M_ C L K _ D D R # 0 M_ C L K _ D D R 1 M_ C L K _ D D R # 1 M _ CK E 0 M _ CK E 1 M _ A_ CAS # M _ A_ RAS # M _ A_ W E#

S A 0 _D I M 0 S A 1 _D I M 0

2 , 1 1 C L K _ S C LK 2 , 1 1 C L K _ S D A TA 3 .3 VS 5 5 5 M _ OD T0 M _ OD T1 M _A _D M[ 7 : 0 ]

B A0 B A1 B A2 S 0# S 1# C K0 C K0 # C K1 C K1 # C KE0 C KE1 C AS# R AS# W E# S A0 S A1 S CL S DA O D T0 O D T1 D D D D D D D D D D D D D D D D D D D D D D D D M M M M M M M M Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q 0 1 2 3 4 5 6 7 S0 S1 S2 S3 S4 S5 S6 S7 S 0# S 1# S 2# S 3# S 4# S 5# S 6# S 7#

V D DS P D N C1 N C2 N CT E ST EV ENT # R ESET#

Sheet 10 of 40 DDRIII SO-DIMM _0

20m ils CU? ?


9 MV R E F _ D Q _ D I M 0 ? ? C PU SU PPORT

1 12 6 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43

VR EF _ D Q VR EF _ C A VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS S1 S2 S3 S4 S5 S6 S7 S8 S9 S 10 S 11 S 12 S 13 S 14 S 15

R1 9

*0 _ 0 4 M VR EF _ DIM 0 C 89 C 88

R1 8

0 _0 4

R N3 1 0 K _ 8 P 4 R_ 0 4 1 8 S A 1 _ DIM 1 2 7 S A 0 _ DIM 1 3 6 S A 1 _ DIM 0 4 5 S A 0 _ DIM 0

S A 1 _ DIM 1 1 1 S A 0 _ DIM 1 1 1

2 . 2 u _6 . 3 V _ X 5 R _ 0 4 0 . 1 u _1 0 V _ X 7 R _ 0 4 20 10/01 /08

2.2 U? ? : 6-07-225 11-2A0

V TT _ ME M V T T1 V T T2 G1 G2 203 204 G ND 1 G ND 2

M _A _D QS [ 7: 0 ]

A S 0 A 62 1 -U 2S N -7 F

5 M _ A _ D Q S # [ 7: 0 ]

C LOSE TO SO- DI MM _ 0
M V R E F _D I M 0

1 .5 V

A S 0 A 6 2 1-U 2 S N -7 F

1 .5 V + C3 6 0 *2 2 0 u_ 2 . 5 V _ B _ A + C 32 9 5 6 0 u_ 2 . 5 V _ 6 . 6* 6 . 6 *5 . 9 C4 9 1 0u _ 6 . 3 V _ X5 R _ 06 C 69 1 0 u _6 . 3 V _ X 5 R _ 0 6 C 84 * 1 0 u_ 6 . 3 V _ X 5R _ 06 C6 2 1 u_ 6 . 3 V _ X 5R _ 0 4 C 82 * 1u _ 6 . 3 V _ X5 R _0 4 C 76 * 1 u_ 6 . 3 V _ X 5R _ 0 4 C7 1 1 u_ 6 . 3 V _ X 5R _ 04 C 75 * 1u _ 6 . 3 V _ X5 R _0 4 + C 32 3 *5 6 0 u _2 . 5 V _ 6 . 6 *6 . 6 *5 . 9

R 63

1 K _ 1 % _0 4

R6 5 1 K _ 1 %_ 0 4

C9 2 0. 1u _ 1 0 V _ X7 R _0 4

1. 5V

C8 0 0 . 1 u_ 1 0 V _ X7 R _ 04

C 52 0 . 1 u _1 0 V _ X 7 R _ 0 4

C 59 * 0 . 1 u_ 1 0 V _ X 7R _ 04

C5 5 0 . 1u _ 1 0 V _ X7 R _ 04

C 60 * 0. 1 u _ 1 0V _X 7 R _ 0 4

C 64 * 0 . 1 u_ 1 0 V _ X 7R _ 04

C6 6 *0 . 1 u _ 10 V _ X 7 R _ 0 4

C 72 0 . 1 u _1 0 V _ X 7 R _ 0 4

C 85 0 . 1 u _ 1 0V _ X 7 R _ 0 4

C4 8 *0 . 1 u _1 0 V _ X 7 R _ 0 4

4 , 9 , 11 , 2 1 , 2 3 , 27 , 2 9 , 3 1 , 33 , 3 6 1 . 5 V 11 , 3 3 V T T _ ME M 2 , 1 1 , 1 2, 13 , 1 4 , 1 5, 16 , 1 7 , 1 8, 19 , 2 0 , 2 1, 23 , 2 4 , 2 5 , 26 , 2 7 , 2 8 , 29 , 3 0 , 3 1 , 35 , 3 6 3 . 3 V S

V T T _ ME M

C1 0 6 1 0u _ 6 . 3 V _ X5 R _ 06

C 11 0 * 1u _ 6 . 3 V _ X5 R _ 04

C 108 1 u _ 6 . 3 V _ X5 R _0 4

C1 1 1 1 u_ 6 . 3 V _ X 5R _ 0 4

C 11 2 * 1u _ 6 . 3 V _ X5 R _0 4

DDRIII SO-DIMM_0 B - 11

Schematic Diagrams

DDRIII SO-DIMM_1
SO-DIMM B
5 M_ B _ A [ 1 5 : 0 ]

CHANGE TO STANDARD
JD I M M1 A M_ B _ A 0 M_ B _ A 1 M_ B _ A 2 M_ B _ A 3 M_ B _ A 4 M_ B _ A 5 M_ B _ A 6 M_ B _ A 7 M_ B _ A 8 M_ B _ A 9 M_ B _ A 1 0 M_ B _ A 1 1 M_ B _ A 1 2 M_ B _ A 1 3 M_ B _ A 1 4 M_ B _ A 1 5 98 97 96 95 92 91 90 86 89 85 1 07 84 83 1 19 80 78 1 09 1 08 79 1 14 1 21 1 01 1 03 1 02 1 04 73 74 1 15 1 10 1 13 1 97 2 01 2 02 2 00 1 16 1 20 M_ B _ D M M_ B _ D M M_ B _ D M M_ B _ D M M_ B _ D M M_ B _ D M M_ B _ D M M_ B _ D M M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q 0 1 2 3 4 5 6 7 S0 S1 S2 S3 S4 S5 S6 S7 S# 0 S# 1 S# 2 S# 3 S# 4 S# 5 S# 6 S# 7 11 28 46 63 1 36 1 53 1 70 1 87 12 29 47 64 1 37 1 54 1 71 1 88 10 27 45 62 1 35 1 52 1 69 1 86 A A A A A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 / A P 11 12 / B C # 13 14 15 D Q0 D Q1 D Q2 D Q3 D Q4 D Q5 D Q6 D Q7 D Q8 D Q9 D Q 10 D Q 11 D Q 12 D Q 13 D Q 14 D Q 15 D Q 16 D Q 17 D Q 18 D Q 19 D Q 20 D Q 21 D Q 22 D Q 23 D Q 24 D Q 25 D Q 26 D Q 27 D Q 28 D Q 29 D Q 30 D Q 31 D Q 32 D Q 33 D Q 34 D Q 35 D Q 36 D Q 37 D Q 38 D Q 39 D Q 40 D Q 41 D Q 42 D Q 43 D Q 44 D Q 45 D Q 46 D Q 47 D Q 48 D Q 49 D Q 50 D Q 51 D Q 52 D Q 53 D Q 54 D Q 55 D Q 56 D Q 57 D Q 58 D Q 59 D Q 60 D Q 61 D Q 62 D Q 63 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 12 9 13 1 14 1 14 3 13 0 13 2 14 0 14 2 14 7 14 9 15 7 15 9 14 6 14 8 15 8 16 0 16 3 16 5 17 5 17 7 16 4 16 6 17 4 17 6 18 1 18 3 19 1 19 3 18 0 18 2 19 2 19 4 M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q M_ B _ D Q 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 M_ B _ D Q[ 6 3 : 0 ] 5 1 .5 V J D I M M1 B

La y out Not e: si gnal /spa c e /si gna l : 8/4/8

B.Schematic Diagrams

Sheet 11 of 40 DDRIII SO-DIMM _1

5 5 5 5 5 5 M 5 M 5 M 5 M 5 5 5 5 5 10 10 2 , 10 2 ,1 0 5 5 5

M_ B _ B S 0 M_ B _ B S 1 M_ B _ B S 2 M_ C S #2 M_ C S #3 _C L K _ D D R 2 _C L K _ D D R # 2 _C L K _ D D R 3 _C L K _ D D R # 3 M_ C K E 2 M_ C K E 3 M_ B _ C A S # M_ B _ R A S # M_ B _ W E # S A 0 _ DIM 1 S A 1 _ DIM 1 C LK _S C L K CL K_ SD A T A M_ OD T 2 M_ OD T 3 M_ B _ D M [ 7 : 0]

SA 0 _ DIM 1 SA 1 _ DIM 1

B A0 B A1 B A2 S 0# S 1# C K0 C K0 # C K1 C K1 # C KE0 C KE1 C AS# R AS# W E# S A0 S A1 S CL S DA O DT 0 O DT 1 D D D D D D D D D D D D D D D D D D D D D D D D M0 M1 M2 M3 M4 M5 M6 M7 QS QS QS QS QS QS QS QS QS QS QS QS QS QS QS QS 0 1 2 3 4 5 6 7 0# 1# 2# 3# 4# 5# 6# 7#

3 . 3V S

75 76 81 82 87 88 93 94 99 1 00 1 05 1 06 1 11 1 12 1 17 1 18 1 23 1 24

20m ils
C1 0 3 1 u _6 . 3 V _ X 5R _ 0 4 C1 0 4 0. 1u _ 1 0 V _X 7 R _0 4

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

1 99 77 1 22 1 25 1 98 30

VDD SP D NC 1 NC 2 N C TE S T EV ENT # RE S E T #

4 , 1 0 T S # _D I MM 0 _ 1 4 ,1 0 DD R3 _ DR A M RS T # C 21 C 22 2 . 2 u _6 . 3 V _ X 5 R _ 0 4 0 . 1 u _1 0 V _ X 7R _ 0 4

1 1 26

VREF _ D Q VREF _ C A VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS1 0 VSS1 1 VSS1 2 VSS1 3 VSS1 4 VSS1 5

9 M V R E F _D Q_ D I M1

R 22

* 0 _0 4

R2 1

0 _0 4 2 . 2 u _6 . 3 V _ X 5 R _ 0 4 0 . 1 u _1 0 V _ X 7R _ 0 4 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43

M V R E F _D I M1 C 91 C 90

VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS

S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 S 24 S 25 S 26 S 27 S 28 S 29 S 30 S 31 S 32 S 33 S 34 S 35 S 36 S 37 S 38 S 39 S 40 S 41 S 42 S 43 S 44 S 45 S 46 S 47 S 48 S 49 S 50 S 51 S 52

44 48 49 54 55 60 61 65 66 71 72 12 7 12 8 13 3 13 4 13 8 13 9 14 4 14 5 15 0 15 1 15 5 15 6 16 1 16 2 16 7 16 8 17 2 17 3 17 8 17 9 18 4 18 5 18 9 19 0 19 5 19 6

2.2U? ? :6-07-22511-2A0

V TT _ ME M V T T1 V T T2 G1 G2 20 3 20 4 GN D 1 GN D 2

M_ B _ D Q S [ 7 : 0 ]

A S 0 A 6 2 1-U A S N -7 F

5 M_ B _ D Q S # [ 7 : 0 ]

A S 0 A 6 2 1-U A S N -7 F

CLOS E TO SO -DI M M_ 1 La y out Not e:


1 .5 V M V R E F _D I M 1

S O- DIM M _ 1 i s pl a ce d f a rt he r from the G M CH t ha n SO -DI M M _0

1 .5 V

R 64

1 K _ 1 % _ 04

R 66 C 86 *1 0 u _ 6. 3 V _ X 5 R _ 0 6 C 50 1 0 u _6 . 3 V _ X 5R _ 0 6 C 68 1 0 u _ 6. 3 V _ X 5 R _ 0 6 C7 7 *1 u _6 . 3 V _ X 5R _ 0 4 C5 4 1u _ 6 . 3 V _ X5 R _0 4 C7 8 1 u_ 6 . 3 V _ X 5R _ 04 C 70 1 u _6 . 3 V _ X 5 R _ 0 4 C 61 * 1u _ 6 . 3 V _ X5 R _0 4 1 K _ 1 %_ 0 4

C9 3 0. 1u _ 1 0V _X 7 R _ 0 4

1 .5 V

C 11 6 0 . 1 u_ 1 0 V _ X 7R _ 04

C 24 0 . 1 u _1 0 V _ X 7R _ 0 4

C 56 0 . 1 u _ 10 V _ X 7 R _ 0 4

C2 3 9 0. 1 u _ 1 0V _ X 7 R _ 0 4

C6 3 0. 1u _ 1 0V _X 7 R _ 0 4

C7 3 0 . 1 u_ 1 0 V _ X7 R _0 4

C 79 0 . 1 u_ 1 0 V _ X 7R _ 04

C 83 0 . 1 u _1 0 V _ X 7R _ 0 4

C 47 0 . 1 u _ 10 V _ X 7 R _ 0 4

C7 4 0. 1 u _ 1 0V _ X 7 R _ 0 4

4 , 9, 10 , 2 1 , 2 3, 27 , 2 9 , 3 1, 3 3 , 3 6 1 . 5V 1 0 , 3 3 V T T _M E M 2, 10 , 1 2 , 1 3, 1 4 , 1 5 , 1 6, 1 7 , 1 8 , 19 , 2 0 , 2 1 , 23 , 2 4 , 2 5, 26 , 2 7 , 2 8, 29 , 3 0 , 3 1, 3 5 , 3 6 3 . 3V S

V T T _ ME M

C 10 7 1 0 u_ 6 . 3 V _ X 5R _ 06

C 11 4 1 u _ 6. 3 V _ X 5 R _ 0 4

C 1 15 * 1 u_ 6 . 3 V _ X 5R _ 04

C1 0 9 1u _ 6 . 3 V _X 5 R _0 4

C1 1 3 *1 u _6 . 3 V _ X 5 R _ 0 4

B - 12 DDRIII SO-DIMM_1

Schematic Diagrams

LVDS, Inverter
PANEL CONNECTOR
COSTDOWN
VIN V IN_ L CD 3 .3 V S 2 1 3 R N6 4 2 . 2 K _ 4P 2R _0 4

E DID M ode

? ? ? ?
8 0mi ls
J _ LC D 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 87 2 1 6-3 0 0 6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 P _ D D C _D A T A P _ D D C _C LK B R I GH TN E S S I N V _ B L ON LV D S -L 2N LV D S -L 2P L V D S -L 2 N 1 7 L V D S -L 2 P 1 7 3 . 3V S B RIG HT N E S S 2 8 P _ DDC _ DA T A 1 7 P _ DDC _ CL K 1 7

L25

*1 5 m il _ s ho rt _ 0 6

C 30 7 0 . 1 u_ 5 0 V _Y 5 V _ 06

C 3 04 0 . 1 u _5 0 V _ Y 5 V _ 06

C 30 1 0 . 1 u _5 0 V _ Y 5 V _ 06 17 17 17 17 17 17 L V D S -LC L K N LV D S -L C L K P L V D S -L 1 N L V D S -L1 P L V D S -L 0 N L V D S -L0 P L V D S -L C L K N L V D S -L C L K P L V D S -L 1N L V D S -L 1P L V D S -L 0N L V D S -L 0P

B.Schematic Diagrams

CLOSE TO LVDS CONN. PIN

C2 9 8 0. 1u _ 10 V _ X 7 R _ 04 C 6 0 . 1 u _1 0 V _ X7 R _0 4

PL VD D C4

2 A
4. 7 u _ 6. 3 V _ X 5R _ 06

PANEL POWER
3. 3 V S

Sheet 12 of 40 LVDS, Inverter

2A
C 15 U 1 0. 1 u _ 10 V _ X 7 R _ 04 4 5 3 R 13 1 0 0 K _ 04 VIN VIN EN V O UT 1 PL VD D D1 4 C B R I GH T N E S S AC A

3 .3 V

2A

C 2 97 * 0 . 1u _ 1 0V _ X 5 R _ 0 4

*B A V 9 9 R E C T I F I E R 1 7 N B _ E NA V D D GN D G5 2 4 3A 2

INVERTER CONNECTOR
28 BKL _ EN R6 8 1 0K _ 0 4 B K L _ E N_ R R6 7 10 0 K _ 0 4 C 96 0 . 4 7u _ 1 0V _ Y 5V _ 0 4 3 .3 V U3 A 7 4L V C 08 P W 3 1 7 BL O N B LO N R6 9 10 0 K _ 0 4 19 S B _B L O N 3. 3V R 70 1 00 K _ 0 4 U 3D 7 4 LV C 0 8P W 11 13 7 14 Z12 03 10 7 R7 1 1 M_ 04 C 99 0 . 1 u _1 0 V _ X7 R _ 0 4 Z12 02 9 8 I N V _ B L ON 2 5 7 7 Z 1 2 01 4 6 * 0. 1u _ 1 0V _ X 5 R _ 04 14 3. 3V 3 .3 V

U 3B 7 4 LV C 0 8P W

14

C 95

U 3C 7 4 L V C0 8 P W

28 , 3 0

L ID_ S W #

12

16 , 2 8 A L L_ S Y S _P W R G D

3 0 , 3 1, 3 2 , 3 3, 3 4 , 3 5, 3 6 , 3 7 V I N 3 , 4 , 1 4 , 15 , 1 6 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 2 5, 2 9 , 3 0, 3 1 , 3 3, 3 4 , 3 5 3. 3 V 2 , 1 0, 1 1 , 1 3, 1 4 , 1 5, 16 , 1 7 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 25 , 2 6 , 2 7, 2 8 , 2 9, 3 0 , 3 1, 3 5 , 3 6 3. 3 V S 3 1 ,3 2 S YS 1 5 V

14

LVDS, Inverter B - 13

Schematic Diagrams

HDMI, CRT
HDMI PORT
FOR INTEL GRAPHIC
U2 17 H D MI B_ D 2B P 17 H D MI B_ D 2B N 17 H D MI B_ D 1B P 17 H D MI B_ D 1B N 17 H D MI B_ D 0B P 17 H D MI B_ D 0B N 17 H D MI B_ C LK B P 17 H D MI B_ C LK B N 1 7 H D MI _C TR LC LK 1 7 H D MI _C T R LD A TA H D MI _C T R LC L K H D MI _C T R LD A T A M_P OR T B_ H P D #_ R 3 . 3V S 39 38 42 41 45 44 48 47 9 8 7 25 32 10 3 4 6 34 35 I N _D 1 + I N _D 1 I N _D 2 + I N _D 2 I N _D 3 + I N _D 3 I N _D 4 + I N _D 4 SCL SDA HP D OE # D C C _E N # R T_ E N # PC0 PC1 R E XT OE _1 QE _2 OU T_ D 1+ OU T_D 1 OU T_ D 2+ OU T_D 2 OU T_ D 3+ OU T_D 3 OU T_ D 4+ OU T_D 4 SC L _S I N K S D A _S I N K H P D _S I N K V CC[ 1] V CC[ 2] V CC[ 3] V CC[ 4] V CC[ 5] V CC[ 6] V CC[ 7] V CC[ 8] G ND[ 1] G ND[ 2] G ND[ 3] G ND[ 4] G ND[ 5] G ND[ 6] G ND[ 7] G ND[ 8] G ND[ 9] GN D [ 10 ] 22 23 19 20 16 17 13 14 28 29 30 2 11 15 21 26 33 40 46 1 5 12 18 24 27 31 36 37 43 H D MI B_ D A TA 2P H D MI B_ D A TA 2N 5 VS H D MI B_ D A TA 1P H D MI B_ D A TA 1N H D MI B_ D A TA 0P H D MI B_ D A TA 0N H D MI B_ C LOC K P H D MI B_ C LOC K N H D MI B_ E XT1 _S C L H D MI B_ E XT1 _S D A H D MI B_ E XT1 _H P D 33 . VS C1 0. 1u _1 0V _X 7R _ 04 C 40 0. 1 u_ 10V _ X7 R _0 4 C3 1 01 . u_ 10 V_ X7 R _0 4 2 0K _1 %_0 4 R4 8 1 2 RN2 2. 2 K_ 4P 2 R _0 4 4 3 H D MI B_ C LOC K N H D MI B_ C LOC K P F OR E MI 1 L5 2 200 9. 06 .1 8 H D MI B_ E XT1 _S D A 18 16 14 12 10 *L VA R 0 40 2-24 0E 0 R 05P -L F *LV A R 04 02 -240 E 0R 0 5P -LF 8 6 4 2 + 5V D D C / C E C GN D S DA R E S E R VE D CE C T MD S C L OC K C L K S H I E LD T MD S C L OC K + TMD S D A TA 0S H I E LD 0 T MD S D A TA 0 + T MD S D A T A1 S HI EL D1 T MD S D A T A1 + S H I E LD 2 T MD S D A TA 2 + TMD S D A TA 2S CL RD1 B A V9 9 R E C TI F I E R AC AC AC C 32 7 10 u_6 . 3V _X 5R _ 06 C 32 4 22 u_ 6. 3V _ X5 R _0 8 H OT PL U G D ET E C T 19 17 15 13 11 L6 9 7 *LV A R 04 02 2 40 E 0R 05 P -LF R 43 5 3 1 *L VA R 0 40 2-24 0E 0 R 05P -L F R4 4 4 3 H D MI B _D A TA 0 N 1 2 H D MI B _ D AT A 0P *H D MI 20 12 F2 S F-9 00 T0 4-sh ort H D MI B_ E XT1 _S C L H D MI _ CE C FOR E MI H D MI B_ E XT1 _H P D 5V S

For ESD
RD2 RD3 B A V9 9 R E C TI F I E R B A V 99 R E C T F I IER R 20 7

L 27 1 _0 4

5 VS

1_ 04 J _H D MI 1

4 3 * H D MI 201 2F 2 SF -90 0T 04 -sho rt R4 2

B.Schematic Diagrams

R5 6 R4 7 ? ? ?

*4. 7 K_ 04 *0_ 04

Z4 30 4 D C C _E N # PC 0 PC 1 Z4 30 5 Z4 30 6 Z4 30 7

R2 8 3. 3 VS R4 9 R5 8 ? ? ?

49 9_ 1%_ 04 *4. 7 K _04 *4. 7 K _04

H D MI B_ D A TA 1N H D MI B_ D A TA 1P C2 6 0 . 1u _1 0V _X 7R _ 04 C 67 0. 1u _1 0V _X 7R _ 04

1 4

2 3

R 41

L8 4 3 H D MI B _D A TA 2 N 1 2 H D MI B _ D AT A 2P *H D MI 20 12 F2 S F-9 00 T0 4-sh ort

3 . 3V S R 26 P OR T C _H P D *1 0mi l _sh ort * 20 K_ 1% _04 17 P OR TC _ H P D P OR TC _ H P D D Q7 *MT N 70 02 Z H S3 M_P OR TB _ H PD #_R G R3 2 *2 0K _1 %_ 04 M_ P OR TB _H P D # _R R3 4

49

GN D P T N 33 60B B S P I N 4 9 =G N D

6-03-03360-03 0
PS 810 1 ( 6-0 3-0 810 1-0 32) PI N T O P IN
3. 3V S R 57 R 30 R 29 ? ? ? 4. 7 K_ 04 4. 7 K_ 04 *4 . 7 K _0 4 D C C _ EN # P C0 P C1

3 . 3V S

C 35 *0 . 1u _10 V _X 7R _ 04

R3 3

C 31 7 0. 1u _1 0V _X 7R _ 04

C 53 0. 1 u_ 10V _ X7 R _0 4

*7 . 5K _1 %_0 4

CRT PORT
17 D A C _ D D C AD A T A 17 D A C _ D D C AC L K 1 7 D A C _ H SY N C 17 D AC _ V SY N C 5V S 3 . 3V S 3. 3 VS

6-19-31001-264
3. 3V S 5 VS 1 7 D A C _R E D 1 7 D A C _GR E E N 1 7 D A C _B L U E 6 p_ 50 V _N P O_0 4 6 p_ 50 V_ N P O_04 6p _5 0V _N PO_ 04 R1 2 1 50 _1% _0 4 R 11 15 0_1 %_ 04 R 10 15 0_ 1% _0 4 R ED

J _C R T 1 108 A H 15 FS T 04N 1C 3 1 9 2 GR N BL U E 6 p_ 50V _ N PO _04 3 11 4 12 5 13 6 7 15 C 3 00 2 20 p_ 50 V_ N P O_0 4 C 30 2 10 00 p_5 0V _ X7 R _0 4 C 2 99 2 20p _5 0V _N PO_ 04 C 7 10 00 p_5 0V _ X7 R _0 4 8 GN D 1 GN D 2 DDCL K 14 DDCDA T A HS Y NC V S Y NC

10 11 13 15 1 2 7 8 0 . 22 u_ 50V _ 06 0. 2 2u _5 0V _0 6 0. 22 u_ 50 V _06

U1 5 D D C _I N 1 D D C _I N 2 SY N C _ I N 1 SY N C _ I N 2 VC C _ S Y N C VC C _ V I D EO VC C _ D D C BY P I P 47 72 C Z1 6

D D C _ OU T1 D D C _ OU T2 S Y N C _ OU T1 S Y N C _ OU T2 V I D E O_1 V I D E O_2 V I D E O_3 GN D

9 12 14 16 3 4 5 6 C R T _H S Y N C C R T _V S Y N C R1 5 R1 4 33 _04 33 _04

D D C D A TA D D C LK HS Y NC VS Y N C BL U E GR N RE D

6p _5 0V _N P O_0 4

6 p_ 50 V_ N P O_0 4

RN7 2. 2K _ 4P 2R _ 04 1 2 1 2

RN1 2. 2K _ 4P 2R _ 04

C 3 05

C 30 6

C 303

C M20 09- 02Q R P N:6 -02 -200 90- B60 I P47 72C Z16 PN :6- 02- 4772 1-B 60

2 , 10 , 11, 1 2, 1 4, 15 , 16 , 17, 1 8, 1 9, 20 , 21 , 2 3, 2 4, 2 5, 26 , 27 , 2 8, 2 9, 30 , 31 , 35, 3 6 3. 3 V S 2, 1 7, 20 , 21 , 2 6, 2 7, 30 , 31 , 35, 3 6 5V S

B - 14 HDMI, CRT

C1 6

C 10

C1 2

C1 4

C 13

C 11

. . .

L4 L3 L2

F C M10 05 K F-3 00 T03 F C M10 05 K F-3 00 T03 F C M10 05 K F-3 00 T03

2 4 m il
10

4 3

4 3

*L VA R 0 40 2-24 0E 0 R 05P -L F

*LV A R 04 02 2 - 40 E 0R 05 P -LF

Sheet 13 of 40 HDMI, CRT

*LV A R 04 02 -240 E 0R 0 5P -LF

R5 1

L7 *H D MI 2 01 2F 2S F -90 0T 04 s ho rt

*L VA R 0 40 2-24 0E 0 R 05P -L F

C 1 28 17 -119 A 5-L R 46

R5 9

R 55

Schematic Diagrams

IBEXPEAK - M 1/9
RT C V CC

V DD 3

2 0m ils

IBEXPEAK - M (HDA,JTAG,SATA)
C 408 1 5 p_ 5 0 V _ N P O_ 0 4 2 . 2 u_ 1 6 V _ X 5 R _ 0 6 2 1 X6 C M 20 0 S 3 2 7 6 8 12 2 0 _ 3 2. 76 8 K H z 1 C 382 R 299 2 0 K_ 1 % _ 0 4 R 297 1 0 M _ 04 U 20A R T C_ X 1 R T C_ X 2 B 13 D 13 D3 3 B3 3 C3 2 A3 2 C3 4 A3 4 F34 AB9 S E R IRQ S E R IRQ 2 4 ,2 8 LP LP LP LP C_ A D C_ A D C_ A D C_ A D 0 1 2 3 2 4 , 28 2 4 , 28 2 4 , 28 2 4 , 28 3 4

A C

20 mils
3

R T C_ V B A T _ 1

D 16 B A T5 4 C S 3

RT C CL EAR
J O PEN 2 * OP E N _ 1 0 m i l1 M M

R 251

C4 0 5 2 . 2 u_ 1 6 V _ X 5 R _ 0 6 2 R 300 2 0 K_ 1 % _ 0 4 1

C 404 1 5 p_ 5 0 V _ N P O_ 0 4

10 m ils
R T C_ V B A T 1

1 K_ 0 4

Z o= 50O ? 5%
R T C_ R S T # S R T C _R T C # C 14 D 17 A 16 A 14

RT C X 1 RT C X 2

FW H 0 / L AD 0 FW H 1 / L AD 1 FW H 2 / L AD 2 FW H 3 / L AD 3 F W H 4 / L F R A ME #

J _ RT C 1 J_R TC1 1 2 1 2 8 5 2 05 -0 2 7 0 1

RT C RS T # S RT C RS T #

LP C _ F R A M E # 2 4 , 28

LPC

TP M CL EAR
J O PEN 1 * OP E N _ 1 0 m i l1 M M R T CV CC R2 9 3 3 3 0 K_ 0 4

S M_ I N TR U D E R # P C H _ I N T V R ME N

R2 9 4 1M _ 0 4

C4 0 6 2 . 2 u_ 1 6 V _ X 5 R _ 0 6 2

INT R UD E R # INT V R M E N

RTC

L D RQ 0 # L D R Q1 # / G P I O 2 3 S E RIR Q

B.Schematic Diagrams

2 7, 29 H D A _ B I T C L K 3 .3 V S N C1 S H O RT

A 30 HD A _ B C L K D 29 H DA _ S P K R P1 C 30 HD A _ S Y NC SPKR HD A _ RS T # S A TA 1R X N S A T A 1 RX P SATA1 TXN S A TA 1 TX P S A TA 2R X N S A T A 2 RX P SATA2 TXN S A TA 2 TX P S A TA 3R X N S A T A 3 RX P SATA3 TXN S A TA 3 TX P S A TA 0R X N S A T A 0 RX P SATA0 TXN S A TA 0 TX P AK7 AK6 AK1 1 AK9 S A T A R X N0 SATAR XP0 S A T A T X N0 SATATXP0 S A T A R X N0 SATAR XP0 SATATXN 0 SATATXP0 26 26 26 26

BIOS ROM
C 21 7 0 . 1 u _1 0 V _ X 7 R _ 0 4

2 7, 29 H D A _ S Y N C 27 H D A_ SPKR

SATA HDD SATA ODD


Sheet 14 of 40 IBEXPEAK - M 1/9

32Mbit
U1 0 8 V DD S I SO 3 W P# C E# SC K HO L D# VS S 2 1 6 4 SPI_ SO 5 SPI_ SI SPI_ VD D 8

32Mbit
U 11 5 VD D SI SO SPI_ C S0 # SPI_ SC L K SC K 7 S P I _ H OL D # HO L D# VS S SPI_ W P# 3 W P# C E# 2 1 6 4 SPI_ SO SPI_ C S1 # SPI_ SI

2 7, 29 H D A _ R S T #

S P I_ V D D R 159 3 .3 K _ 1 % _ 0 4 S P I_ W P #

27 29

HD A _ S D IN0 HD A _ S D IN1

G 30 F 30 E 32 F 32

HD A _ S D IN0 HD A _ S D IN1

AH AH AH AH

6 5 9 8

S A T A R X N1 SATAR XP1 S A T A T X N1 SATATXP1

S A T A R X N1 SATAR XP1 SATATXN 1 SATATXP1

26 26 26 26

R 152 3 .3 K _ 1 % _ 0 4 S P I _ H OL D # 7

SPI_ SC L K 2 7, 29 H D A _ S D O U T R 298 1 K_ 0 4 H DA _ DO CK _ E N# B 29

HD A _ S D IN3

IHDA

HD A _ S D IN2

AF1 1 AF9 AF7 AF6 AH 3 AH 1 AF3 AF1 AD AD AD AD 9 8 6 5 S A T A R X N2 SATAR XP2 S A T A T X N2 SATATXP2

HD A _ S D O

MX 2 5 L 3 20 5 D M2 I -1 2 G

*M X 2 5 L3 2 0 5 D M 2 I -1 2 G H D A _ D O C K _ E N # / GP I O3 3 HD A _ DO C K _ RS T # / G P IO 1 3

SATA

H 32 J 30

SPI_* = 1.5"~6.5"
28 ME _ W E #

D 17 C

R B7 5 1 V A P C H _ JT A G _ T C K _B U F M3 1 J OP E N 3 *O P E N _ 10 m i l -1 MM P C H _ JT A G _ T MS P C H _ JT A G _ T D I P C H _ JT A G _ T D O P C H _ JT A G _ R S T # K3 K1 J2

S A TA 4R X N S A T A 4 RX P SATA4 TXN S A TA 4 TX P S A TA 5R X N S A T A 5 RX P SATA5 TXN S A TA 5 TX P

J TA G_ T C K J TA G_ T MS J TA G_ T D I

AD 3 AD 1 AB3 AB1 1 .1 VS_ VT T

JTAG

Flash Desc riptor Security O veride

AF1 6 S A T A ICO M P O S A T A I C O MP I AF1 5

S A T A I C OM P

R8 9

37 . 4 _ 1 % _ 0 4

J TA G_ T D O J4 J TA G_ R S T #

SPI_ SC L K SPI_ C S0 # SPI_ C S1 # S P I_ CS 0 # _ R S P I_ CS 1 # _ R

BA2 AV3 AY3

3 .3 V S S P I _ C LK SPI_ C S 0 # T3 SPI_ C S 1 # S ATAL ED # Y9 S P I _ M OS I SAT A0 G P / G PIO 2 1 O DD _ DE T E C T # R1 0 8 SATA_ L ED # R2 7 5 *1 0 K _ 0 4 S A T A _ LE D # 2 9 10 K _ 0 4 O D D _ D E TE C T # 2 6 SATA_ D ET# 1 R2 7 1 10 K _ 0 4 3 .3 VS

3 .3 V

SPI_ SI SPI_ SO R 262 33_04 S P I _ S O_ R

AY1 AV1

SPI

SPI_ M ISO I b e xP e ak -M _ R e v 0 _ 9

SAT A1 G P / G PIO 1 9

V1

R 290 * 2 0K _1 % _ 0 4

R 28 8 * 20 0 _ 0 6

R 2 86 * 20 0 _ 0 6

R 283 * 2 00 _ 0 6 PC PC PC PC H _ J T A G_ T M S H _ J T A G_ T D I H _ J T A G_ T D O H _ J T A G_ R S T # 3 .3 VS R 93 R 2 78 1 0 K _ 04 *1 K _ 0 4 S E R IR Q H DA _ S P K R

ESATA
S A T A T XP 2 S A T A T XN 2 C 17 4 C 17 1 * 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4 * 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4

R 289 * 1 0K _0 4

R 28 5 *1 0 0 _1 % _ 0 4

R 2 84 * 10 0 _ 1 % _ 04

R 282 * 1 00 _ 1 % _ 0 4 3 .3 VS

NO REBOOT STRAP : HDA_ SPKR Hi gh Ena ble

iTPM ENABLE/DISABLE
R 2 61 *1 K _ 0 4 S P I _S I S A T A RX N 2 S A T A RX P 2 C 16 1 C 17 0 * 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4 * 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4 TPM FUN CTION: SPI_SI High E nable

R2 8 1

*4 . 7 K _ 0 4 P C H _ JT A G_ T C K _B U F

? ? ? ? , ESAT A REDR IVER? ? ? ? ? ?

2 3, 25 , 2 8 , 2 9 , 3 1 , 3 2, 3 7 V D D 3 21 R T CV CC 2 , 4 , 6 , 7 , 1 5 , 1 6 , 1 9 , 20 , 2 1 , 3 4 , 3 5 , 3 6 1 . 1V S _ V T T 3 , 4 , 12 , 1 5 , 1 6 , 1 8 , 1 9, 20 , 2 1 , 2 3 , 2 4 , 2 5, 29 , 3 0 , 3 1 , 3 3 , 3 4, 3 5 3 . 3 V 2, 10 , 1 1 , 1 2 , 1 3 , 1 5, 16 , 1 7 , 1 8 , 1 9 , 2 0, 2 1 , 2 3 , 2 4 , 2 5 , 26 , 2 7 , 2 8 , 2 9 , 3 0, 31 , 3 5 , 3 6 3 . 3 V S

IBEXPEAK - M 1/9 B - 15

Schematic Diagrams

IBEXPEAK - M 2/9
IBEXPEAK - M (PCI-E,SMBUS,CLK)
U2 0 B B G3 0 B J3 0 BF 2 9 BH2 9 23 23 23 23 P C I E _ R X N 2 _N P C IE _ RX P 2 _ N P C I E _T X N 2 _N P C I E _T X P 2 _ N 23 23 23 23 E W _C EW _ C E W _C EW _ C AR D A RD AR D A RD AW 3 0 BA3 0 BC3 0 BD3 0 AU3 0 A T3 0 AU3 2 AV3 2 BA3 2 BB3 2 BD3 2 BE3 2 BF 3 3 BH3 3 B G3 2 B J3 2 BA3 4 AW 3 4 BC3 4 BD3 4 A T3 4 AU3 4 AU3 6 AV3 6 B G3 4 B J3 4 B G3 6 B J3 6 PE R N1 PER P1 P E T N1 PETP1 PE R N2 PER P2 P E T N2 PETP2 S MB A L E R T # / GP I O 1 1 S M B C LK S M B D A TA B9 H 14 C 8 P C H _ B T_ E N # S M B _ C LK SM B_ D ATA PCH _ B T _ E N # 2 9 S MB _ C L K 2 S MB _ D A T A 2 18 P CH _ UP E K _ INIT # 1 8 S ML 0 _ C LK 23 S M D _ CP U _ T HE R M S M C _ CP U _ T HE R M U S B _O C #8 9 P C H _ B T _E N # U S B _ OC # 89 L P D _ S P I_ IN T R# S M L 0 _ DAT A S M L 0 _ CL K R N 16 2 . 2 K _4 P 2 R _ 0 4 3 2 4 1 R N 11 2 . 2 K _4 P 2 R _ 0 4 3 2 4 1 R N 13 1 0 K _ 8 P 4 R _ 04 1 8 2 7 3 6 4 5 R N 10 2 . 2 K _4 P 2 R _ 0 4 3 2 4 1 3 .3 V

SM B_ C L K SM B_ D ATA

C1 2 4 C1 2 5

0 . 1 u _ 10 V _ X 7 R _0 4 0 . 1 u _ 10 V _ X 7 R _0 4

P C I E _ T XN 2 _ C P C I E _ T XP 2 _C

S M L 0 A L E R T # / GP I O 6 0 S ML 0 C LK

J14 C 6 G 8

P C H _ U P E K _I N I T # S M L 0 _C L K S M L 0 _D A T A

SMBus

P CIE _ R X N3 _ W L A N P CIE _ R X P 3 _ W L A N P C IE _ T X N3 _ W L A N P C IE _ T X P 3 _ W L A N

C1 3 1 C1 3 0

0 . 1 u _ 10 V _ X 7 R _0 4 0 . 1 u _ 10 V _ X 7 R _0 4

P C I E _ T XN 3 _ C P C I E _ T XP 3 _C

PE R N3 PER P3 P E T N3 PETP3 PE R N4 PER P4 P E T N4 PETP4

S ML 0 D A TA M 14 E1 0 G 12 S M L1 D A T A / GP I O 7 5 L P D _ S P I _ I N TR # S M C _ C P U _ TH E R M S M D _ C P U _ TH E R M

S ML 0 _ D A T A 2 3

B.Schematic Diagrams

S M L 1 A L E R T # / GP I O 7 4 S M L 1 C L K / GP I O 5 8

2 5 P C I E _ R X N 4 _ GL A N 2 5 PC IE_ RXP4 _ G L AN 25 P C I E _ TX N 4 _ GL A N 25 P C I E _ TX P 4 _ G L A N

C1 2 6 C1 2 7

0 . 1 u _ 10 V _ X 7 R _0 4 0 . 1 u _ 10 V _ X 7 R _0 4

P C I E _ T XN 4 _ C P C I E _ T XP 4 _C

S M C_ C P U_ T H E RM S M D_ C P U_ T H E RM

3 ,2 8 3 ,2 8 PEG _ CL KR EQ # R 287 R 112 1 0K _0 4 1 0K _0 4

Sheet 15 of 40 IBEXPEAK - M 2/9

PCI-E x1 Lane Lane Lane Lane Lane Lane Lane Lane


3 .3 V 3 .3 V S R N8 1 0 K_ 8 P4 R_ 0 4 1 8 2 7 3 6 4 5

Usage WLAN NEW CARD 3G GLAN / CARD R EADER X X X X

PE R N5 PER P5 P E T N5 PETP5 PE R N6 PER P6 P E T N6 PETP6 PE R N7 PER P7 P E T N7 PETP7 PE R N8 PER P8 P E T N8 PETP8

PCI-E*

T13

Controller Link

C L_ C L K 1 CL _ D A T A 1 C L _R S T 1 # T11 T9 10K pul l-down to GND

L A N _ C L K R E Q#

1 2 3 4 5 6 7 8

P E G _A _ C L K R Q# / GP I O 4 7

H 1

P E G _ C LK R E Q #

100-M Hz Gen2 diffe rential clock to PCI e Grap hics devic e.

PEG

C L K O U T _ P E G_ A _ N C LK OU T _ P E G _A _P C L K O U T _ D MI _ N C L K O U T _D M I _P

AD 4 3 AD 4 5 AN 4 AN 2 C L K_ EXP_ N C L K_ EXP_ P P C H _ C L K _ D P _N _ R P C H _ C L K _ D P _P _ R R 26 4 R 26 5 * 10 m i l _ sh o rt * 10 m i l _ sh o rt 4 4

AK4 8 AK4 7 P C IE CL K RQ 0 # P C I E C L K R Q1 # P C I E C L K R Q0 # P C I E C L K R Q5 # P E G_ B _ C L K R Q # P C IE CL K RQ 1 # P9

C LK OU T _D P _ N / C LK OU T _ B C L K 1 _ N C L K O U T_ D P _ P / C L K O U T _ B C L K 1 _P CL K O UT _ P C IE 0 N CL K O UT _ P C IE 0 P P C I E C L K R Q0 # / GP I O 7 3

AT1 AT3

CL K _ D P _ N 4 CL K _ D P _ P 4 100-M Hz diff erenti al cloc k from PCH to Proce ssor. Conne ct to P EG_CLK #/PEG_C LK pin s of th e proce sso

A M4 3 A M4 5 U4

From CLK BUFFER

C L K I N _ D MI _ N C L K I N _D M I _P

AW 2 4 B A 24

C L K _ P C IE _ IC H# 2 C L K _ P C IE _ IC H 2

CL K O UT _ P C IE 1 N CL K O UT _ P C IE 1 P P C I E C L K R Q1 # / GP I O 1 8

C L K I N _B C L K _ N C L K I N _ B C LK _P

AP 3 AP 1

C L K _ B U F _ B C LK _N C L K _ B U F _ B C LK _P

2 2

2 3 CL K _ P C IE _ N E W _ C A RD # 23 C L K _ P C I E _ N E W _ C A R D 2 3 N E W C A R D _ C LK R E Q # R 279 0_04 C L K _ S L O T 2 _O E #

A M4 7 A M4 8 N4

C L K I N _ D O T _9 6 N C L K I N _ D OT _ 9 6P

F18 E1 8

C L K _ B U F _ D O T 9 6_ N C L K _ B U F _ D O T 9 6_ P

2 2 C3 9 8 2 2 p _5 0 V _ N P O _0 4

CL K O UT _ P C IE 2 N CL K O UT _ P C IE 2 P P C I E C L K R Q2 # / GP I O 2 0

C L K IN _ S A T A _ N / CK S S C D_ N C L K I N _ S A T A _ P / C K S S C D _P

AH 1 3 AH 1 2

C L K_ SATA# 2 C L K_ SATA 2

2 3 C L K _ P C I E _ MI N I # 2 3 C LK _P C I E _M I N I 2 3 W L A N _ C LK R E Q #

AH4 2 AH4 1 A8

CL K O UT _ P C IE 3 N CL K O UT _ P C IE 3 P P C I E C L K R Q3 # / GP I O 2 5

RE F CL K 1 4 IN

P4 1

C L K _ BU F _ RE F 1 4 2

R 266 1 M _ 04

1 X5 X 8 A 0 2 5 0 0 0F G1 H _2 5 M H z 2

C L K I N _ P C I L O OP B A C K

J42

C L K _ P C I_ F B 1 8 X T A L 2 5 _I N X T A L 2 5 _O U T X C L K _R C OM P R 87 9 0 . 9_ 1 % _ 0 4 1 . 1 V S _V T T

2 5 C L K _ P C I E _ GL A N # 2 5 C L K _ P C I E _ GL A N L A N _ CL K R E Q #

A M5 1 A M5 3 M9

CL K O UT _ P C IE 4 N CL K O UT _ P C IE 4 P P C I E C L K R Q4 # / GP I O 2 6

X TA L2 5 _ I N X T A L 2 5 _ OU T X C L K _ R C O MP

AH 5 1 AH 5 3 A F 38

C3 9 5 9 0.9-O ? % pul lup t o +VccI O ( 1.05V, S0 rai l)

2 2 p _5 0 V _ N P O _0 4

CL K O UT _ P C IE 5 N CL K O UT _ P C IE 5 P P C I E C L K R Q5 # / GP I O 4 4

Clock Flex

A J5 0 A J5 2 P C I E C L K R Q5 # H6

T45 C L K O U T F L E X 0 / GP I O 6 4 P4 3

C L K O U T F L E X 1 / GP I O 6 5

AK5 3 AK5 1 P E G_ B _ C L K R Q# P1 3

CL K O UT _ P E G _ B _ N CL K O UT _ P E G _ B _ P P E G _B _C L K R Q# / G P I O 5 6 I b ex P ea k -M _ R e v 0 _ 9

C L K O U T F L E X 2 / GP I O 6 6

T42

C L K O U T F L E X 3 / GP I O 6 7

N 50

3 .3 V S 2 , 1 0, 1 1 , 1 2 , 1 3 , 1 4 , 1 6, 1 7 , 1 8 , 1 9 , 2 0 , 2 1, 23 , 2 4 , 2 5 , 2 6 , 2 7, 28 , 2 9 , 3 0 , 3 1 , 3 5, 36 1 . 1 V S _ V T T 2 , 4 , 6 , 7 , 1 4 , 1 6 , 19 , 2 0 , 2 1 , 3 4 , 3 5 , 36 3 .3 V 3 , 4 , 12 , 1 4 , 1 6 , 1 8 , 1 9 , 20 , 2 1 , 2 3 , 2 4 , 2 5 , 2 9, 3 0 , 3 1 , 3 3 , 3 4 , 3 5

B - 16 IBEXPEAK - M 2/9

Schematic Diagrams

IBEXPEAK - M 3/9
IBEXPEAK - M (DMI,FDI,GPIO)
U2 0 C 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 R2 5 9 D MI _ R XN 0 D MI _ R XN 1 D MI _ R XN 2 D MI _ R XN 3 D D D D MI _ R MI _ R MI _ R MI _ R XP XP XP XP 0 1 2 3 0 1 2 3 B C2 4 B J2 2 AW 2 0 B J2 0 B D2 4 B G2 2 BA2 0 B G2 0 BE2 2 BF2 1 B D2 0 BE1 8 B D2 2 B H2 1 B C2 0 B D1 8 D M I0 RXN D M I1 RXN D M I2 RXN D M I3 RXN D D D D D D D D M M M M M M M M I0 RXP I1 RXP I2 RXP I3 RXP I 0 TX N I 1 TX N I 2 TX N I 3 TX N F F F F F F F F DI_ R DI_ R DI_ R DI_ R DI_ R DI_ R DI_ R DI_ R _R _R _R _R _R _R _R _R XN XN XN XN XN XN XN XN 0 1 2 3 4 5 6 7 B A 18 BH 1 7 BD 1 6 BJ 1 6 B A 16 B E 14 B A 14 BC 1 2 B B 18 B F 17 BC 1 6 BG 1 6 AW 1 6 BD 1 4 B B 14 BD 1 2 FD FD FD FD FD FD FD FD FD FD FD FD FD FD FD FD I _ T XN I _ T XN I _ T XN I _ T XN I _ T XN I _ T XN I _ T XN I _ T XN I _ T XP I _ T XP I _ T XP I _ T XP I _ T XP I _ T XP I _ T XP I _ T XP 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

DM DM DM DM

I _ T XN I _ T XN I _ T XN I _ T XN

D M I _ T XP 0 D M I _ T XP 1 D M I _ T XP 2 D M I _ T XP 3 4 9 . 9 _ 1 % _0 4 D MI _ C OM P _ R

D M I 0 TX P D M I 1 TX P D M I 2 TX P D M I 3 TX P

F DI F DI F DI F DI F DI F DI F DI F DI

XP0 XP1 XP2 XP3 XP4 XP5 XP6 XP7

F DI_ IN T

BJ 1 4 B F 13 BH 1 3 BJ 1 2 BG 1 4

F DI_ IN T 3 F DI_ F S Y N C0 3 F DI_ F S Y N C1 3 F DI_ L S Y NC 0 3 F DI_ L S Y NC 1 3

B.Schematic Diagrams

DMI

FDI

1 . 1 V S _V TT

B H2 5 BF2 5

F D I_ F SY NC 0 F D I_ F SY NC 1 F DI_ L S Y NC 0 F DI_ L S Y NC 1

D M I _ Z C O MP D M I _ I R C OM P

FOR RESET SWITCH


3 .3 VS R 11 1 1 0 K_ 0 4 S Y S _ RE S E T # T6 S YS_ R ESET# W A KE# J12 P CI E _ W A K E # P CIE _ W A K E # 2 3 ,2 5 S Y S _ P W R OK M6 S YS _ P W RO K C L K R U N # / GP I O3 2 Y 1 P M_ C L K R U N # P M_ C L K R U N # 2 4 3 . 3V P CIE _ W A K E # S U S _ S T A T # / GP I O6 1 P8 S4 _ STATE# S 4_ S T A T E # 2 4 P M_ S L P _ L A N # S W I# S U S C L K / GP I O6 2 F3 S US _ P W R_ A C K E4 P W R_ BT N # A C_ P R E S E N T SL P_ S4 # H 7 S U S C # 2 8 ,3 3 P M_ B A T L O W # SL P_ S3 # P1 2 S US B # SU SB# 2 3 , 2 8, 31 P M_ C L K R U N # R2 6 8 8. 2K _0 4 R2 9 2 8. 2K _0 4 3 . 3V S R2 8 0 R1 0 9 R1 1 4 10 K _ 0 4 *1 0 K _ 0 4 10 K _ 0 4 R1 2 0 R1 2 5 R1 2 8 1K _0 4 *1 0 K _ 0 4 10 K _ 0 4

Sheet 16 of 40 IBEXPEAK - M 3/9

S B _ P W RO K

B1 7

P W R OK

P M _ MP W R O K

K5

M E P W RO K

R2 9 1

1 0 K_ 0 4

A U X P P W R OK _ R

A1 0

EXT-LAN
4 P M_ D R A M _ P W R GD R S MR S T # 1 0 K_ 0 4 S US _ P W R_ A C K D9

L A N_ RS T #

D R A MP W R O K

System Power Management

S L P _ S 5 # / GP I O6 3

28

R SM RST #

C1 6

R2 9 5

R S M R S T#

2 8 SU S_ PW R _ AC K P W R_ B T N #

M1

S US _ P W R_ A C K / G P IO 3 0

28

P W R _ B T N#

P5

P W R B T N#

S LP _M #

K8

1 8 ,2 8 A C _ P RE S E N T

A C_ PR E SE N T

P7

A CP R E S E NT / G P IO 3 1

TP2 3

N 2

A L L _S Y S _ P W R G D

R1 3 9

10 K _ 0 4

P M _ B A T L OW #

A6

B A T L OW # / GP I O 7 2

P MS Y N C H

BJ 1 0

H _ P M_ S Y N C 4 P M_ S LP _L A N #

28

S W I#

S W I#

F1 4

R I# I b ex P e a k -M _R e v 0 _ 9

S LP _L A N #

F6

3 .3 V

3 .3 V 3 .3 V U 8A 7 4 L VC0 8 PW 14 4 , 3 3 , 3 4 1 . 1 V S _ V T T _ P W R GD 3 2 7 7 A L L _S Y S _ P W R G D 3 4 1 .1 VS _ V T T _ EN R 13 7 2K _ 04 12 , 2 8 7 1 . 1 V S _V TT _ E N 4 6 5 7 3 .3 V U 8C 7 4 L V C 08 P W 8 10 R 141 1 0 K_ 0 4 14 U8 D 74 L V C 0 8 P W 11 13 14 R 135 R 140 R 138 * 1 0m i l _ sh o rt * 1 0m i l _ sh o rt * 1 0m i l _ sh o rt P M _ MP W R O K S B_ P W RO K S Y S _ P W R OK

U8 B 7 4L V C 0 8 P W

14

4 , 36

D E L A Y _ P W R GD A L L _ S Y S _ P W R GD

3 5 V G F X _ V OR E _ P G

12

3 3 D D R 1 . 5 V _ P W R GD SU SB#

H _V TT P W R G D

ON
R 13 4 1 K_ 0 4 3 .3 V S 2, 10 , 1 1 , 1 2 , 1 3 , 14 , 1 5 , 1 7 , 1 8 , 1 9, 2 0 , 2 1 , 2 3 , 2 4, 25 , 2 6 , 2 7 , 2 8, 29 , 3 0 , 3 1 , 3 5 , 36 3 .3 V 3, 4, 12 , 1 4 , 1 5 , 1 8, 19 , 2 0 , 2 1 , 2 3 , 24 , 2 5 , 2 9 , 3 0 , 3 1, 3 3 , 3 4 , 3 5 1 . 1 V S _ V T T 2 , 4 , 6 , 7 , 1 4 , 15 , 1 9 , 2 0 , 2 1 , 3 4, 3 5 , 3 6

IBEXPEAK - M 3/9 B - 17

Schematic Diagrams

IBEXPEAK - M 4/9
IBEXPEAK - M (LVDS,DDI)
U20D 12 B LON 12 NB _ENA VDD T 48 T 47 Y48 3. 3V S R96 R97 R83 *1 0K _04 *1 0K _04 2.37K_1% _04 12 P _DDC_CLK 12 P _DDC_DA T A L_CT RL_CLK L_CT RL_DA TA LVD S_IBG A B48 Y45 A B46 V48 A P39 A P41 AT 43 AT 42 A V53 A V51 B B47 B A52 AY48 A V47 B B48 B A50 AY49 A V48 A P48 A P47 AY53 AT 49 AU52 AT 53 R105 C180 *33 p_50V _NPO_04R99 C176 *33 p_50V _NPO_04R91 C172 *33 p_50V _NPO_04 R 1 04 R 98 R 92 *15mil_short 15 0_1% _04 15 0_1% _04 15 0_1% _04 DA C_BLUE _R DA C_GRE EN_R DA C_RED _R A A52 A B53 AD53 V51 V53 Y53 Y51 AD48 A B51 DA C_RE D_R *15mil_short DA C_GRE EN_R *15mil_short DA C_BLUE _R AY51 AT 48 AU50 AT 51 L_B KLTE N L_V DD_EN L_B KLTCT L L_DDC _C LK L_DDC _D ATA L_CT RL_CLK L_CT RL_DA T A LV D_IBG LV D_VB G LV D_VRE F H LV D_VRE F L LV DSA _CLK# LV DSA _CLK SDV O_CTRLCLK S DVO_CTR LD AT A T 51 T 53 S DVO _TV CLK I NN BJ46 SD VO_T V CLKINP BG46 S DV O_STA LL N BJ48 SD VO_S TALLP BG48 BF45 S DV O_I N TN BH45 S DVO_INT P

B.Schematic Diagrams

Digi tal Displ ay Inter face

Sheet 17 of 40 IBEXPEAK - M 4/9

12 LV DS - L0N 12 LV DS - L1N 12 LV DS - L2N 12 LV DS - L0P 12 LV DS - L1P 12 LV DS - L2P

LV DSA _DA TA #0 LV DSA _DA TA #1 LV DSA _DA TA #2 LV DSA _DA TA #3 LV DSA _DA TA 0 LV DSA _DA TA 1 LV DSA _DA TA 2 LV DSA _DA TA 3 LV DSB _CLK# LV DSB _CLK LV DSB _DA TA #0 LV DSB _DA TA #1 LV DSB _DA TA #2 LV DSB _DA TA #3 LV DSB _DA TA 0 LV DSB _DA TA 1 LV DSB _DA TA 2 LV DSB _DA TA 3

DD PB _0 N DDP B_0P DD PB _1 N DDP B_1P DD PB _2 N DDP B_2P DD PB _3 N DDP B_3P DDP C_CTRLCLK DDPC_CTR LD AT A

RN5 2. 2K _4P2R_04 3 2 4 1

3.3VS HD MI _CTR LC LK 13 HD MI _CTR LD AT A 13

Y49 AB 49

BE 44 DDP C_AU XN DDPC _A UX P BD44 40 DDP C_HPD AV DDPC _0 N DD PC_0P DDPC _1 N DD PC_1P DDPC _2 N DD PC_2P DDPC _3 N DD PC_3P DDP D_CTRLCLK DDPD_CTR LD AT A BE 40 BD40 BF41 BH41 BD38 BC38 BB 36 BA 36 U50 U52

PC H_DDPC_H PD HD MI B _D2BN 13 HD MI B _D2BP 1 3 HD MI B _D1BN 13 HD MI B _D1BP 1 3 HD MI B _D0BN 13 HD MI B _D0BP 1 3 HD MI B _CLKB N 13 HD MI B _CLKB P 13

13 13 13

DA C_B LU E D AC_GRE EN D AC_RE D

NEAR PCH

CR T_B LUE CR T_G REE N CR T_R ED CR T_D DC_CLK CR T_D DC_DAT A CR T_H SYNC CR T_V SY NC DA C_IREF CR T_IRTN

5VS Q18 MTN7002ZHS 3 D R339 100K _ 04 PORTC_HP D 13 G

13 DAC_DDC ACLK 13 DAC_DDC ADA TA 13 13 R 88 1K_1% _04 DAC_HS YNC DAC_V SYN C DA C_I R EF _R

BC46 DDP D_AU XN DDPD _A UX P BD46 DDP D_HPD AT38 DDPD _0 N DD PD_0P DDPD _1 N DD PD_1P DDPD _2 N DD PD_2P DDPD _3 N DD PD_3P BJ40 BG40 BJ38 BG38 BF37 BH37 BE 36 BD36

PCH_DDP C_HP D

IbexPeak-M_Rev0_9

Connec t to GND
PCH_DDP C_HP D R342 *0_04 P ORT C_HPD

No Conn ect Ext ernal Gra phics (P CH Integr ated Gra phics Dis able) Extern al Graphi cs (PCH Integrat ed Graphi cs Disab le)
2,10,11, 12,13,14 ,15,16,1 8,19,20, 21,23,24, 25,26,27, 28,29,30 ,31,35,3 6 3.3VS 2, 13,20,21, 26,27,30 ,31,35,3 6 5VS

B - 18 IBEXPEAK - M 4/9

D isp lay Por t D

C RT

D isp lay Por t C

EMI

HDMIB _D2BN_C HDMIB _D2BP _C HDMIB _D1BN_C HDMIB _D1BP _C HDMIB _D0BN_C HDMIB _D0BP _C HDMIB _CLKB N_C HDMIB _CLKB P_C

C132 C133 C118 C119 C120 C121 C122 C123

0.1u_10V_X 7R_04 0.1u_10V_X 7R_04 0.1u_10V_X 7R_04 0.1u_10V_X 7R_04 0.1u_10V_X 7R_04 0.1u_10V_X 7R_04 0.1u_10V_X 7R_04 0.1u_10V_X 7R_04

D isp lay Por t B

SD VO

12 LV DS - LCLK N 12 LV DS - LCLK P

L VDS

BG44 DDPB _AU XN BJ44 DDP B _A UX P DDPB _HPD AU38 BD42 BC42 BJ42 BG42 BB 40 BA 40 AW38 BA 38

Schematic Diagrams

IBEXPEAK - M 5/9
IBEXPEAK - M (PCI,USB,NVRAM)
U2 0E H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M 48 M 45 F53 M 40 M 43 J36 K48 F40 C42 K46 M 51 J52 K51 L34 F42 J40 G46 F44 M 47 H36 J50 G42 H47 G34 3. 3VS 4 RN2 3 3 8.2 K_8P4 R_0 4 2 1 4 RN1 2 3 8.2 K_8P4 R_0 4 2 1 4 RN2 2 3 8.2 K_8P4 R_0 4 2 1 4 RN2 4 3 8.2 K_8P4 R_0 4 2 1 4 RN2 0 3 8.2 K_8P4 R_0 4 2 1 5 6 7 8 5 6 7 8 5 6 7 8 INT_PIR QE# PC I_ IRD Y# I NT _ PIRQ D# PCI_ FRAME# P C I_ P ER R# PCI _LO CK# PCI_ DEVSEL# P C I_ S ER R# PCI _REQ #1 P C I_ TRD Y# I NT _ PIRQ H# PCI _REQ #0 IN T_PI RQA# IN T_PI RQB# IN T_PI RQC # IN T_PI RQD # PCI_ REQ# 0 PCI_ REQ# 1 PCI_ REQ# 3 PCI_ GN T#0 PCI_ GN T#1 DG PU_PWM_SELEC T# PCI_ GN T#3 IN T_PI RQE# IN T_PI RQF# IN T_PI RQG # IN T_PI RQH # G38 H51 B37 A44 F51 A46 B45 M 53 F48 K45 F36 H53 B41 K53 A36 A48 K6 PCI_ SERR# PCI_ PERR# E44 E50 A D0 A D1 A D2 A D3 A D4 A D5 A D6 A D7 A D8 A D9 A D 10 A D 11 A D 12 A D 13 A D 14 A D 15 A D 16 A D 17 A D 18 A D 19 A D 20 A D 21 A D 22 A D 23 A D 24 A D 25 A D 26 A D 27 A D 28 A D 29 A D 30 A D 31 C/BE0# C/BE1# C/BE2# C/BE3# P I RQ A # P I RQ B # P I RQ C# P I RQ D# REQ0# REQ1# / G P I O5 0 REQ2# / G P I O5 2 REQ3# / G P I O5 4 GNT0# GNT1# / GPIO 51 GNT2# / GPIO 53 GNT3# / GPIO 55 P I RQ E # / GPI O2 P I RQ F # / GPI O3 P I RQ G# / GPIO 4 P I RQ H# / GPIO 5 NV_ CE#0 NV_ CE#1 NV_ CE#2 NV_ CE#3 NV_ DQS0 NV_ DQS1 NV_D Q0 / NV_ IO0 NV_D Q1 / NV_ IO1 NV_D Q2 / NV_ IO2 NV_D Q3 / NV_ IO3 NV_D Q4 / NV_ IO4 NV_D Q5 / NV_ IO5 NV_D Q6 / NV_ IO6 NV_D Q7 / NV_ IO7 NV_D Q8 / NV_ IO8 NV_D Q9 / NV_ IO9 NV_ DQ1 0 / NV_I O10 NV_ DQ1 1 / NV_I O11 NV_ DQ1 2 / NV_I O12 NV_ DQ1 3 / NV_I O13 NV_ DQ1 4 / NV_I O14 NV_ DQ1 5 / NV_I O15 NV_ A LE N V_CL E AY 9 BD 1 AP1 5 BD 8 AV9 BG 8 AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD 6 BB7 BC 8 BJ 8 BJ 6 BG 6 BD 3 AY 6

Boot BIOS Strap


PCI_GNT#0 0 0 1 1
R11 6 R11 8

PCI_GNT#1 0 1 0 1
*1 K _ 04 *1 K _ 04

Boot BIOS Location LPC Reserved PCI SPI


PC I_G NT#0 PC I_G NT#1

(NAND)

NVRAM

B.Schematic Diagrams

Understand the RED FONT define


R12 1 *1 K_04 P C I_ GNT#3

NV_R COMP

AU 2 AV7 AY 8 AY 5 AV1 1 BF5

NV_ RCO MP

R 26 3

3 2.4 _1 % _ 04

N V_RB# NV_W R#0 _RE# NV_W R#1 _RE# N V_WE# _CK0 N V_WE# _CK1

Sheet 18 of 40 IBEXPEAK - M 5/9

PCI

BA CKL IG HT CO NTR OL FR OM IG PU/ DG PU

USB

I NT _ PIRQ G# 5 I NT _ PIRQ C# 6 7 INT_PIR QA# 8 PC I_ S TOP# 5 INT_PIR QB# INT_PIR QF# 6 PCI _REQ #3 7 8DG PU_PW M_SELEC T#

P C IR S T# S ER R# P ER R#

PCI_ IR DY# PCI_ DEVSEL# PCI_ FRAME# PCI_ LO CK# PCI_ STOP# PCI_ TR DY# 28 PME# PLT_ RST#

A42 H44 F46 C46 D49 D41 C48 M7 D5 N52 P53 P46 P51 P48

IRD Y# P AR DEVS EL # FR AME# P L OCK#

USBP0N U SBP 0P USBP1N U SBP 1P USBP2N U SBP 2P USBP3N U SBP 3P USBP4N U SBP 4P USBP5N U SBP 5P USBP6N U SBP 6P USBP7N U SBP 7P USBP8N U SBP 8P USBP9N U SBP 9P USBP10N USBP10 P USBP11N USBP11 P USBP12N USBP12 P USBP13N USBP13 P

H 18 J 18 A1 8 C 18 N 20 P2 0 J 20 L 20 F2 0 G 20 A2 0 C 20 M22 N 22 B2 1 D 21 H 22 J 22 E2 2 F2 2 A2 2 C 22 G 24 H 24 L 24 M24 A2 4 C 24

US B_ PN0 US B_ PP 0 US B_ PN1 US B_ PP 1 US B_ PN2 US B_ PP 2 US B_ PN3 US B_ PP 3 US B_ PN4 US B_ PP 4 US B_ PN5 US B_ PP 5

30 30 30 30 23 23 23 23 30 30 24 24

USB PORT0 USB PORT1 WLAN NEW CARD USB PORT2 CCD

? ? ? ?

US B_ PN9 2 4 US B_ PP 9 24

3G BT

US B_ PN11 29 US B_ PP 11 29

USBRBI A S# S TOP# T RD Y# P ME# P L TR S T# CLKOU T_ PCI0 CLKOU T_ PCI1 CLKOU T_ PCI2 CLKOU T_ PCI3 CLKOU T_ PCI4 I bex Peak -M_Re v 0_9 OC 0# / GPI O59 OC 1# / GPI O40 OC 2# / GPI O41 OC 3# / GPI O42 OC 4# / GPI O43 O C5 # / G PIO9 OC 6# / GPI O10 OC 7# / GPI O14 US BR BIAS

B2 5 D 25

USB_ B I AS

R 29 6

2 2.6 _1 % _ 06

PIN PL T_RS T# to Buf fer


1 5 CL K _ PCI _FB 2 8 PCLK_ KB C 2 4 PCLK_ TPM

2 4 PLT_RST# R1 23 R1 19 R3 43 22_ 04 22_ 04 *22_ 04

CL K _ PCI_ FB_R CL K _ PCI_ KBC_R P C LK_TPM_PC H

N 16 J 16 F1 6 L 16 E1 4 G 16 F1 2 T15

USB_ OC# 23 USB_ OC# 45 USB_ OC# 67 USB_ OC# 89 USB_ OC# 101 1 USB_ OC# 121 3 GPIO 14

USB_O C#0 1 30 USB_O C#2 3 23

3. 3V

USB_O C#8 9 15 R 12 4 R 11 0 R 11 3 1 0K_0 4 1 0K_0 4 *0_ 04

AC_ PRESENT 1 6,2 8

3 .3 V S C1 91 *0. 1u _10 V_X 7 R_ 04 5 U6 MC74 VHC1 G0 8DFT1G 4 2 3 R 117 1 00K_ 04 BUF_ P LT _ RST# 4 ,2 3, 25, 28 15 P C H_ UPEK _ IN IT# USB_OC #6 7 USB_OC #1 011 USB_OC #4 5 PCH _UPEK_I NI T # 5 6 7 8 4 3 2 1 RN1 4 10K_ 8P4R _04

3.3 V

PL T_R ST#

2, 10, 11 ,12 ,1 3,1 4, 15, 16 ,1 7,1 9, 20, 21 ,23 ,2 4, 25, 26 ,27 ,2 8,2 9, 30, 31 ,3 5,3 6 3. 3VS 3 ,4, 12 ,1 4,1 5, 16, 19 ,20 ,2 1, 23, 24 ,25 ,2 9,3 0, 31, 33 ,3 4,3 5 3. 3V

IBEXPEAK - M 5/9 B - 19

Schematic Diagrams

IBEXPEAK - M 6/9

IBEXPEAK - M (GPIO,VSS_NCTF,RSVD)
U20F ED P _CA RD _DE T # 0213 3.3V S R 270 S_GPIO CHANGE TO EDP_C ARD_DET# SM I# 1K _1% _04 ED P _CA RD _DE T # 28 S M I# DGP U _HP D_IN T R# SC I# PC H_M UT E # * 10K _04 HOS T _A LE RT #1 3.3V S R 101 10K _04 BIO S_ RE C 3.3V S R 350 R 351 *1 0K_ 04 *1 0K_ 04 BIO S_ RE C AA 2 SA T A 4G P / GP IO16 F 38 Y7 H10 12 S B _B LON SB _B LO N SP I_C S#2 A B 12 V 13 M 11 V 6 AB 7 A B 13 V 3 P 3 SD A T AO UT 0 / GP IO3 9 * 0_04 4 ,9 D RA M R ST _ CT RL DRA M RS T _CT R L SV _S E T _UP 3 C RIT _T E M P _R EP # R126 R 107 1K _04 HOS T _A LE RT #1 T P 10 RN9 10K _8P 4R_04 1 8 2 7 3 6 4 5 A 4 A 49 A 5 A 50 A 52 A 53 B 2 B 4 B 52 B 53 BE 1 B E 53 BF 1 B F 53 B H1 B H2 B H52 B H53 B J1 B J2 B J4 B J49 B J5 B J50 B J52 B J53 D1 D2 D53 E 1 E 53 VS S _NC T F _1 VS S _NC T F _2 VS S _NC T F _3 VS S _NC T F _4 VS S _NC T F _5 VS S _NC T F _6 VS S _NC T F _7 VS S _NC T F _8 VS S _NC T F _9 VS S _NC T F _10 VS S _NC T F _11 VS S _NC T F _12 VS S _NC T F _13 VS S _NC T F _14 VS S _NC T F _15 VS S _NC T F _16 VS S _NC T F _17 VS S _NC T F _18 VS S _NC T F _19 VS S _NC T F _20 VS S _NC T F _21 VS S _NC T F _22 VS S _NC T F _23 VS S _NC T F _24 VS S _NC T F _25 VS S _NC T F _26 VS S _NC T F _27 VS S _NC T F _28 VS S _NC T F _29 VS S _NC T F _30 VS S _NC T F _31 Ib exP eak-M _R ev0_9 T P 11 AJ 24 AK 41 T P 12 T P 13 T P 14 T P 15 T P 16 T P 17 T P 18 AK 42 M 32 N32 M 30 N30 H12 AA 23 AB 45 AB 38 AB 42 AB 41 N C_4 N C_5 T 39 R 267 *0_0 4 CRIT _ T EM P _RE P #_R 1 0K_ 04 PC H_G PIO 57 H3 F 1 PC IEC LK RQ7 #/ G PIO 46 AB 6 AA 4 SA T A 5G P / GP IO49 F 8 GP IO57 T P 8 T P 9 M 18 N18 SD A T AO UT 1 / GP IO4 8 T P 6 T P 7 AV 45 AF 13 PC IEC LK RQ6 #/ G PIO 45 T P 4 T P 5 AY 46 AV 43 T A CH0 / GP IO1 7 C LK OUT _ BC LK 0_N / CLK OU T _P CIE 8N CLK OU T _B CLK 0_P/ C LK OUT _PC IE8 P AM 1 BG 10 T 1 BE 10 BD 10 R257 56 _04 R25 3 D37 J32 T A CH3 / GP IO7 F 10 K 9 LA N_P HY _PW R_ CT RL / G PIO 12 T 7 GP IO15 AM 3 B CLK _CP U_ N 4 B CLK _CP U_ P 4 H_P E CI_R R274 10 K_0 4 R25 4 R25 8 3.3VS K B C_R ST # 28 H _CP UP W RGD 4 56_04 1.1V S_V T T *10K _04 0_04 1.1V S _VT T H _P EC I 4,28 A 20G AT E GP IO8 DGPU HDP (NV CON TROL BYSE LF) R 269 * 0_04 28 27 3.3V S CI# P CH_ M UT E # R 349 C38 T A CH1 / GP IO1 T A CH2 / GP IO6 Y3 BM B US Y# / GP IO0 CLK OU T _P CIE 6N C LK OUT _PC IE6 P AH 45 AH 46

MISC

CLK OU T _P CIE 7N C LK OUT _PC IE7 P

AF 48 AF 47 R272 U2 10 K_0 4 3.3V S G A20 28

B.Schematic Diagrams

B IO S R E CO VE R Y D IS A BL E -- -- N O S TU FF (D E FA U LT )

R 102 * 0_04

3.3V S

3.3V S

GP IO28 ST P_P C I #/ G PIO 34 SA T A CL KR EQ # / GP IO35 SA T A 2G P / GP IO36 SA T A 3G P / GP IO37 SL OA D / GP IO38

CPU

Sheet 19 of 40 IBEXPEAK - M 6/9

E NA B LE - -- -- S TU F F

SC LOC K / GP IO2 2 M E M _LE D/G PIO 24 GP IO27

GPIO

PE CI R CIN# P ROC P WR GD T HR M T R IP #

R 277

*1 0K_ 04

CRB _S V _DE T

C RB / SV DE T EC T N O S TU F F [ DE TE C T]

R 276 1 00K _04 3.3V S R 352

ST P_P C I# GP IO35 *1 K_0 4 DGP U _PR S NT #

H _T HR M T RIP # 4 C onnected to PCH (THRMTRI P#) BA 22 AW 22 BB 22 AY 45 R outing g uideline s availa ble in C alpella Design G uide. N OTE: CRB uses a 54.9 O ? % s eries re sistor a nd 56-O pull-up.

T P 1 T P 2 T P 3

3.3V S

R 95

10K _04

SV _S E T _UP M F G_M ODE R 100 CRB _S V _DE T

3.3V

P C H_M U T E # S P I_CS #2 D RA M R ST _CT R L

3.3V S RN2 1 10K _8P 4R_04 1 8 2 7 3 6 4 5 RN4 10K _8P 4R_04 1 8 2 7 3 6 4 5

NCTF

S CI# S M I# M F G_ M OD E S T P _PC I#

RSVD

T P 19 N C_1 N C_2 N C_3

DG PU _HP D_ IN T R# CR IT _T E M P _RE P #_R DG PU _P RS NT # GP IO35

R 103

*1 0K_ 04

D GP U_P R SN T #

INIT 3_3V # T P 24

P6 C10

LOW: DGPU PRESENT

2,4,6,7,14,15,16 ,2 0,21,34,35,36 1.1V S _VT T 3,4,12,14 ,1 5,16,18,20,21,23,24,25,29 ,3 0,31,33,34,35 3.3V 2 ,1 0,11,12,13,14,15,16,17 ,1 8,20,21,23,24,25,26,27,28 ,2 9,30,31,35,36 3.3V S

B - 20 IBEXPEAK - M 6/9

Schematic Diagrams

IBEXPEAK - M 7/9

IBEXPEAK - M (POWER)
3 .3 V S R 90 *0 _ 0 6 1 .1 V S _ V T T U 2 0G AB 2 4 AB 2 6 AB 2 8 AD 2 6 AD 2 8 AF 2 6 AF 2 8 AF 3 0 AF 3 1 AH 2 6 AH 2 8 AH 3 0 AH 3 1 AJ 3 0 AJ 3 1 VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC O O O O O O O O O O O O O O O RE RE RE RE RE RE RE RE RE RE RE RE RE RE RE [1 ] [2 ] [3 ] [4 ] [5 ] [6 ] [7 ] [8 ] [9 ] [ 1 0] [ 1 1] [ 1 2] [ 1 3] [ 1 4] [ 1 5] V C C A _D A C _ 3 . 3 V S V C CA DA C [1 ] V C CA DA C [2 ] AE5 0 AE5 2 C 400 0 . 0 1 u _ 5 0 V _ X 7R _ 0 4 C 399 0 . 1 u _ 1 0 V _ X 7 R _ 04 C 47 0 2 2 u _6 . 3 V _X 5 R _ 0 8 C1 5 1 1 0u _ 6 . 3 V _ X 5 R _0 6 L12 H C B 1 6 0 8K F -1 2 1 T 25 5 VS U5 4 C 139 0 . 1 u _ 1 0 V _ X 7 R _ 04 C 152 2 2 u _ 6 . 3 V _ X 5 R _ 08 R 80 1 7 .4 K _ 1 % _ 0 4 3 R 81 1 0 K_ 1 % _ 0 4 A DJ SH D N G N D 1 2 OU T IN 5 C 15 6 1 u _ 6. 3V _ X 5 R _ 0 4

POWER
CRT
V S S A _ DA C [1 ] V S S A _ DA C [2 ] AF5 3 AF5 1

C 182 1 0 u _ 6 .3 V _ X 5 R_ 0 6

C1 5 7 1 u _ 6 . 3 V _ X 5R _ 0 4

VCC CORE

S C 1 5 63 I S K -3 . 0 T R T

B.Schematic Diagrams

3 . 3 V S _ V C C A _ LV D V CC A L V D S V SSA_ L VD S A H 38 A H 39 C 1 62 R8 6

3. 3V S

*1 5 m i l _ sh o rt _ 0 6

1 .1 VS_ VT T

1 0 u _ 6. 3 V _X 5 R _ 0 6 VC VC VC VC CT X _ L V D CT X _ L V D CT X _ L V D CT X _ L V D S[1 ] S[2 ] S[3 ] S[4 ] AP4 3 AP4 5 AT4 6 AT4 5 C1 4 6 V C C3 _ 3 [2 ] AN 2 0 AN 2 2 AN 2 3 AN 2 4 AN 2 6 AN 2 8 BJ 2 6 BJ 2 8 AT2 6 AT2 8 AU 2 6 AU 2 8 AV 2 6 AV 2 8 AW 2 6 AW 2 8 BA 2 6 BA 2 8 BB 2 6 BB 2 8 BC 2 6 BC 2 8 BD 2 6 BD 2 8 BE 2 6 BE 2 8 BG 2 6 BG 2 8 BH 2 7 AN 3 0 AN 3 1 1 . 5 V S _ 1. 8V S 3 .3 V S AN 3 5 1 .1 V S _ V T T 1 .1 V S _ VC C A P L L _ F DI AT2 2 BJ 1 8 V C CF DI P L L V C C I O[ 1 ] VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC VC CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI O[ 2 5 ] O[ 2 6 ] O[ 2 7 ] O[ 2 8 ] O[ 2 9 ] O[ 3 0 ] O[ 3 1 ] O[ 3 2 ] O[ 3 3 ] O[ 3 4 ] O[ 3 5 ] O[ 3 6 ] O[ 3 7 ] O[ 3 8 ] O[ 3 9 ] O[ 4 0 ] O[ 4 1 ] O[ 4 2 ] O[ 4 3 ] O[ 4 4 ] O[ 4 5 ] O[ 4 6 ] O[ 4 7 ] O[ 4 8 ] O[ 4 9 ] O[ 5 0 ] O[ 5 1 ] O[ 5 2 ] O[ 5 3 ] V C C3 _ 3 [3 ] AB3 4 AB3 5 0 . 0 1 u_ 5 0 V _ X 7 R _ 0 4 C 14 5 0 . 0 1 u _5 0 V _ X 7 R _ 04 C 14 1 1 0 u _6 . 3 V _X 5 R _ 0 6 1 . 8 V S _ V C C TX _ L V D L11 H C B 1 6 0 8K F -1 2 1 T 25 1 .8 VS

AK 2 4

L29 * B K P 10 0 5 H S 1 2 1 _0 4 BJ 2 4 C 378

V C C I O[ 2 4 ]

LVDS

1 .1 VS_ VC C APL L _ EXP

C 140 1 0 u _ 6 . 3 V _ X 5R _ 0 6

V C CA PL L E X P

Sheet 20 of 40 IBEXPEAK - M 7/9

HVCMOS

1 .1 VS_ VT T

C 38 1 1 0 u _6 . 3 V _X 5 R _ 0 6

C1 6 6 1 u_ 6 . 3 V _ X 5 R _ 04

C 167 1 u _ 6 .3 V _ X 5 R_ 0 4

DMI

PCI E*

NAND / SPI

L28 * H C B 1 0 0 5 K F - 12 1 T 2 0

FDI

C3 7 7 *1 0 u _ 6 . 3 V _ X 5 R _ 0 6

1 .1 V S _ V T T R2 5 5

1 .5 V S

1. 8V S

R 256 R 252

*1 5 m i l _s h o rt _ 0 6 *0 _ 0 4

.
1 0 u _ 6 .3 V _ X 5 R_ 0 6 C 142 1 u _ 6 . 3 V _ X 5R _ 0 4 C1 4 7 1 u _6 . 3 V _X 5 R _ 0 4 1 . 1 V S _V C C D P L L _F D I * 1 5 m il _ s h o rt _ 0 6 1 .5 V S _ 1 .8 V S

V C C3 _ 3 [4 ]

A D 35

3. 3V S

C1 6 5 0 . 1 u _1 0 V _ X 7 R _0 4

1. 5V S _ 1 . 8 V S VC C V RM [2 ] AT2 4

AT1 6 V C C DM I[ 1 ] V C C DM I[ 2 ] A U 16 C 1 34

1. 1V S _ V T T

1u _ 6 . 3 V _ X 5 R _ 0 4 VC VC VC VC VC VC VC VC VC C C C C C C C C C PN PN PN PN PN PN PN PN PN A ND A ND A ND A ND A ND A ND A ND A ND A ND [1 ] [2 ] [3 ] [4 ] [5 ] [6 ] [7 ] [8 ] [9 ] A M 16 AK1 6 AK2 0 AK1 9 AK1 5 AK1 3 A M 12 A M 13 A M 15

V _ N V R A M_ V C C Q R 76 C1 5 8 0 . 1 u _1 0 V _ X 7 R _0 4 R 75 * 0 _0 4

1 .8 V S

3 .3 V S

V C C I O[ 5 4 ] V C C I O[ 5 5 ]

* 1 5 m il _ s h o rt _ 0 6

V C C3 _ 3 [1 ]

V C CV RM [1 ]

3 .3 V S V C C ME 3 _ 3 [ 1 ] V C C ME 3 _ 3 [ 2 ] V C C ME 3 _ 3 [ 3 ] V C C ME 3 _ 3 [ 4 ] AM 8 AM 9 AP1 1 AP9 V C C ME 3 . 3 V R 79 R 82 C 14 4 0 . 1 u _ 10 V _X 7 R _ 0 4 *1 5 m i l_ s h o rt _ 0 6 * 0_04

3 .3 V

AM 2 3

I b e x P e a k -M_ R e v 0 _ 9

3, 4, 12 , 1 4 , 1 5 , 1 6 , 1 8 , 1 9 , 2 1 , 2 3, 24 , 2 5 , 2 9 , 3 0 , 3 1 , 3 3 , 3 4 , 3 5 2 3 ,3 1 ,3 6 2 , 1 3, 17 , 2 1 , 2 6 , 2 7 , 3 0 , 3 1 , 3 5 , 3 6 21 7 ,3 3 2 , 1 0 , 1 1 , 1 2 , 1 3 , 1 4 , 1 5, 16 , 1 7 , 1 8 , 1 9 , 2 1 , 2 3 , 2 4 , 2 5, 26 , 2 7 , 2 8 , 2 9 , 3 0 , 3 1 , 3 5 , 3 6 2, 4, 6, 7, 14 , 1 5 , 1 6 , 1 9 , 2 1 , 3 4 , 3 5 , 3 6

3 .3 V 1 .5 V S 5 VS 1 .5 V S _ 1 .8 V S 1 .8 V S 3 .3 V S 1 .1 V S _ VT T

IBEXPEAK - M 7/9 B - 21

Schematic Diagrams

IBEXPEAK - M 8/9
IBEXPEAK - M (POWER)
L32 *H C B 1 0 0 5K F -12 1 T 20 1 .1 VS _ V T T C 3 91 1 0 u _6 . 3 V _ X 5R _0 6 C 39 2 * 0. 1 u _ 10 V _ X 5 R _ 04 A F 23 1. 1 V S _ V C C A _ C L K U2 0 J

V ol ta ge Ra il V ol tag e V _C PU _I O V 5R EF
1. 1 V S _ V T T

S0 Ic cm ax Cu rr en t (A)

1. 1/1 .0 5 < 1 ( mA ) 5 < 1 ( mA ) 5 3. 3 1. 05 3. 3 1. 05 1. 05 1. 05 1. 05 1. 05 1. 1 1. 05 1. 05 1. 05 1. 05 3. 3 1. 8 3. 3 1. 05 3. 3 3. 3 1. 8/1 .5 1. 05 3. 3 1. 8 < 1 ( mA ) 0.3 57 0.0 52 0.0 69 0.0 68 0.0 69 0.0 40 1.4 32 0.0 58 0.0 61 0.0 37 3.0 62 0.3 20 1.8 49 0.0 85 0.1 56 2 ( mA ) 0.0 31 0.1 63 0.0 06 0.1 96 < 1 ( mA ) < 1 ( mA ) 0.0 59

PO WE R
VC VC VC VC CIO CIO CIO CIO [5 ] [6 ] [7 ] [8 ] V2 4 V2 6 Y2 4 Y2 6 V2 8 U2 8 U2 6 U2 4 P2 8 P2 6 N2 8 N2 6 M2 8 M2 6 L 28 L 26 J 28 J 26 H2 8 H2 6 G2 8 G2 6 F28 F26 E2 8 E2 6 C2 8 C2 6 B2 7 A2 8 A2 6 U2 3 V2 3 F24

52mA

A P 51 A P 53

VC CAC L K[1 ] VC CAC L K[2 ]

V 5R EF _S us V cc 3_ 3 V cc AC lk V cc AD AC V cc AD PL LA
3 .3 V

C 15 3 1 u _6 . 3 V _ X 5R _0 4

32 0mA
1 . 1 V S _ V TT C 1 49 T P _ P C H _V C C D S W 1 u _ 6. 3 V _ X 5 R _ 04 C 17 8

V C C L A N [ 1] V C C L A N [ 2] D CP S U S B Y P

A F 24 Y 20 A D 38

0 . 1 u _1 0 V _ X7 R _0 4 A D 39

VC CM E[1 ] VC CM E[2 ] A D 41 VC CM E[3 ] VC CM E[4 ] VC CM E[5 ] VC CM E[6 ] VC CM E[7 ]

B.Schematic Diagrams

1 . 1 V S _ V TT C 3 79 2 2 u _6 . 3 V _ X 5R _0 8 C 15 4 1 u _ 6. 3 V _ X 5R _ 04

USB

1849mA

A F 43 A F 41 A F 42

C 3 80 2 2 u _6 . 3 V _ X 5R _0 8

C 14 8 1 u _ 6. 3 V _ X 5R _ 04

V 41 V 42 Y 39 Y 41 Y 42

Cl oc k a nd M is ce ll an eo us

Sheet 21 of 40 IBEXPEAK - M 8/9


1 .1 V S_ VT T L 31 H C B 1 00 5 K F -1 2 1T 2 0 1 . 1V S _V C C A _ A _ D P L C 1 83

V 39

VC CM E[8 ] VC CM E[9 ] V C C M E [ 1 0] V C C M E [ 1 1] V C C M E [ 1 2]

V C C S U S 3_ 3 [ 1 ] V C C S U S 3_ 3 [ 2 ] V C C S U S 3_ 3 [ 3 ] V C C S U S 3_ 3 [ 4 ] V C C S U S 3_ 3 [ 5 ] V C C S U S 3_ 3 [ 6 ] V C C S U S 3_ 3 [ 7 ] V C C S U S 3_ 3 [ 8 ] V C C S U S 3_ 3 [ 9 ] V C C S U S 3 _3 [ 1 0 ] V C C S U S 3 _3 [ 1 1 ] V C C S U S 3 _3 [ 1 2 ] V C C S U S 3 _3 [ 1 3 ] V C C S U S 3 _3 [ 1 4 ] V C C S U S 3 _3 [ 1 5 ] V C C S U S 3 _3 [ 1 6 ] V C C S U S 3 _3 [ 1 7 ] V C C S U S 3 _3 [ 1 8 ] V C C S U S 3 _3 [ 1 9 ] V C C S U S 3 _3 [ 2 0 ] V C C S U S 3 _3 [ 2 1 ] V C C S U S 3 _3 [ 2 2 ] V C C S U S 3 _3 [ 2 3 ] V C C S U S 3 _3 [ 2 4 ] V C C S U S 3 _3 [ 2 5 ] V C C S U S 3 _3 [ 2 6 ] V C C S U S 3 _3 [ 2 7 ] V C C S U S 3 _3 [ 2 8 ] V C C I O[ 5 6 ] V 5 REF _ S U S

142.6mA
C 18 7 0 . 1 u_ 1 0 V _ X7 R _ 0 4

V cc AD PL LB V cc ap ll EXP V cc Co re V cc DM I V cc DM I V cc FD IP LL V cc IO V cc LA N V cc ME V cc ME 3_ 3 V cc pN AN D V cc RT C V cc SA TA PLL V cc Su s3 _3

3. 3 V _ V C C P U S B R 10 6 C 18 4 0 . 1 u_ 1 0 V _ X7 R _ 0 4 * 15 m i _ l s ho rt _ 0 6

1 . 1 V S _ V TT 5 V _ P C H _V C C 5 R E F S U S D 11 C R1 2 2 1 0 0_ 1 % _0 4 C 18 8 1 u _6 . 3 V _ X5 R _0 4 V C C5 RE F R B 5 5 1V 3 0 A 3 .3 V 5V

V cc Su sH DA V cc VR M V cc VR M V cc AL VD S V cc TX _L VDS

0 . 1u _ 1 0V _X 7 R _ 0 4 V CCR T CE X T V9

D CP R T C

C3 9 3 + C3 9 4 22 u _ 6. 3 V _ X 5R _ 08 *2 2 0u _ 4 V _V _B L 30 H C B 1 00 5 K F -1 2 1T 2 0 C3 8 6 + C3 9 0 22 u _ 6. 3 V _ X 5R _ 08 *2 2 0u _ 4 V _V _B

C 3 89 R2 6 0 1u _ 6. 3V _ X 5 R _ 0 4 *0 _ 0 4 1 . 1 V S _ V C C A _B _D P L

1 . 5 V S _ 1. 8 V S

D1 0 C R 1 15 C1 8 9

R B 5 51 V 3 0 A 1 00 _ 1 %_ 0 4

3 . 3V S 5V S

68mA 69 mA

A U 24

V 5 RE F

K4 9 J 38 L 38 M3 6 N3 6 P3 6 U3 5 A D1 3 C 18 6 0 . 1 u_ 1 0 V _ X7 R _ 0 4 3 .3 VS C 17 5 0 . 1 u_ 1 0 V _ X7 R _ 0 4

V C C V R M[ 3 ]

PCI /G PI O/ LP C

B B 51 B B 53

V C C 3_ 3 [ 8 ] V C C 3_ 3 [ 9 ] V C C 3 _3 [ 1 0 ] V C C 3 _3 [ 1 1 ] V C C 3 _3 [ 1 2 ] V C C 3 _3 [ 1 3 ]

3 .3 VS 1 u_ 6 . 3 V _ X5 R _ 0 4

V C C A D P L LA [ 1] V C C A D P L LA [ 2]

C 3 85 1u _ 6. 3V _ X 5 R _ 0 4 C1 6 0 1 u _ 6. 3 V _ X 5R _ 04 B D 51 B D 53 A H 23 A J 35 A H 35 A F 34 A H 34 C1 6 3 1 u _ 6. 3 V _ X 5R _ 04 A F 32 V 12 C 1 81 C 1 79 0 . 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0V _X 7 R _ 0 4 V CCS S T V C C A D P L LB [ 1] V C C A D P L LB [ 2] V C C I O [ 2 1] V C C I O [ 2 2] V C C I O [ 2 3] VC CIO [2 ]

C1 3 8

1 u _ 6. 3 V _ X 5R _ 04

VCCIO 3062mA
1 .1 VS _ V T T

V C C 3 _3 [ 1 4 ] VC CIO [3 ] 1. 1 V S _ V C C A P L L VC CIO [4 ] D CP S S T V C CS A T A P L L [1 ] V C CS A T A P L L [2 ] AK3 AK1 C 39 6 * 1u _ 6 . 3V _ X 5 R _ 0 4 C 39 7 *1 0 u _6 . 3 V _ X 5R _ 06 L33 *H C B 1 0 0 5K F -12 1 T 20 1 .1 VS _ V T T

1 .1 V _ INT _ V CC S US

Y 22

D CP S U S V C CIO [9 ]

A H2 2

20 .4mA
3. 3 V C 19 4 0 . 1 u _1 0 V _ X7 R _0 4

P 18 U 19 U 20 U 22

V C C S U S 3 _3 [ 2 9 ] V C C S U S 3 _3 [ 3 0 ]

V CC V RM [4 ]

A T 20 A H1 9 A D2 0 AF2 2 A D1 9 AF2 0 AF1 9 A H2 0 AB1 9 AB2 0 AB2 2 A D2 2 AA3 4 Y3 4 Y3 5 AA3 5 L 30 C 19 5 1 . 1V S _V T T

1. 5V S _ 1 . 8 V S

SATA

V C C S U S 3 _3 [ 3 1 ] V C C S U S 3 _3 [ 3 2 ]

PC I/ GPI O/ LP C

V C C I O[ 1 0 ] V C C I O[ 1 1 ] V C C I O[ 1 2 ] VCC VCC VCC VCC I O[ 1 3 ] I O[ 1 4 ] I O[ 1 5 ] I O[ 1 6 ]

1. 1 V S _ V T T

35 7mA
3. 3 V S C 18 5 0 . 1 u _1 0 V _ X7 R _0 4

V 15 V 16 Y 16

V C C 3 _ 3 [ 5] V C C 3 _ 3 [ 6] V C C 3 _ 3 [ 7]

C 17 3 1 u _6 . 3 V _ X 5R _0 4 14 2, 1 0 , 1 1, 1 2 , 1 3, 14 , 1 5 , 16 , 1 7 , 18 , 1 9 , 20 , 2 3 , 2 4, 2 5 , 2 6, 2 7 , 2 8, 2 9 , 3 0, 31 , 3 5 , 36 20 2, 1 3 , 1 7, 2 0 , 2 6, 2 7 , 3 0, 31 , 3 5 , 36 4 , 9 , 1 0, 1 1 , 2 3, 2 7 , 2 9, 31 , 3 3 , 36 2 4, 2 7 , 3 0, 31 , 3 3 , 34 3 , 4 , 12 , 1 4 , 15 , 1 6 , 18 , 1 9 , 2 0, 2 3 , 2 4, 2 5 , 2 9, 3 0 , 3 1, 33 , 3 4 , 35 2, 4 , 6 , 7 , 1 4, 1 5 , 1 6, 1 9 , 2 0, 34 , 3 5 , 36 1 .5 V * 15 m i _ l s ho rt _ 0 6 *0 _ 04 3 .3 V RT CV CC 3 .3 V S 1 . 5 V S _ 1. 8 V S 5 VS 1 .5 V 5V 3 .3 V 1 . 1 V S _ V TT

<1mA
1 . 1 V S _ V TT C1 5 0 1 u _6 . 3 V _ X5 R _0 4 C 1 43 0 . 1 u _1 0 V _ X 7R _0 4 C 16 8

A T 18 A U 18

V C C I O[ 1 7 ] V C C I O[ 1 8 ] V C C I O[ 1 9 ] V C C I O[ 2 0 ] VCC VCC VCC VCC ME [ 1 3 ] ME [ 1 4 ] ME [ 1 5 ] ME [ 1 6 ]

V _ C P U _ I O[ 1 ] V _ C P U _ I O[ 2 ]

0 . 1 u _1 0 V _ X7 R _0 4

CP U

1. 5 V _ V C C S U S H D A R 12 7 R 12 9

VC CR T C I be x P e a k-M _R e v 0 _9

RT C

RT C V CC C 1 92 0 . 1 u _1 0 V _ X 7R _0 4 C 19 3

2mA

A 12

HDA

V C CS U S HD A

0 . 1 u _1 0 V _ X7 R _0 4

1 u _ 6. 3 V _ X 5R _ 04

B - 22 IBEXPEAK - M 8/9

Schematic Diagrams

IBEXPEAK - M 9/9
IBEXPEAK - M (GND)
U 20I AY 7 B 11 B 15 B 19 B 23 B 31 B 35 B 39 B 43 B 47 B7 BG 1 2 B B 12 B B 16 B B 20 B B 24 B B 30 B B 34 B B 38 B B 42 B B 49 BB5 BC 1 0 BC 1 4 BC 1 8 BC 2 BC 2 2 BC 3 2 BC 3 6 BC 4 0 BC 4 4 BC 5 2 BH 9 BD 4 8 BD 4 9 BD 5 B E 12 B E 16 B E 20 B E 24 B E 30 B E 34 B E 38 B E 42 B E 46 B E 48 B E 50 BE6 BE8 BF3 B F 49 B F 51 BG 1 8 BG 2 4 BG 4 BG 5 0 BH 1 1 BH 1 5 BH 1 9 BH 2 3 BH 3 1 BH 3 5 BH 3 9 BH 4 3 BH 4 7 BH 7 C 12 C 50 D 51 E 12 E 16 E 20 E 24 E 30 E 34 E 38 E 42 E 46 E 48 E6 E8 F 49 F5 G 10 G 14 G 18 G2 G 22 G 32 G 36 G 40 G 44 G 52 A F 39 H 16 H 20 H 30 H 34 H 38 H 42 VS S[ 1 59 ] VS S[ 1 60 ] VS S[ 1 61 ] VS S[ 1 62 ] VS S[ 1 63 ] VS S[ 1 64 ] VS S[ 1 65 ] VS S[ 1 66 ] VS S[ 1 67 ] VS S[ 1 68 ] VS S[ 1 69 ] VS S[ 1 70 ] VS S[ 1 71 ] VS S[ 1 72 ] VS S[ 1 73 ] VS S[ 1 74 ] VS S[ 1 75 ] VS S[ 1 76 ] VS S[ 1 77 ] VS S[ 1 78 ] VS S[ 1 79 ] VS S[ 1 80 ] VS S[ 1 81 ] VS S[ 1 82 ] VS S[ 1 83 ] VS S[ 1 84 ] VS S[ 1 85 ] VS S[ 1 86 ] VS S[ 1 87 ] VS S[ 1 88 ] VS S[ 1 89 ] VS S[ 1 90 ] VS S[ 1 91 ] VS S[ 1 92 ] VS S[ 1 93 ] VS S[ 1 94 ] VS S[ 1 95 ] VS S[ 1 96 ] VS S[ 1 97 ] VS S[ 1 98 ] VS S[ 1 99 ] VS S[ 2 00 ] VS S[ 2 01 ] VS S[ 2 02 ] VS S[ 2 03 ] VS S[ 2 04 ] VS S[ 2 05 ] VS S[ 2 06 ] VS S[ 2 07 ] VS S[ 2 08 ] VS S[ 2 09 ] VS S[ 2 10 ] VS S[ 2 11 ] VS S[ 2 12 ] VS S[ 2 13 ] VS S[ 2 14 ] VS S[ 2 15 ] VS S[ 2 16 ] VS S[ 2 17 ] VS S[ 2 18 ] VS S[ 2 19 ] VS S[ 2 20 ] VS S[ 2 21 ] VS S[ 2 22 ] VS S[ 2 23 ] VS S[ 2 24 ] VS S[ 2 25 ] VS S[ 2 26 ] VS S[ 2 27 ] VS S[ 2 28 ] VS S[ 2 29 ] VS S[ 2 30 ] VS S[ 2 31 ] VS S[ 2 32 ] VS S[ 2 33 ] VS S[ 2 34 ] VS S[ 2 35 ] VS S[ 2 36 ] VS S[ 2 37 ] VS S[ 2 38 ] VS S[ 2 39 ] VS S[ 2 40 ] VS S[ 2 41 ] VS S[ 2 42 ] VS S[ 2 43 ] VS S[ 2 44 ] VS S[ 2 45 ] VS S[ 2 46 ] VS S[ 2 47 ] VS S[ 2 48 ] VS S[ 2 49 ] VS S[ 2 50 ] VS S[ 2 51 ] VS S[ 2 52 ] VS S[ 2 53 ] VS S[ 2 54 ] VS S[ 2 55 ] VS S[ 2 56 ] VS S[ 2 57 ] VS S[ 2 58 ] V SS [ 2 59 ] V SS [ 2 60 ] V SS [ 2 61 ] V SS [ 2 62 ] V SS [ 2 63 ] V SS [ 2 64 ] V SS [ 2 65 ] V SS [ 2 66 ] V SS [ 2 67 ] V SS [ 2 68 ] V SS [ 2 69 ] V SS [ 2 70 ] V SS [ 2 71 ] V SS [ 2 72 ] V SS [ 2 73 ] V SS [ 2 74 ] V SS [ 2 75 ] V SS [ 2 76 ] V SS [ 2 77 ] V SS [ 2 78 ] V SS [ 2 79 ] V SS [ 2 80 ] V SS [ 2 81 ] V SS [ 2 82 ] V SS [ 2 83 ] V SS [ 2 84 ] V SS [ 2 85 ] V SS [ 2 86 ] V SS [ 2 87 ] V SS [ 2 88 ] V SS [ 2 89 ] V SS [ 2 90 ] V SS [ 2 91 ] V SS [ 2 92 ] V SS [ 2 93 ] V SS [ 2 94 ] V SS [ 2 95 ] V SS [ 2 96 ] V SS [ 2 97 ] V SS [ 2 98 ] V SS [ 2 99 ] V SS [ 3 00 ] V SS [ 3 01 ] V SS [ 3 02 ] V SS [ 3 03 ] V SS [ 3 04 ] V SS [ 3 05 ] V SS [ 3 06 ] V SS [ 3 07 ] V SS [ 3 08 ] V SS [ 3 09 ] V SS [ 3 10 ] V SS [ 3 11 ] V SS [ 3 12 ] V SS [ 3 13 ] V SS [ 3 14 ] V SS [ 3 15 ] V SS [ 3 16 ] V SS [ 3 17 ] V SS [ 3 18 ] V SS [ 3 19 ] V SS [ 3 20 ] V SS [ 3 21 ] V SS [ 3 22 ] V SS [ 3 23 ] V SS [ 3 24 ] V SS [ 3 25 ] V SS [ 3 26 ] V SS [ 3 27 ] V SS [ 3 28 ] V SS [ 3 29 ] V SS [ 3 30 ] V SS [ 3 31 ] V SS [ 3 32 ] V SS [ 3 33 ] V SS [ 3 34 ] V SS [ 3 35 ] V SS [ 3 36 ] V SS [ 3 37 ] V SS [ 3 38 ] V SS [ 3 39 ] V SS [ 3 40 ] V SS [ 3 41 ] V SS [ 3 42 ] V SS [ 3 43 ] V SS [ 3 44 ] V SS [ 3 45 ] V SS [ 3 46 ] V SS [ 3 47 ] V SS [ 3 48 ] V SS [ 3 49 ] V SS [ 3 50 ] V SS [ 3 51 ] V SS [ 3 52 ] V SS [ 3 53 ] V SS [ 3 54 ] V SS [ 3 55 ] V SS [ 3 56 ] V SS [ 3 66 ] H 49 H5 J 24 K 11 K 43 K 47 K7 L 14 L 18 L2 L 22 L 32 L 36 L 40 L 52 M 12 M 16 M 20 N 38 M 34 M 38 M 42 M 46 M 49 M5 M8 N 24 P 11 A D 15 P 22 P 30 P 32 P 34 P 42 P 45 P 47 R2 R 52 T12 T41 T46 T49 T5 T8 U 30 U 31 U 32 U 34 P 38 V 11 P 16 V 19 V 20 V 22 V 30 V 31 V 32 V 34 V 35 V 38 V 43 V 45 V 46 V 47 V 49 V5 V7 V8 W2 W 52 Y 11 Y 12 Y 15 Y 19 Y 23 Y 28 Y 30 Y 31 Y 32 Y 38 Y 43 Y 46 P 49 Y 5 Y 6 Y 8 P 24 T43 A D 51 A T8 A D 47 Y 47 A T12 A M6 A T13 A M5 A K45 A K39 A V14

U 20 H AB 1 6 VS S [0 ] AA 1 9 AA 2 0 AA 2 2 A M1 9 AA 2 4 AA 2 6 AA 2 8 AA 3 0 AA 3 1 AA 3 2 AB 1 1 AB 1 5 AB 2 3 AB 3 0 AB 3 1 AB 3 2 AB 3 9 AB 4 3 AB 4 7 AB 5 AB 8 A C2 A C 52 A D 11 A D 12 A D 16 A D 23 A D 30 A D 31 A D 32 A D 34 A U 22 A D 42 A D 46 A D 49 A D7 AE 2 AE 4 AF 1 2 Y 13 A H 49 A U4 AF 3 5 AP 1 3 A N 34 AF 4 5 AF 4 6 AF 4 9 AF 5 AF 8 A G2 A G5 2 A H 11 A H 15 A H 16 A H 24 A H 32 AV 1 8 A H 43 A H 47 A H7 A J 19 AJ2 A J 20 A J 22 A J 23 A J 26 A J 28 A J 32 A J 34 A T5 AJ4 AK 1 2 A M4 1 A N 19 AK 2 6 AK 2 2 AK 2 3 AK 2 8 VS S [1 ] VS S [2 ] VS S [3 ] VS S [4 ] VS S [5 ] VS S [6 ] VS S [7 ] VS S [8 ] VS S [9 ] VS S [1 0 ] VS S [1 1 ] VS S [1 2 ] VS S [1 3 ] VS S [1 4 ] VS S [1 5 ] VS S [1 6 ] VS S [1 7 ] VS S [1 8 ] VS S [1 9 ] VS S [2 0 ] VS S [2 1 ] VS S [2 2 ] VS S [2 3 ] VS S [2 4 ] VS S [2 5 ] VS S [2 6 ] VS S [2 7 ] VS S [2 8 ] VS S [2 9 ] VS S [3 0 ] VS S [3 1 ] VS S [3 2 ] VS S [3 3 ] VS S [3 4 ] VS S [3 5 ] VS S [3 6 ] VS S [3 7 ] VS S [3 8 ] VS S [3 9 ] VS S [4 0 ] VS S [4 1 ] VS S [4 2 ] VS S [4 3 ] VS S [4 4 ] VS S [4 5 ] VS S [4 6 ] VS S [4 7 ] VS S [4 8 ] VS S [4 9 ] VS S [5 0 ] VS S [5 1 ] VS S [5 2 ] VS S [5 3 ] VS S [5 4 ] VS S [5 5 ] VS S [5 6 ] VS S [5 7 ] VS S [5 8 ] VS S [5 9 ] VS S [6 0 ] VS S [6 1 ] VS S [6 2 ] VS S [6 3 ] VS S [6 4 ] VS S [6 5 ] VS S [6 6 ] VS S [6 7 ] VS S [6 8 ] VS S [6 9 ] VS S [7 0 ] VS S [7 1 ] VS S [7 2 ] VS S [7 3 ] VS S [7 4 ] VS S [7 5 ] VS S [7 6 ] VS S [7 7 ] VS S [7 8 ] VS S [7 9 ] I be x Pe ak -M_R e v 0_ 9 VS S[ 8 0] VS S[ 8 1] VS S[ 8 2] VS S[ 8 3] VS S[ 8 4] VS S[ 8 5] VS S[ 8 6] VS S[ 8 7] VS S[ 8 8] VS S[ 8 9] VS S[ 9 0] VS S[ 9 1] VS S[ 9 2] VS S[ 9 3] VS S[ 9 4] VS S[ 9 5] VS S[ 9 6] VS S[ 9 7] VS S[ 9 8] VS S[ 9 9] VS S[ 1 0 0] VS S[ 1 0 1] VS S[ 1 0 2] VS S[ 1 0 3] VS S[ 1 0 4] VS S[ 1 0 5] VS S[ 1 0 6] VS S[ 1 0 7] VS S[ 1 0 8] VS S[ 1 0 9] VS S[ 1 1 0] VS S[ 1 1 1] VS S[ 1 1 2] VS S[ 1 1 3] VS S[ 1 1 4] VS S[ 1 1 5] VS S[ 1 1 6] VS S[ 1 1 7] VS S[ 1 1 8] VS S[ 1 1 9] VS S[ 1 2 0] VS S[ 1 2 1] VS S[ 1 2 2] VS S[ 1 2 3] VS S[ 1 2 4] VS S[ 1 2 5] VS S[ 1 2 6] VS S[ 1 2 7] VS S[ 1 2 8] VS S[ 1 2 9] VS S[ 1 3 0] VS S[ 1 3 1] VS S[ 1 3 2] VS S[ 1 3 3] VS S[ 1 3 4] VS S[ 1 3 5] VS S[ 1 3 6] VS S[ 1 3 7] VS S[ 1 3 8] VS S[ 1 3 9] VS S[ 1 4 0] VS S[ 1 4 1] VS S[ 1 4 2] VS S[ 1 4 3] VS S[ 1 4 4] VS S[ 1 4 5] VS S[ 1 4 6] VS S[ 1 4 7] VS S[ 1 4 8] VS S[ 1 4 9] VS S[ 1 5 0] VS S[ 1 5 1] VS S[ 1 5 2] VS S[ 1 5 3] VS S[ 1 5 4] VS S[ 1 5 5] VS S[ 1 5 6] VS S[ 1 5 7] VS S[ 1 5 8] AK 3 0 AK 3 1 AK 3 2 AK 3 4 AK 3 5 AK 3 8 AK 4 3 AK 4 6 AK 4 9 AK 5 AK 8 AL 2 AL 5 2 AM1 1 BB 4 4 AD 2 4 AM2 0 AM2 2 AM2 4 AM2 6 AM2 8 BA 4 2 AM3 0 AM3 1 AM3 2 AM3 4 AM3 5 AM3 8 AM3 9 AM4 2 AU 2 0 AM4 6 AV 2 2 AM4 9 AM7 AA 5 0 BB 1 0 AN 3 2 AN 5 0 AN 5 2 AP 1 2 AP 4 2 AP 4 6 AP 4 9 AP 5 AP 8 AR 2 AR 5 2 AT1 1 BA 1 2 AH 4 8 AT3 2 AT3 6 AT4 1 AT4 7 AT7 AV 1 2 AV 1 6 AV 2 0 AV 2 4 AV 3 0 AV 3 4 AV 3 8 AV 4 2 AV 4 6 AV 4 9 AV 5 AV 8 AW 14 AW 18 AW 2 BF 9 AW 32 AW 36 AW 40 AW 52 AY 1 1 AY 4 3 AY 4 7

B.Schematic Diagrams

Sheet 22 of 40 IBEXPEAK - M 9/9

Ibe x P ea k -M _R e v 0 _9

IBEXPEAK - M 9/9 B - 23

Schematic Diagrams

New Card, Mini PCIE


3 . 3V C 46 1 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 U2 6 MC 74 V H C 1 G0 8 D F T 1 G R3 2 4 3 *1 0 0 K _0 4 R3 2 5 *1 0 0 K _0 4 C2 1 8 0 . 1u _ 1 0V _X 7 R _ 0 4 C2 3 4 0 . 1u _ 1 0V _X 7 R _ 0 4 C 2 30 0 . 1 u _1 0 V _ X7 R _0 4 3. 3V

NEW CARD(Port 8)
1. 5 V S 3 . 3 V S 3. 3 V U2 4 17 AUX IN P E R S T# A U XO U T 2 3. 3 V I N 3. 3V O U T 1. 5V O U T 12 1. 5 V I N CP P E # C PUS B # 4 , 1 8 , 2 5, 2 8 B U F _P L T _ R S T # 1 8 U S B _ OC #2 3 1 6 , 2 8, 31 3 . 3V SU SB# R3 3 3 1 0 K _ 04 4 5 13 14 16 NC NC NC NC NC W 8 3L 3 5 1Y G C4 4 9 0 . 1 u_ 1 0 V _X 7 R _ 0 4 C4 6 6 0 . 1 u_ 1 0 V _X 7 R _ 0 4 C 4 53 0 . 1 u _1 0 V _ X 7R _0 4 R C LK E N S HD N# GN D GN D 18 20 7 21 6 19 1 SYSR ST # OC # S TB Y # 8 15 3 11

B U F _ P L T_ R S T#

1 4 2

J _N E W 1 NC _ RS T # N C _ 3. 3 V A U X N C _ 3. 3 V NC_ P E R S T # 13 12 14 15 10 9 17 4 11 16 19 18 22 21 25 24 3 2

36mils 48mils 48mils


P C I E _W A K E # 3. 3 V S 1 5 C L K _ P C I E _N E W _ C A R D 1 5 C L K _ P C I E _N E W _ C A R D # R1 6 6 1 0K _ 0 4

PE RS T # +3 . 3 V A U X +3 . 3 V +3 . 3 V +1 . 5 V +1 . 5 V CP P E # CP U S B # W AKE# CL K RE Q # R E F C LK + R E F C LK P E Tp 0 P E Tn 0 PE Rp 0 PE Rn 0 US B _ D+ US B _ DGN D GN D GN D GN D GN D 1 GN D 2

N C _ 1. 5 V N C_ CP P E # N C_ CP US B #

B.Schematic Diagrams

10 9

1 6 , 25 P C I E _ W A K E # 1 5 N E W C A R D _ C L K R E Q#

Sheet 23 of 40 New Card, Mini PCIE

N C _ R C L K E N R 32 6 N C _ S H D N # R 33 7

*1 0 K _0 4 *1 0 K _0 4

3 . 3V

1 .5 VS

3. 3 V S

3 .3 V

1 5 PCIE _ RX P2 _ NEW _ C A RD 1 5 P C I E _ R X N 2_ N E W _ C A R D 1 5 P C I E _T X P 2 _N E W _ C A R D 1 5 P C I E _T X N 2 _ N E W _ C A R D

R E SE RV E D R E SE RV E D

5 6

Port 3

1 8 US B _ P P 3 1 8 US B _ P N 3

6-02-83351-9Q0
EN E P2 231 p in 3, 4,1 5, 22 ha s in ter na ll y pu ll ed hi gh ( 17 0Ko hm )
1 5 S M L 0_ D A TA 1 5 S M L 0_ C LK 8 7 S MB _ D A T A S MB _ C L K 1 30 8 0 1-0 2

1 20 23 26 G ND 1 G ND 2

6-21-G3A60-126 Connect 6-21-G3A60-126-S ? ?

MINI CARD (WLAN,Port 5)


L ayou t Sho w "W L AN (W imax, 802 .11N ) "Not e
J _ MI N I 1 29 2 8 ,2 9 B T _E N # B T _E N R3 4 0 R3 4 1 P C I E _W A K E # *0 _ 04 * 10 m i _ l s h ort 1 3 5 7 11 13 9 15 W AKE# CO E X1 CO E X2 C L K R E Q# RE F CL K RE F CL K + GN D 0 GN D 1 3 . 3V A U X _ 0 1 .5 V _ 0 UIM _ P W R U I M_ D A T A U I M_ C L K U I M_ R E S E T U I M_ V P P G ND 5 2 6 8 10 12 14 16 4 U U U U U I M_ P W R _1 I M_ D A T A _ 1 I M_ C L K _ 1 I M_ R S T _ 1 I M_ V P P _ 1

20 mil 20 mil

3. 3 V W L A N1 .5 V R 3 15 C 4 44 * 0 . 1u _ 1 0V _X 7 R _ 0 4 * 1 5m i l _s h o rt _0 6 1 .5 V

3 .3 V S

R 3 05

1 0 K _ 04

1 5 W L A N _ C L K R E Q# 1 5 CL K_ P CIE _ M INI# 1 5 CL K _ P CIE _ M INI

KEY
21 27 29 2 8 W LA N _ D E T # P C I E _ R XN 3 _W L A N P CIE _ RX P 3 _ W L A N P C I E _ T XN 3 _W L A N P C I E _ TX P 3 _ W L A N 28 28 8 0 D E T# 3 IN1 3 .3 V MI N I _ C L K 1 MI N I _ D A T A 1 MI N I _ R S T # 1 V DD 3 R3 0 6 *1 5 mi l _ sh o rt _ 06 35 23 25 31 33 17 19 37 39 41 43 45 47 49 51 GN D 2 GN D 3 GN D 4 GN D 1 1 PET n 0 PET p 0 P E R n0 P E R p0 R e s e rv ed 0 R e s e rv ed 1 GN D 1 2 3 . 3V A U X _ 3 3 . 3V A U X _ 4 GN D 1 3 R e s e rv ed 2 R e s e rv ed 3 R e s e rv ed 4 R e s e rv ed 5 8 8 91 0 -5 20 4 M-0 1 G ND 6 G ND 7 G ND 8 G ND 9 G ND 1 0 W _ D I S A B LE # PER SET # S MB _ C L K S MB _ D A T A U S B_ DUS B _ D + 3 . 3V A U X _ 1 1 .5 V _ 1 1 .5 V _ 2 3 . 3V A U X _ 2 LE D _ W W A N # L ED_ W L A N # LE D _ W P A N # 18 26 34 40 50 20 22 30 32 36 38 24 28 48 52 42 44 46 B U F _ P LT _ R S T # BT _ DE T # 28 USB _ P N 2 1 8 USB _ P P2 1 8 R 3 17 W L A N1 .5 V 3 .3 V 80 C LK 28 * 1 5m i l _s h o rt _0 6 3. 3 V R 3 16 * 1 0K _ 0 4 3 .3 V S

15 15 15 15

W LA N _ E N 2 8 , 2 9

20 mil 3 .3 V AUX _ 1 40 mil 20 mil

Port 2

4 , 9 , 10 , 1 1 , 21 , 2 7 , 2 9, 3 1 , 3 3, 3 6 1 . 5 V 2 0 , 3 1, 3 6 1 . 5 V S 3 , 4 , 12 , 1 4 , 1 5, 1 6 , 1 8, 1 9 , 2 0, 2 1 , 2 4 , 25 , 2 9 , 30 , 3 1 , 33 , 3 4 , 3 5 3 . 3 V 2, 1 0 , 1 1, 12 , 1 3 , 14 , 1 5 , 16 , 1 7 , 1 8, 1 9 , 2 0, 2 1 , 2 4, 2 5 , 2 6 , 27 , 2 8 , 29 , 3 0 , 31 , 3 5 , 3 6 3 . 3 V S 14 , 2 5 , 28 , 2 9 , 31 , 3 2 , 3 7 V D D 3

B - 24 New Card, Mini PCIE

Schematic Diagrams

CCD, 3G, TPM


MINI CARD 3G(Port 6)
Layo ut S ho w "3.5G(HS DPA)" N o te
J_ 3 G1 1 3 5 7 11 13 9 15 W A KE# C OE X 1 C OE X 2 C R R G G L K R E Q# EF CL KEF CL K+ ND 0 ND 1 3 .3 V A UX _ 0 1 .5 V _ 0 U I M_ P W R U I M_ D A T A U I M_ C L K U I M_ R E S E T U I M_ V P P G ND 5 2 6 8 10 12 14 16 4 R 1 67 D UIM UIM UIM UIM UIM _ PW R _ DAT A _ CL K _ RST _ VPP 3G _ 3. 3 V 3 .3 V

3G POWER
R 17 8 * 0 _0 6 Q 14 A O3 4 15 S D 3 G_ 3. 3 V

3A 120 mils 6 0mi ls


+C 2 48 C 25 1 0 . 1 u _1 0 V _ X7 R _ 0 4 0 . 1 u _1 0 V _X 7 R _ 0 4 2 2 0 u_ 4 V _ V _B 1 0 u_ 6 . 3 V _X 5 R _ 0 6 1u _ 6 . 3V _ X 5 R _ 04

3A 120 mils

C 1 96 C 20 1

C 2 41

R1 7 0 10 0 K _ 04 R 1 68 20 K _ 1 %_ 0 4

C2 4 2 0. 1 u _ 10 V _ X 7R _ 04

KE Y
10 0 K _ 04 21 27 29 28 3 G _D E T# 35 23 25 31 33 17 19 37 39 41 43 45 47 49 51 G ND 2 G ND 3 G ND 4 G N D 11 P E Tn 0 P E Tp 0 P E Rn 0 P E Rp 0 R e se rv e d 0 R e se rv e d 1 G N D 12 3 .3 V A UX _ 3 3 .3 V A UX _ 4 G N D 13 R e se rv e d 2 R e se rv e d 3 R e se rv e d 4 R e se rv e d 5 88 9 1 0-5 2 04 M -01 G ND 6 G ND 7 G ND 8 G ND 9 GN D 1 0 W _ D I S A B LE # PER SET# S MB _ C L K S MB _ D A T A US B _ DUS B _ D + 3 .3 V A UX _ 1 1 .5 V _ 1 1 .5 V _ 2 3 .3 V A UX _ 2 L E D_ W W A N # L E D_ W L A N # L E D_ W P A N # 18 26 34 40 50 20 22 30 32 36 38 24 28 48 52 42 44 46 R1 5 6 3 G_ E N 28 3 2 * 1 5m i l_ s h ort _ 0 6 3 G_ 3. 3 V L19 *W C M2 0 12 F 2 S -1 61 T 0 3-s h o rt 4 1 28 3 G_ P O W E R G

Q1 3 MT N 70 0 2 Z H S 3

B.Schematic Diagrams

F ro m SB G PIO Pin de f au lt HI Po w er Pl a ne : Su sp en d S3: De fi n ed


US B _ P N9 US B _ P P 9 18 18

3 G_ 3 . 3V

C2 2 1 0. 1 u _ 10 V _ X 7R _0 4

C4 2 0 10 u _ 6. 3 V _ X 5R _ 06

6 0mil s
3 G_ 3 . 3 V C 4 21 *0 . 1u _ 1 0V _ X 5 R _ 04 +C 20 6 2 2 0u _ 4 V _V _ B

SIM CONN
R1 3 6 4 . 7K _0 4 J _S I M 1 R 30 7 * 10 m i l_ s ho rt U I M_ C L K U I M_ R S T U I M_ P W R C 4 30 2 2 p _5 0 V _ N P O _0 4

Sheet 24 of 40 CCD, 3G, TPM


R3 0 4 *1 0 m il _ sh o rt C7 C6 C5 C4 1 1 2 2p _ 5 0V _ N P O_ 04 C4 1 0 2 2p _ 5 0V _ N P O_ 04 U I M_ D A T A U I M_ V P P

L OCK ( TO P V IE W)
C 3 C 2 C 1 U I M_ C LK U I M_ R S T U I M_ P W R U I M_ D A TA U I M _V P P U I M _G N D

OPE N
C 1 7 70 6 6 1-1 S I ML O C K

C 4 12 22 p _5 0 V _ N P O _0 4

3 . 3V S * 0. 1 u _ 10 V _ X 7 R _ 0 4 *0 . 1 u _1 0 V _ X 7R _0 4 *0 . 1 u_ 1 0V _ X 7 R _ 0 4

TPM 1.2
[ PVT- 1]
1 4, 2 8 1 4, 2 8 1 4, 2 8 1 4, 2 8 L P C _A D 0 L P C _A D 1 L P C _A D 2 L P C _A D 3 26 23 20 17 21 22 16 27 15 * 0 _0 4 TP M _L P C P D # TP M _B A D D T P M_ P P 28 9 TE S T B I / B A D D 7 XT AL I PP X TA L O NC_ 1 NC_ 2 NC_ 3 TE S T I *S L B 9 6 35 T T GN GN GN GN D_ 1 D_ 2 D_ 3 D_ 4 14 4 11 18 25 XTAL O U1 4 LA D 0 LA D 1 LA D 2 LA D 3 LC LK VDD 1 VDD 2 VDD 3 10 19 24

CCD
5V C2 8 3 L1 * 15 m i l_ s h ort _ 0 6 C2 0. 1 u _ 10 V _ X 7R _0 4 R 8 5 *1 u _6 . 3 V _ X5 R _0 4 G C 3 1 u _6 . 3 V _ X5 R _0 4 R9 1 00 K _ 0 4 C5 1u _ 6. 3V _ X 5R _ 04 C8 0. 1 u _ 10 V _ X 7R _0 4 C9 1u _ 6 . 3V _ X 5 R _ 04 MJ_C CD1 1 Q4 M TP 3 4 0 3N 3 S D 5 V_ CC D

48 m il

C2 8 7

C 26 6

1 8 P C L K _T P M 1 4 ,2 8 18 1 4 ,2 8 16 1 6 S 4 _ S T A TE # L P C _F R A ME # P L T _ RS T # S E RIRQ P M _ CL K RU N# R 19 7

T PM
3 . 3V S VS B 5 C2 6 5

LF R A ME # LR E S E T # S E RIR Q CL K RU N# LP C P D #

C2 9 0

1 0 0K _ 0 4 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 GP I O GP I O 2 D 6 2 13 T P M3 0 04 T P M3 0 05 XTAL I 4 3 C 2 54 * 18 p _5 0 V _ N P O _0 4 1 2 X3 * C M2 0 0 S 32 7 6 81 2 2 0_ 3 2. 7 6 8 K H z C 26 0 * 18 p _ 50 V _ N P O _0 4 28 CC D_ E N CC D_ E N G S R 7 3 3 0 K _0 4 Q 5 M TN 70 0 2 Z H S 3 18 U S B_ PN5 18 US B _ P P 5 2 8 CC D_ DE T # C C D _D E T# J_ C C D 1 1 2 3 4 5 85 2 0 5-0 5 0 01

T P M3 0 01 1 T P M3 0 02 3 T P M3 0 03 1 2 8

F rom H8 d efau lt HI

As se rte d be fore e nte rin g S 3 L PC r es et timing : L PCPD# ina ct iv e t o L RST# in ac tive 3 2~96 us
T P M _L P C P D # R1 9 8 R1 9 0 R1 8 8 R1 8 4 *1 0 K _ 04 *1 0 K _ 04 *1 0 K _ 04 *1 0 K _ 04 P C LK _ T P M R1 8 5 *3 3 _0 4 C 27 8 3 .3 V S * 1 0p _ 50 V _ N P O _ 06

3, 4 , 1 2 , 14 , 1 5 , 16 , 1 8 , 19 , 2 0 , 21 , 2 3 , 25 , 2 9 , 30 , 3 1, 33 , 3 4, 35 3 . 3 V 2, 1 0 , 11 , 1 2 , 13 , 1 4 , 15 , 1 6 , 17 , 1 8 , 19 , 2 0 , 21 , 2 3 , 25 , 2 6 , 27 , 2 8 , 29 , 3 0, 31 , 3 5, 36 3 . 3 V S 2 1 , 27 , 3 0, 31 , 3 3, 34 5 V

H I: ACC ESS LOW : NO RMAL ( Int er nal PD) H I: 4E / 4F H TP M _B AD D LOW : 2E/ 2F H TP M _P P

T P M _P P T P M _B A D D

CCD, 3G, TPM B - 25

Schematic Diagrams

Card Reader, LAN (JMB251)


Sw it ch in g Re gu la to r cl os e to P IN 6

S5 WAKE ON LAN
D V DD V D D3

JMC251

S D _C L K

R 18 7

2 2 _0 4 3 .3 V_ L AN 3 .3 V _ L A N

( >2 0m il )
REG L X

L35 DV DD C 4 36 1 0 u _6 . 3 V _ X 5R _ 06 Pi n#7 C2 9 3

S W F 25 2 0 C F -4 R 7M -M

S D_ D3 SD _ BS

S D_ W P M D I O7

S D_ D0 S D _D 1 S D_ D2

M D I O 12

M DI O Si ng le E nd = 5 0 O hm

Fo r JM C2 51 /2 61 on ly

3 .3 V_ L AN R 1 75 4 .7 K _ 0 4 S D _ CD # U1 3 R 1 76 V C C_ C A RD 1 0 K _ 04 M S _ INS#

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

M DIO 0 M D I O1 M DIO 2 V DD IO M DIO 3 MD I O 4 M D I O5 GN D M D I O6 M DIO 7 V DD IO M DIO 8 MD I O9 M DIO 1 0 MD I O1 1 M D I O1 2

B.Schematic Diagrams

R N2 5 1 0 K _8 P 4 R _0 4 8 1 7 2 6 3 5 4

L A N_ L E D0 L A N_ L E D1 SD _ W P SD _ BS M D I O 13 D VDD 26 26 26 26 L A N _M D I P 0 L A N _M D I N 0 D VDD L A N _M D I P 1 L A N _M D I N 1 3 .3 V _ L A N L A N _M D I P 2 L A N _M D I N 2 D VDD L A N _M D I P 3 L A N _M D I N 3 L A N_ M DIP 2 L A N_ M DIN 2 L A N_ M DIP 3 L A N_ M DIN 3

Sheet 25 of 40 Card Reader, LAN (JMB251)

Card Reader Pull High/Low Resistors


3 .3 VS R 1 86 R 3 12 R 1 74 * 10 K _ 0 4 M D I O 7 * 20 0 K _ 0 4 M D I O 12 * 20 0 K _ 0 4 M D I O 14

26 26 26 26

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

L ED 0 L ED 1 VD D G ND V I P _1 V I N_ 1 A V D D 12 V I P _2 V I N_ 2 G ND A V D D 33 V I P _3 (N C ) V I N _ 3 (N C ) A V D D 12 (N C ) V I P _4 (N C ) V I N _ 4 (N C )

JMC251 JMC261
(LQFP 64)

G ND M D I O1 3 M D I O1 4 S MB _ S D A / C R _ LE D N T EST N V D DIO V DD V C C3 O C R _C D 0 N C R _C D 1 N S MB _ S C L/ L E D 2 C R E QN M PD W AKEN RS T N A V DD X

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

M DIO 1 3 M DIO 1 4 C R1 _ L E DN 3 .3 V_ L AN D VD D V C C _C A R D

S D _ CD # M S _ INS # L A N _L E D 2

L A N _ P CIE _ W A K E # 2 8 D VD D R3 0 8 0 _0 4

R EXT V D DX 3 3 X IN X O UT GN D LX F B1 2 V D DR E G CL KN C L KP A VD DH RXP R XN GN D T XN T XP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

JM C 2 5 1

PC Ie D if fe re nt ia l Pa ir s = 10 0 Oh m
C 2 49 C 2 50 0 . 1 u_ 1 0 V _ X7 R _0 4 0 . 1 u_ 1 0 V _ X7 R _0 4 P C I E _ R X P 4 _ GL A N 1 5 P C I E _R X N 4 _ GL A N 15

L ANX IN LA N X O U T

RE G L X D VDD

R1 9 9 12 K _ 1 % _ 04 DV D D

P C I E _ T XN 4 _G L A N 1 5 P C I E _T X P 4 _ GL A N 15 3. 3V _ L A N C LK _P C I E _ GL A N 1 5 C L K _ P C I E _ GL A N # 1 5

3. 3 V _ L A N C 2 96 0 . 1 u _ 10 V _ X 7 R _ 0 4 Pin# 26

3 . 3 V _ LA N DV D D C 24 4 0 . 1 u _1 0 V _ X 7R _ 04 C 2 94 0 . 1 u _ 10 V _ X 7 R _ 0 4 Pin# 51 C2 7 5 0 . 1 u_ 1 0 V _ X7 R _0 4 Pi n#62 C 2 45 0 . 1 u _ 10 V _ X 7 R _ 0 4 Pin#5 5 C 4 31 1 0 u _6 . 3 V _ X 5 R _ 0 6 Pin# 55 Rese rved Pi n#8 C 44 8 1 0u _ 6 . 3 V _X 5 R _ 0 6 Pin# 8

Fo r JM C2 51 /2 61 on ly
V CC _ CA R D C 4 26 0 . 1 u _ 10 V _ X 7 R _ 0 4 LA N X OU T V CC _ CA R D

3 .3 V_ L AN R1 8 3 X4 C 2 95 0 . 1 u _ 10 V _ X 7 R _ 0 4 Pin# 38 C2 3 5 0 . 1 u_ 1 0 V _ X7 R _0 4 Pi n#27 2 1 1 M_ 0 4 L A N XI N

X 8 A 0 2 50 0 0 F G1 H _2 5 MH z C 2 58 22 p _ 50 V _ N P O_ 0 4

C2 7 1 2 2p _ 5 0 V _N P O _0 4

3 .3 V_ L AN V C C_ C A RD C 4 63 1 0 u _6 . 3 V _ X 5 R _ 0 6 Pin# 59 Rese rved C4 1 9 0 . 1 u_ 1 0 V _ X7 R _0 4 Pi n#59 C 2 72 0 . 1 u _ 10 V _ X 7 R _ 0 4 Pin#2 C 2 82 S D _C L K 0 . 1 u _ 10 V _ X 7 R _ 0 4 Pin# 11 C2 8 1 *1 0 p _5 0 V _ N P O_ 0 6 C4 2 8 0 . 1 u_ 1 0 V _ X7 R _0 4 C4 2 9 4 . 7 u_ 6 . 3 V _ X5 R _0 6 C4 5 6 0 . 1 u_ 1 0 V _ X7 R _0 4 C 2 46 0 . 1 u _ 10 V _ X 7 R _ 0 4 V C C_ CA RD

Place all capac itors clo sed to chip . The subscript in eac h CAP incicat es th e pi n n umber of JM C 251/JMC261 tha t should b e closed to .

Near Cardreader CON N


14 , 2 3 , 2 8, 2 9 , 3 1 , 32 , 3 7 V D D 3 26 D V DD 2 , 1 0 , 1 1, 1 2 , 1 3 , 14 , 1 5 , 1 6, 1 7 , 1 8 , 19 , 2 0 , 2 1, 23 , 2 4 , 2 6, 2 7 , 2 8 , 29 , 3 0 , 3 1, 3 5 , 3 6 3 . 3V S 3 , 4 , 1 2, 1 4 , 1 5 , 16 , 1 8 , 1 9, 20 , 2 1 , 2 3, 2 4 , 2 9 , 30 , 3 1 , 3 3, 3 4 , 3 5 3 . 3V

B - 26 Card Reader, LAN (JMB251)

( >2 0m il )

2A
3 .3 V C 47 2 U 27 *0 . 1 u_ 1 0 V _ X7 R _0 4 4 5 V IN V IN V O UT 1 3 . 3V _ L A N

0 . 1u _ 1 0V _X 7 R _ 0 4 Pi n#7

2A

L37 2 1 H C B 2 0 1 2 K F -5 00 T 4 0

2 8 S 5 _ L A NO N

3 R 34 5

EN

GN D *G 52 4 3 A

R 17 8 0 NC NC

R1 88 NC NC 10 0K

R4 32 NC 0 NC

C5 66 F un ct io n Di sa bl e D3 E NC NC En ab le D 3E (1 ) 0. 1u En ab le D 3E (2 )

*1 0 0 K _ 04

1. For JM C251/JMC261 on ly. 2. MPD co nnect to Main Po wer or RSTN for D3E applicaion, t o AUX po wer ot herwise.

Card Reader Power


V CC_ C A RD 3. 3V _ L A N 3 .3 V_ L AN L A N _L E D 2 C R1 _ L E DN R 1 77 R 1 72 * 4. 7 K _ 0 4 * 4. 7 K _ 0 4

R 3 30 7 5 _ 1% _ 0 4

R3 0 9 R3 1 0 C2 4 7

* 0 _0 4 * 1 00 K _ 0 4 * 0 . 1u _ 1 0V _X 5 R _ 0 4

3 .3 VS

S5 WAKE ON LAN
B U F _ P L T _ R S T # 4 , 18 , 2 3 , 2 8 R 346 0_04 R3 4 7 D 22 1 6 , 2 3 P C I E _W A K E # P C I E _W A K E # A C L A N _ P CIE _ W A K E # L A N _ P CIE _ W A K E # 2 8 * 1 0K _ 0 4 3 .3 V_ L AN 2009 /11/1 7

*S C S 7 5 1 V -4 0

4 IN 1 SOCKET SD/MMC/MS/MS Pro


J _ C A R D -R E V 1 S D_ C D# S D_ D 2 S D_ D 3 S D_ B S P1 P2 P3 P4 P5 P6 P7 P8 P9 P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P1 8 P1 9 P2 0 P2 1 C D_ S D D A T 2_ S D C D / D A T 3_ S D C MD _S D V S S _S D V D D_ S D C LK _S D V S S _S D D A T 0_ S D D A T 1_ S D W P _S D V S S _M S V C C_ M S S C L K _ MS D A T 3_ M S I N S _ MS D A T 2_ M S S D I O/ D A T 0 _M S D A T 1_ M S BS_ M S V S S _M S M D R 0 19 -C 0 -10 4 2

S D _ C LK S D_ D 0 S D_ D 1 S D_ W P

C 4 25 0 . 1 u _ 10 V _ X 7 R _ 0 4

S D _ C LK S D_ D 3 MS _ I N S # S D_ D 2 S D_ D 0 S D_ D 1 S D_ B S

G ND G ND

P2 2 P2 3

Schematic Diagrams

LAN (JMC251), SATA HDD, ODD

GIGA LAN (JMC251)


L2 6 25 25 25 25 25 25 25 25 D V DD L A N _ MD L A N _ MD L A N _ MD L A N _ MD L A N _ MD L A N _ MD L A N _ MD L A N _ MD IP 0 IN0 IP 1 IN1 IP 2 IN2 IP 3 IN3 L A N _ MD I P 0 L A N _ MD I N 0 L A N _ MD I P 1 L A N _ MD I N 1 L A N _ MD I P 2 L A N _ MD I N 2 L A N _ MD I P 3 L A N _ MD I N 3 12 11 9 8 6 5 3 2 10 7 4 1 R2 7 *0 _ 04 TD TD TD TD TD TD TD TD TC TC TC TC 4+ 43+ 32+ 21+ 1T4 T3 T2 T1 MX 4 + MX 4 MX 3 + M X 3MX 2 + MX 2 MX 1 + MX 1 MC MC MC MC T4 T3 T2 T1 13 14 16 17 19 20 22 23 15 18 21 24 L MX 1 + L MX 1 L MX 2 + L MX 2 L MX 3 + L MX 3 L MX 4 + L MX 4 L P2 *S B 0 4 02 T L -04 0 -s ho rt 1 8 D L MX 1 + 2 7 D L MX 1 3 6 D L MX 2 + 4 5 D L MX 2 L P1 *S B 0 4 02 T L -04 0 -s ho rt 4 5 D L MX 3 + 3 6 D L MX 3 2 7 D L MX 4 + 1 8 D L MX 4 J _R J 1 1 2 3 6 4 5 7 8 DA + DA DB + DB DC DC DD DD + + she i ld she i ld GN D 1 GN D 2 G ND

B.Schematic Diagrams

P J S -0 8S L3 B

GS T 5 00 9 L F

4 0 mil
C3 0 0 . 01 u _ 50 V _ X 7R _ 04 C2 7 0 . 01 u _ 50 V _ X 7R _ 04 C2 5 0. 01 u _ 50 V _ X 7R _ 04 C2 3

PN:6-19-41001-239
NM NM NM NM CT _ 1 CT _ 2 CT _ 3 CT _ 4 R2 3 R2 4 R2 5 R3 1 7 5 _ 1% _ 0 4 N M C T _ R 7 5 _ 1% _ 0 4 7 5 _ 1% _ 0 4 7 5 _ 1% _ 0 4 C 3 26 1 0 0 0p _ 2 K V _ X7 R _1 2

0. 0 1 u _5 0 V _ X 7R _0 4

Sheet 26 of 40 LAN (JMC251), SATA HDD, ODD

SATA HDD
J_ H D D 1 S S S S S S S P P P P P P P P P P P P P P P 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S A T A _T X P 0 S A T A _T X N 0 S A T A _R X N 0 S A T A _R X P 0 C 4 27 C 4 24 C 4 23 C 4 22 0 . 01 u _ 50 V _ X 7R _ 04 0 . 01 u _ 50 V _ X 7R _ 04 0 . 01 u _ 50 V _ X 7R _ 04 0 . 01 u _ 50 V _ X 7R _ 04 3 .3 V S S A T A T X P 0 14 S A T A T X N0 1 4 S A T A R XN 0 14 S A T A R XP 0 1 4

SATA ODD
J _ OD D 1 S1 S2 S3 S4 S5 S6 S7 SATA_ TXP1 S A T A _ T X N1 S A T A _ RX N 1 S A T A _ RX P 1 C3 8 8 C3 8 7 C3 8 4 C3 8 3 0 . 0 1 u _5 0 V _ X7 R _0 4 0 . 0 1 u _5 0 V _ X7 R _0 4 0 . 0 1 u _5 0 V _ X7 R _0 4 0 . 0 1 u _5 0 V _ X7 R _0 4 S A T A TX P 1 1 4 S A T A TX N 1 1 4 S A T A RX N1 1 4 S A T A RX P 1 1 4

C 4 18 0 . 0 1 u_ 5 0 V _ X7 R _ 0 4

C 4 17 * 10 u _ 6. 3V _ X 5 R _ 0 6 5 VS P1 P2 P3 P4 P5 P6 C 1 8 55 3 -1 13 0 5 -L P I N GN D 1 ~ 2 = GN D C 21 1 5V S OD D _ D E T E C T# 1 4

C3 6 8 *0 . 1 u _1 0 V _ X 5R _0 4

C3 7 0 0 . 1 u_ 1 0 V _X 7 R _ 0 4

C 3 65 0 . 1 u _1 0 V _ X 7R _0 4

C3 7 5 *0 . 1 u _1 0 V _ X5 R _0 4

C3 7 6 1 u_ 6 . 3 V _X 5 R _ 0 4

C 37 4 1 0 u _6 . 3 V _ X5 R _0 6

+ C 37 2 1 0 0u _ 6 . 3V _B _ A

0 . 1 u _1 0 V _ X 7 R _ 0 4

0 . 1 u _1 0 V _ X 7 R _ 0 4

2 2 u _6 . 3 V _ X 5 R _ 08

HD D_ NC 1 HD D_ NC 2 HD D_ NC 3

2 2 u _6 . 3 V _ X 5 R _ 08

HD D_ NC 0

0 . 1 u _1 0 V _ X 7 R _ 0 4

1 u _ 6. 3 V _ X 5 R _ 0 4

A C E S -9 19 0 7 -02 2 0 A -H 0 1 P I N GN D 1 ~ 2 = GN D

* 10 0 u _6 . 3 V _ B _ A 5 VS 5 VS DV DD 3 .3 V 1 .5 V 3 .3 V S 2 , 13 , 1 7 , 20 , 2 1 , 2 7, 3 0 , 3 1, 3 5 , 3 6 25 3 , 4, 1 2 , 1 4, 1 5 , 1 6 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 2 5, 2 9 , 3 0, 3 1 , 3 3, 34 , 3 5 4 , 9, 1 0 , 1 1, 2 1 , 2 3 , 27 , 2 9 , 31 , 3 3 , 36 2 , 10 , 1 1 , 12 , 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0 , 21 , 2 3 , 24 , 2 5 , 27 , 2 8 , 2 9, 3 0 , 3 1, 3 5 , 3 6

C 4 16

C 4 15

C 4 13

C 4 14

C 2 00

C 19 9

C 28 5 0 . 0 1u _ 5 0V _X 7 R _ 0 4

C 81 0 . 0 1u _ 5 0V _ X 7 R _ 0 4

C 4 39 0. 0 1 u _5 0 V _ X7 R _0 4

LAN (JMC251), SATA HDD, ODD B - 27

Schematic Diagrams

Audio Codec VIA 1812


CODEC (VIA1812 /ALC272) PC BEEP
28 K B C _B E E P 1 14 HD A _ S P K R 2 D1 8 B A T 5 4C S 3 3. 3 V S 3 .3 V S 1 .5 V R 31 9 R 31 3 *1 5 m li _ s ho rt _ 0 6 *0 _0 4 C 29 1 0 . 1 u _1 0 V _ X7 R _ 0 4 3. 3 V S _ A U D C 4 38 C4 6 7 1 0u _ 6 . 3V _ X 5 R _ 0 6 C4 4 2 5 V S_ A UD 10 u _ 6. 3 V _ X 5R _ 06 D1 9 C L2 3 *R B 5 51 V 3 0 A H C B 1 6 0 8K F -12 1 T 25 5V 5V S

P IN2 5, PI N3 8 ?

1? 1 0u F/. 1u F

A C A 3 BEEP

C 2 88 0. 1 u _ 10 V _ X 7R _ 04

1 9

25 38

4 7

DV SS 1 D VSS2

C4 5 8 C2 8 0 MI C 2_ L MI C 2_ R MI C 1_ L MI C 1_ R

2 2 p _5 0 V _ N P O _0 4 * 2 2p _ 5 0V _ N P O_ 0 4 * 2 2p _ 5 0V _ N P O_ 0 4 2 2 _ 04 2 2 _ 04 2 2 _ 04 2 2 _ 04 2 2 _ 04 2 2 p _5 0 V _ N P O _0 4 2 2 p _5 0 V _ N P O _0 4 48 45 46 44 A LC _G P I O0 A LC _G P I O1 A Z _ S DO UT _ R A Z _ B IT CL K _ R A Z _ S D I N 0 _R A Z _ S Y N C_ R A Z _ RS T # _ R E A P D _M OD E 2 3 5 6 8 10 11 47

D VDD D V D D -I O

A V DD1 A V DD 2

B.Schematic Diagrams

C2 6 8 C2 6 9 C2 6 3 C2 5 2

* 0 . 1u _ 1 0V _ X 5 R _ 0 4 * 0 . 1u _ 1 0V _ X 5 R _ 0 4 * 0 . 1u _ 1 0V _ X 5 R _ 0 4 * 0 . 1u _ 1 0V _ X 5 R _ 0 4 A UD G 1 4, 2 9 H D A _ S D O U T 1 4, 2 9 H D A _ B I T C L K 14 H DA_ S D IN0 1 4, 29 H D A _ S Y N C 1 4 , 2 9 H D A _ R S T#

C2 7 4 R3 3 1 R3 2 9 R3 2 3 R3 2 2 R3 1 8 C4 4 5 C4 5 1

Sheet 27 of 40 Audio Codec VIA1812

La yo ut No te :
Ver y cl os e t o Au di o C od ec

BEEP A UD G

R3 1 1 R3 1 4 C4 3 4

1 0K _ 0 4 PC BEEP_ C 5 . 1K _1 % _ 04 1 00 p _ 50 V _ N P O _ 04

C 43 5 30 30 MI C _ S E N S E HP _ S E NS E *0 . 1 u_ 1 0 V _X 7 R _ 0 4 *0 . 1 u_ 1 0 V _X 7 R _ 0 4

1u _ 6. 3V _ X 5 R _ 0 4 M I C _ S E N S E R 1 81 2 0 K _ 1% _ 0 4 H P _S E N S E R 3 34 5 . 1 K _ 1% _ 0 4 C2 6 2 * 10 0 p _5 0 V _ N P O _0 4 C2 8 9 * 10 0 p _5 0 V _ N P O _0 4 C 2 56 C 2 57 4 . 7u _ 6 . 3V _X 5 R _ 0 6 4 . 7u _ 6 . 3V _X 5 R _ 0 6

R314 1. 5V V IA 181 2 10 K 3. 3V V IA 181 2 5. 1K AL C27 2 1K


30 30 M I C 1 -L MI C 1-R M I C 1 -L M I C 1 -R

C 25 5 C 28 6 I N T _ MI C R 17 9

1 K _ 04

I N T _ MI C _R

M I C 1 -L M I C 1 -R

AVSS1 A VSS2

R 18 2 R 18 0

7 5 _1 % _ 04 7 5 _1 % _ 04

M I C 1 _ L_ C M IC1 _ R_ C

C 2 61 C 2 53

26 42

C4 4 1 6 80 p _ 50 V _ X 7R _ 04

C 44 0 6 8 0p _ 5 0V _X 7 R _ 0 4

L ay ou t N ot e:
V ery c lo se to A ud io Co de c

A UD G

A UD G A UDG 5 V S _ RE A R

L ay ou t N ot e:
C ode c pi n 1 ~ p in 11 a nd p in 44 ~ pi n 48 a re Di gi tal s ig na ls. T he ot he rs ar e An alo g si gn als .

PIN 13 ,PIN34 JD_SENSE

F R O N T -L F R O N T -R

R 3 35

R 3 38

Thermal Pad

3 . 3V S A UD G 5 VS R3 3 2 R1 9 6 R1 8 9 R3 2 7 10 0 K _ 04 *1 00 K _ 0 4 *1 00 K _ 0 4 10 0 K _ 04

SPK_ EN GA I N 0 GA I N 1

19 2 3 1 11 13 20 21

LO U T -

S P K OU T L -

L 20

SD # G AIN0 G AIN1

R OU T +

18 14 10 12

S P K O UT R + 3 0 S P K O U T R - 30 A MP _ B Y P A S S C 2 59 4 . 7 u _ 6. 3 V _ X 5R _ 06 AU DG

R3 2 8

A UD G C 4 54 *0 . 1u _ 1 0V _X 5 R _ 0 4

Low mute!
19 P C H _ M U T E # E A P D _M OD E R 3 36 0 _0 4 2 8 K B C _ MU TE # C D2 1 A * S CS 3 5 5 V E A P D _ MO D E _ R

10 0 K _ 04

? 6 db
SPK_ EN Ga in S ett ings GA IN0 GAI N1 A V(in v) 0 0 6 dB 0 1 1 0 dB 1 1 0 1 1 5.6 dB 2 1.6 dB IN PUT IMPE DANC E 90 k 70 k 45 k 25 k A UDG

RO UT G ND G ND G ND BY PASS G ND E X P OS E D P A D NC N 7 01 0

1 4 2 U 25 M C 7 4V H C 1 G 08 D F T1 G 3

6-02-07010-AL0
1 .5 V 3 .3 V 3 .3 V S 5V 5 VS

4 , 9 , 10 , 1 1 , 21 , 2 3 , 2 9, 3 1 , 3 3, 3 6 3 , 4 , 12 , 1 4 , 15 , 1 6 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 9 , 3 0 , 31 , 3 3 , 34 , 3 5 2 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 15 , 1 6 , 17 , 1 8 , 19 , 2 0 , 21 , 2 3 , 2 4, 2 5 , 2 6, 2 8 , 2 9, 3 0 , 3 1, 3 5 , 3 6 2 1 , 24 , 3 0 , 31 , 3 3 , 34 2 , 1 3, 1 7 , 2 0, 2 1 , 2 6, 30 , 3 1 , 35 , 3 6

B - 28 Audio Codec VIA 1812

. .

L 21

H C B 1 6 0 8K F -12 1 T 25 C4 6 5 1 0u _ 6 . 3V _ X 5 R _ 0 6 C 46 4 0 . 1 u_ 1 0 V _X 7 R _ 0 4 C2 7 3 0 . 1 u_ 1 0 V _X 7 R _ 0 4

AU DG 0 . 1 u _1 0 V _ X 7R _0 4 C4 3 3 *0 . 1 u_ 1 0V _X 5 R _ 0 4 L3 6 C 4 69 C 4 68 C 2 67 C 4 32 C 4 43 * 1 5m i _ l s h ort _0 6 0 . 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0V _X 7 R _ 0 4 C 29 2 * 1u _ 6 . 3V _X 5 R _ 0 4 A U DG C 4 47 U2 3 A L C_ V RE F C 4 52 1 0 u_ 6 . 3 V _X 5 R _ 0 6 *0 . 1 u_ 1 0 V _ X7 R _ 0 4

FOR EMI
A U DG V RE F 27 M I C 1 -V R E F O 3 C A MI C 1 -V R E F O -R M I C 1 -R A U DG

G P I O0 / D MI C - D A T A 1 / 2 G P I O1 / D MI C - D A T A 3 / 4 S D A T A -OU T B I T -C LK S D A T A -I N S Y NC R ESET# EAP D S P D I F O1 S P D I F O2 D MI C -C L K 1 / 2 D MI C -C L K 3 / 4 N C P C B E E P -I N S e n s e A ( JD 1) S e n s e B ( JD 2) L I N E 2-L L I N E 2-R M I C 2 -L M I C 2 -R L I N E 1-V R E F O M I C 2 -V R E F O L I N E 2-V R E F O

MI C 1 -V R E F O MO N O -OU T

28 37

R3 2 1

4 . 7 K _0 4

DIGITAL

D2 0 B A T 5 4A S 3 2 MI C 1 -V R E F O -L

R 32 0

4 . 7 K _0 4

CP V E E C BN CB P

31 30 29

C 45 9 C 45 7

2 . 2 u _ 16 V _ X 5R _0 6 2 . 2 u _ 16 V _ X 5R _0 6

La yo ut N ote :
Ne ar MI C con ne ct
A UDG

P CB E E P _ R JD 1 JD 2

43 12 13 34 14 15

LO U T 1 -L L OU T 1 -R LO U T 2 -L L OU T 2 -R

35 36 39 41 33 32 23 24

F R ON T-L F R ON T-R

ANALOG

H P OU T -L H P O U T -R LI N E 1 -L L I N E 1 -R JD R E F

H E A D P H ON E -L 30 H E A D P H ON E -R 3 0

MI C 2 _L MI C 2 _R

16 17 18 19 20 21 22

NEAR CODEC
40 J DR E F R1 9 1 5 . 1K _ 1 % _ 04 C2 7 9 * 1 00 p _5 0 V _ N P O _ 04

MI C 2- V R E F O

MI C 2 -V R E F O MI C 1 _L MI C 1 _R

4 . 7u _ 6 . 3V _X 5 R _ 0 6 4 . 7u _ 6 . 3V _X 5 R _ 0 6

I N T _ MI C V T 18 1 2 A UD G C1 2 9 3 30 p _ 50 V _ X 7R _ 04 1 2 8 8 2 66 -0 2 00 1 P C B F o o t pri n t = 88 2 6 6-2 L

R311 VIA1812 5.1K_1%_04 ALC272 20K_1%_04


L3 4 H C B 10 0 5 K F -12 1 T 20 5 VS

AMP (N7010)
10/16 change footprinter
U 22 0_04 AUD G 0_04 AUD G C4 6 0 C2 6 4 C4 6 2 C2 7 0 1 u _6 . 3 V _ X5 R _0 4 1 u _6 . 3 V _ X5 R _0 4 1 u _6 . 3 V _ X5 R _0 4 1 u _6 . 3 V _ X5 R _0 4 LI N LI N + RIN RIN + 5 9 17 7 L INL IN+ R INR IN+ P V DD P V DD V DD L OU T + 6 15 16 4 S P K OU T L + L 22 F C M 1 00 5 K F -1 2 1T 0 3 F C M 1 00 5 K F -1 2 1T 0 3 A UD G C4 5 5 0 . 1 u_ 1 0 V _X 7 R _ 0 4 C 4 46 * 1 u_ 6 . 3 V _X 5 R _ 0 4 C4 3 7 10 u _ 6. 3V _ X 5 R _ 06

C 45 0 *1 0 u _6 . 3 V _ X 5R _0 6 J_S PK1 2 1

S P K OU T L + _R S P K OU T L -_ R

C2 7 7 L24 *1 0 m li _ sh o rt 18 0 p _5 0 V _ N P O _0 4

C 2 84 18 0 p _5 0 V _ N P O _0 4

FOR E MI

L ay ou t No te :
V er y clo se t o A ud io C ode c

M I C 1 -L

J_ INTM IC1 2 R7 8 2 . 2 1K _ 1 % _0 4 J _ I N T MI C 1 1

J _S P K L1 1 2 8 5 2 04 -0 2 00 1 P C B F oo t p ri nt = 8 5 2 04 -0 2 R

Schematic Diagrams

KBC-ITE IT8502E
V D D3 R3 4 8 C 2 16 0 . 1 u _1 0 V _ X 7R _0 4 *1 5 m li _ sh o rt _ 06 C2 4 3 1 0u _ 6. 3V _ X 5 R _ 0 6 C 24 0 C 2 36 C2 0 3 C 2 28 0 . 1 u_ 1 0 V _X 7 R _ 0 4 0 . 1 u _1 0 V _ X7 R _0 4 0. 1 u _ 10 V _ X 7 R _ 04 0 . 1 u _ 10 V _ X 7R _0 4 C 2 37 L 18 H C B 1 00 5 K F -1 21 T 2 0 1 00 K _ 0 4 0. 1 u _ 10 V _ X 7R _ 04 E C _V C C 26 50 92 11 4 121 12 7 K B C _A G N D K B C_ W R E S E T # C2 2 4 J_ K B 1 8 5 20 1 -2 40 5 1 K S I 0/ S TB # K S I1 /A F D# K S I 2 / I N I T# K S I3 /S L I N# K S I4 K S I5 K S I6 K S I7 58 59 60 61 62 63 64 65 36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55 K B -S I 0 K B -S I 1 K B -S I 2 K B -S I 3 K B -S I 4 K B -S I 5 K B -S I 6 K B -S I 7 K B -S O0 K B -S O1 K B -S O2 K B -S O3 K B -S O4 K B -S O5 K B -S O6 K B -S O7 K B -S O8 K B -S O9 K B -S O1 0 K B -S O1 1 K B -S O1 2 K B -S O1 3 K B -S O1 4 K B -S O1 5 4 5 6 8 11 12 14 15 1 2 3 7 9 10 13 16 17 18 19 20 21 22 23 24 3 74 1 u_ 6 . 3 V _ X5 R _ 0 4 *0 . 1 u_ 1 0 V _ X5 R _ 0 4 *0 . 1 u_ 1 0 V _X 5 R _ 0 4 R1 5 4 C2 2 9 K B C _A V D D L17 H C B 1 0 05 K F -1 2 1 T2 0

U1 2 1 4, 2 4 L P C _A D 0 1 4, 2 4 L P C _A D 1 1 4, 2 4 L P C _A D 2 1 4, 2 4 L P C _A D 3 18 P CL K _ K B C 1 4, 24 L P C _ F R A ME # 1 4, 2 4 S E RIR Q 4 , 1 8 , 23 , 2 5 B U F _ P L T _R S T # 10 9 8 7 13 6 5 22 14 126 4 16 20 23 15

11

VS TBY VST BY VS TBY VST BY VST BY VST BY

P C L K _K B C

LA D 0 LA D 1 LA D 2 LA D 3 LP C C L K LF R A ME # SE RIR Q LP C R S T # / W U I 4/ G P D 2 ( P U )

AVC C

V CC

VBAT

19 GA 2 0 37 A C_ IN # 29 LE D _ A C I N # 3 TH E R M _A LE R T # 30 A P _K E Y # 3 0 W E B _E MA I L #

30

C P U _F A N S 5 _ L A NO N

25 S 5 _ LA N ON 2 3 , 29 W L A N _E N 24 3 G_ P O W E R 27 K B C _ MU T E #

37

B A T _ DE T

3 TH E R M _V OL T 2 5 LA N _ P C I E _ W A K E # 24 3 G_ D E T# 24 CCD _ DE T #

37 37

S M C_ B A T S M D_ B A T

3 , 15 S M C _ C P U _ TH E R M 3 , 15 S M D _ C P U _ TH E R M

27

K B C_ B E E P

LOW ACTIVE

23 23 23 18 30 30 37

80 C L K 3I N 1 8 0 DE T # PM E# T P_ CL K T P _ DA T A V C H G_ S E L

31 PW R_ S W # 1 2, 3 0 L ID_ S W # 3 0 W E B _W W W #

AVSS

VS S VSS VS S VSS VSS VSS VSS

2 3, 2 9 12

B T _E N B K L_ E N

1 12 27 49 91 11 3 122

75

0 _0 4 FO R I T8 51 2CX /E X 0 .1 U_ 04 FO R IT E85 12 -J (I TE8 50 2- J E C Co st Do wn


12 B RIG HT NE S S R1 4 7 * 10 m i _ l s ho rt

3 .3 V S

LPC

K/B MATRIX

K B C _ W R E S E T#

W RS T # GA 2 0 / GP B 5 K B R S T # / GP B 6( P U ) P W U R E Q# / G P C 7 ( P U ) L8 0 L LA T / G P E 7 ( P U ) E C S C I # / GP D 3( P U ) E C S M I # / GP D 4( P U )

76 77 78 79 80 81

DAC
DA C DA C DA C DA C DA C DA C 0/ G 1/ G 2/ G 3/ G 4/ G 5/ G PJ 0 PJ 1 PJ 2 PJ 3 PJ 4 PJ 5

IT8502E
FLASH

K S O0 / P D 0 K S O1 / P D 1 K S O2 / P D 2 K S O3 / P D 3 K S O4 / P D 4 K S O5 / P D 5 K S O6 / P D 6 K S O7 / P D 7 K S O8 / A C K # K S O9 / B U S Y K S O1 0 / P E K S O1 1/ E R R # K S O 12 / S L C T K S O 13 K S O 14 K S O 15

66 67 68 69 L A N _ C A B L E _ D E TE C T 7 0 3 G _D E T # 71 C C D _D E T # 72 M OD E L_ I D 73 S M C_ B A T S M D_ B A T

B A T_ D E T B A T_ V O LT C U R _S E N S E _ R

ADC
ADC ADC ADC ADC ADC ADC ADC ADC 0/ G 1/ G 2/ G 3/ G 4/ G 5/ G 6/ G 7/ G P I0 P I1 P I2 P I3 P I4 P I5 P I6 P I7

F L F R A M E #/ G P G2 F L A D0 /S CE# F L A D1 /S I F LA D 2 / S O F L A D 3/ G P G6 F LC LK / S C K ( P D )F L R S T # / W U I 7 / T M/ G P G0

100 101 102 103 104 105 106 56 57 93 94 95 96 97 98 99 107 82 83 84 35 17 47 48 120 124 119 123 19 112

KB C_ S P I_ CE # KB C_ S P I_ S I KB C_ S P I_ S O KB C_ S P I_ S CL K CC D_ E N 24

110 111 115 116 S M C _ C P U _ TH E R M 1 1 7 S M D _ C P U _ TH E R M 1 1 8 L C D_ B RIG HT NE S S K B C_ B E E P

SMBUS
S MC S MD S MC S MD S MC S MD LK 0 / G A T0 / G LK 1 / G A T1 / G LK 2 / G A T2 / G PB3 PB4 P C1 P C2 PF6 ( PU ) PF7 ( PU )

GPIO
( P D )K S O1 6/ G P C 3 ( P D )K S O1 7/ G P C 5 ( ( ( ( ( ( ( PD PD PD PD PD PD PD )I D )I D )I D )I D )I D )I D )I D 0/ G 1/ G 2/ G 3/ G 4/ G 5/ G 6/ G P H0 P H1 P H2 P H3 P H4 P H5 P H6

2 9 L E D _ S C R OL L # 29 L E D _ N U M# 29 L E D_ C A P # 2 9 L E D _B A T_ C H G# 2 9 LE D _ B A T _F U L L# 29 L E D_ PW R# 8 0 CL K 3 IN 1 8 0 DE T #

24 25 28 29 30 31 32 34 85 86 87 88 89 90 125 18 21 33

PWM
PW PW PW PW PW PW PW PW M0 / G M1 / G M2 / G M3 / G M4 / G M5 / G M6 / G M7 / G P A 0( P A 1( P A 2( P A 3( P A 4( P A 5( P A 6( P A 7( PU PU PU PU PU PU PU PU ) ) ) ) ) ) ) )

( P D )I D 7/ G P G1

EXT GPIO
( P D )E GA D / GP E 1 ( P D )E G C S # / GP E 2 ( P D )E G C L K / GP E 3

PS/2
P S 2 C L K 0 / GP F 0 ( P S 2 D A T 0 / GP F 1 ( P S 2 C L K 1 / GP F 2 ( P S 2 D A T 1 / GP F 3 ( P S 2 C L K 2 / GP F 4 ( P S 2 D A T 2 / GP F 5 ( PU PU PU PU PU PU ) ) ) ) ) )

WAKE UP
( P D )W U I 5 / GP E 5 ( P D )L P C P D #/ W U I 6 / GP E 6

PWM/COUNTER
( P D )T A C H 0/ G P D 6 ( P D )T A C H 1/ G P D 7 ( P D )TM R I 0 / W U I 2/ G P C 4 ( P D )TM R I 1 / W U I 3/ G P C 6 ( P D )C R X/ G P C 0 ( P D )C T X / GP B 2

MC H _ TS A TN _E C

WAKE UP
P W R S W / GP E 4 ( P U ) RI1 # /W UI0 /G P D0 ( P U ) RI2 # /W UI1 /G P D1 ( P U )

CIR

GP INTERRUPT
GI N T/ G P D 5 ( P U )

LPC/WAKE UP
( P D )L8 0 H L A T / GP E 0

108 109

UART
RX D/G P B 0 ( P U ) TX D / GP B 1 ( P U ) I T 85 0 2 E -J

( P D )R I N G# / P W R F A I L #/ LP C R S T # / GP B 7

CLOCK
C K 32 K E C K 32 K

2 128

CK 3 2 K E CK 3 2 K R 16 5 * 10 M_ 0 4 X2 C M2 0 0S 3 2 7 68 1 2 20 _ 3 2. 7 6 8 K H z 1 4 2 3

R1 6 4 C2 3 3

*0 _ 0 4 E C _V S S 0 . 1 u _1 0 V _ X 7R _0 4 C2 3 8 1 2p _ 5 0V _N P O_ 0 4

W/ 0 CI R)

N C3

S HO RT

L C D_ B RIG HT NE S S

K B C _ A GN D

C2 1 9

*0 . 1 u_ 1 0 V _X 5 R _ 0 4

.
C2 3 2 S USB # S USC # 3 G_ E N S W I# C H G_ E N

V D D3

V DD 3

J_K B1

24

EC MODULE CHOOSE (FOR DIFFERENCE K/B TYPE)


V ER . V 1. 0 RX R1 53 10 K/ R 149 X R1 53 X /R 14 9 1 0K
MO D E L _ I D V DD3 R N 19 2. 2K _ 4 P 2 R _ 0 4 3 2 4 1

V OL TA GE 3. 3V 0V
R1 5 3 R1 4 9

MO DE L_I D

E4120

B.Schematic Diagrams

1 0K _ 0 4 *1 0 K _ 04

V DD 3

RX

S M D_ B A T S M C_ B A T

Sheet 28 of 40 KBC-ITE IT8502E


VDD 3

3 G _D E T # C C D _D E T #

R 1 43 R 1 46

1 0 K _ 04 1 0 K _ 04

16 , 2 3 , 31 16 , 3 3 P CL K _ K B C R1 6 0 *1 0_ 0 4 P C L K _ K B C _ R

C2 2 3

S US _ P W R _ A CK 1 6 ME _ W E # 14 A C _ P R E S E N T 1 6 , 18 D D _O N _ L A T C H 31 W L A N _ D E T# 2 3 B T _D E T # 29 D D _O N 31 24

* 10 p _ 50 V _ N P O_ 06

C2 0 9 3 7 B A T_ V O LT B A T _ V OL T 1 u _ 6. 3 V _ X 5R _ 04

S MI # 19 S CI# 19 P W R _B T N # 1 6 RS M RS T # 1 6 K B C _ R S T# 1 9 CP U _ F A NS E N 30

4 ,1 9

H _P E C I

S M C _ C P U _ TH E R M R1 7 3 *0 _ 0 4

V CO RE _ O N 3 6 A L L_ S Y S _ P W R G D 1 2 , 16

V DD 3

C2 1 0 0 . 1 u _1 0 V _ X7 R _0 4

51 2K bit
U9 8 VD D SI SO CE # SCK 5 2 1 6

KBC_SPI_*_R = 0.1"~0.5"
K B C_ S P I_ S I_ R 1 K B C _ S P I _ S O_ R 2 K B C_ S P I_ CE # _ R 1 K B C _ S P I _ S C L K _ R2 4 3 4 3 R N 18 15 _ 4 P 2R _ 04 R N 17 15 _ 4 P 2R _ 04 K B C _ S P I_ S I K B C _ S P I_ S O K B C _ S P I_ CE # K B C _ S P I_ S CL K C 2 26 C 2 27 C 1 97 C 1 98 *3 3 p_ 5 0 V _N P O_ 0 4 *3 3 p_ 5 0 V _N P O_ 0 4 *3 3 p_ 5 0 V _N P O_ 0 4 *3 3 p_ 5 0 V _N P O_ 0 4

16 37 R1 3 1 1 K _ 0 4

? ? ?
K B C_ F L A S H 3 WP #

R 1 5 8 4 . 7 K _ 04 K B C _ H O LD #

H OL D #

VSS

E N 2 5 P 05 -5 0 GC P

C 2 31 1 2 p _5 0 V _ N P O _0 4

V DD 3 3 . 3V S

14 , 2 3 , 25 , 2 9 , 31 , 3 2 , 3 7 2, 1 0 , 1 1, 1 2 , 1 3, 14 , 1 5 , 16 , 1 7 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 2 5, 2 6 , 2 7, 2 9 , 3 0, 3 1 , 3 5, 3 6

KBC-ITE IT8502E B - 29

Schematic Diagrams

LED, MDC, BT
Bluetooth(Port8)
3 .3 V MJ _MDC 1 12 2 11 R 16 3 1 3 .3 V J _ MD C 1 1 4 , 27 H D A _ S D O U T 1 4 , 27 H D A _ S Y N C 14 H DA _ S DIN 1 1 4 , 27 H D A _ R S T # R1 6 1 R1 5 7 R1 5 5 R1 5 1 3 3_ 0 4 H D A _ S D O U T _ R 3 3_ 0 4 H D A _ S Y N C _ R 2 2_ 0 4 H D A _ S D I N 1_ R 3 3_ 0 4 H D A _ R S T # _R 1 3 5 7 9 11 GN D RE S E R VE D A za l a i _ SDO RE S E R VE D GN D 3 . 3V Ma n i /a u x A za l a i _ SYN C G ND A za l a i _ SDI G ND A za l a i _ RS T # A z al i a_ B C LK 8 8 01 8 -1 20 G 2 4 6 8 10 12 R 1 62 M D C _3 . 3 V *0 _ 06 B T _ DE T # 3 .3 V C4 7 3 *1 5m i l _s h o rt _0 6 * 18 0 p _5 0 V _ N P O _0 4 H D A _B I T C LK _ R C2 2 5 0 . 1u _ 1 0V _ X 7 R _ 0 4 R 14 8 C 22 0 2 2 p_ 5 0 V _N P O_ 0 4 2 3, 28 BT_ EN G S 3 3 _ 04 H D A _B I T C LK 1 4 , 2 7 D 1 0K _0 4 B T_ E N # R3 0 3 3. 3 V 15 P C H _ B T_ E N # *1 5 m li _ sh o rt _ 06 47 K _ 0 4 3 .3 V R3 0 2 *0 _ 04 3 V_ BT

COSTDOWN Port 11
18 18 28 23 U S B _P N 1 1 U S B _P P 11 B T _ DE T # B T_ E N # B T_ E N #

J _B T1 1 2 3 4 5 6 8 7 2 12 -0 6 G0

20 MIL

1. 5 V

R3 4 4

10mil L1 6

From EC default HI
50m il
R3 0 1 3 V _B T

50m il

* 15 m i _ l s h ort _ 0 6 Q1 7 MT N 70 0 2 Z H S 3 C4 7 4 1 80 p _5 0 V _ N P O _0 4 C 40 9 1 0 u_ 6 . 3 V _X 5 R _ 0 6 U2 1 4 5 B T _E N 3 V IN V IN EN V OU T 1 C 4 07 1 0 u _6 . 3 V _ X5 R _0 6

B.Schematic Diagrams

G ND

G ND * G5 2 43 A

Sheet 29 of 40 LED, MDC, BT

PN:G 5 24 3A-- 6-0 2- 05 243 -9 C 0

LED

3. 3 V S 3 .3 V S E 3 .3 V S 3. 3 V S 3. 3 V S

3 .3 V S

V DD 3

V DD 3

V D D3

V D D3

R 6 B Q 3 D T A 1 14 E U A A R1 22 0 _ 04 S A T A _L E D # 14 R2 22 0 _ 04 R 3 2 2 0_ 0 4 R 4 2 2 0 _0 4 2 2 0_ 0 4

R5 2 2 0_ 0 4

R1 9 2 2 20 _ 0 4

R1 9 3 2 20 _ 04

R 19 5 2 2 0_ 0 4

R 19 4 2 2 0_ 0 4

BT LED
D5 R Y -S P 17 2 Y G3 4

1 2

D 2 R Y -S P 1 72 Y G 34

R Y -S P 1 7 2 Y G3 4

R Y -S P 1 72 Y G 34

B Q2 D TC 11 4 E U A

L E D_ P W R # 2 8 W L A N_ E N 2 3, 2 8 L E D _A C I N # 2 8

HDD/ODD LED

D 3

NUM LOCK LED

D4

CAPS LOCK LED

SCROLL LOCK LED

SG

R Y -S P 15 5 H Y Y G 4

R Y -S P 1 5 5 H Y Y G4

SG

SG

D1

WLAN LED

POWER ON LED
D 12

BAT LED
1 3 D1 3 R Y -S P 15 5 H Y Y G 4

L E D _B A T _ F U L L # 28 LE D _ B A T _C H G # 2 8

L E D _ N U M# 2 8

L E D _C A P # 28

L E D _ S C R OL L # 28 C

B BT_ EN E Q 1 D TC 1 14 E U A 2 3, 2 8 4 , 9 , 10 , 1 1 , 21 , 2 3 , 27 , 3 1 , 33 , 3 6 1. 5V 3 , 4, 1 2 , 1 4, 1 5 , 1 6, 18 , 1 9, 20 , 2 1 , 23 , 2 4 , 25 , 3 0 , 31 , 3 3 , 34 , 3 5 3. 3V 14 , 2 3 , 25 , 2 8 , 31 , 3 2 , 37 V D D 3 2, 1 0 , 1 1, 1 2 , 1 3, 1 4 , 1 5, 1 6 , 1 7, 1 8 , 1 9, 20 , 2 1, 23 , 2 4 , 25 , 2 6 , 27 , 2 8 , 30 , 3 1 , 35 , 3 6 3. 3V S

H2 C 1 5 8 D 1 58

H1 C 1 58 D 1 5 8

H 12 H 6_ 3 D 3 _ 8

H 10 H 8 H 6_ 3 D 3 _ 8 H 6 _3 D 4_ 4 3 4 5

H 11 1 9 8 7 6 3 4 5

H7 1 9 8 7 6 3 4 5

H2 4 1 9 8 7 6 3 4 5

H 27 1 9 8 7 6 3 4 5

H1 5 1 9 8 7 6 3 4 5

H1 4 1 9 8 7 6

M2 M-M A R K 1

M6 M -MA R K 1

M7 M-MA R K 1

M8 M-M A R K 1

M1 M -MA R K 1

MT H 3 1 5D 1 11

MT H 3 1 5 D 1 11

MT H 31 5 D 1 1 1

MT H 3 1 5D 1 11

MT H 31 5 D 1 1 1

M TH 3 15 D 1 1 1

M5 M-MA R K 1

M3 M-M A R K 1

M4 M -MA R K 1

H 20 H 6 _0 D 3_ 7

H 16 H 6_ 0 D 3 _ 7

H 13 H 6_ 0 D 3 _ 7

H1 7 H 19 H 4 _ 7 B 6_ 0 D 3 _ 7 H 4_ 7 B 6 _0 D 3_ 7

20 09/1 1/5 H 9 3 4 5 1 9 8 7 6 3 4 5 H4 1 9 8 7 6 3 4 5 H 5 1 9 8 7 6 3 4 5 H3 1 9 8 7 6 3 4 5 H2 6 1 9 8 7 6

MT H 3 1 5D 1 11

MT H 31 5 D 1 1 1

MT H 3 1 5D 1 11

MT H 31 5 D 1 1 1

M TH 3 15 D 1 1 1

H 25 C 6 7D 6 7

H 6 C 67 D 67

H 23 C 15 8 D 1 5 8

H2 2 C1 5 8 D1 5 8

H2 1 H 18 H 4 _ 0B 7_ 0 D 3 _ 7 H 4_ 0 B 7 _0 D 3 _ 7

B - 30 LED, MDC, BT

Schematic Diagrams

USB, Fan, TP, Multi Con1


USB PORT*2(Port 0,Port1)
U4 5V U S B _F L G # 5 2 C 10 0 1 0 u_ 6 . 3 V _ X5 R _ 0 6 31 , 3 3 D D _O N # 3 4 F L G # V OU T1 VIN 1 VIN 2 EN # V OU T2 V OU T3 GN D 6 7 8 1 U S B V C C 01

FAN CONTROL
5 V S _F A N 5 VS F O N# 1 2 3 4 U1 9 F ON V IN V OU T VSET G9 9 0 P 11 U GN D GN D GN D GN D 8 7 6 5 28 CP U_ F A N

100 MIL
C1 1 7 0 . 1u _ 1 0V _ X 7 R _ 0 4 C 12 8 0 . 1 u_ 1 0 V _X 7 R _ 0 4 C 13 5 * 10 u _ 6. 3 V _ X 5R _0 6

R T 97 1 5 B GS 5 VS 5V S _F A N J _F A N 1 C4 0 2 US B V C C0 1 0 . 1u _ 1 0V _ X 7 R _ 04 L 10 H C B 16 0 8 K F -1 21 T 25 U S B _ V C C 0 1_ 0 1 0 u _6 . 3 V _ X5 R _0 6 C 4 01 1 2 3 8 5 2 05 -0 3 70 1

60 mil
+C 9 8 1 00 u _ 6. 3 V _ B _ A C8 7 0. 1 u _ 10 V _ X 7R _0 4

B.Schematic Diagrams

Port 0
J _U S B 1 1 V+ DA T A _ L DA T A _ H GN D GN D 1 G ND2 GN D 3 G ND4 3 2 3 4

28 C P U _ F A N S E N 3 .3 V S R2 7 3 4 . 7 K _0 4 J FAN 3 1

18 18

U S B _ P N0 US B _ P P 0

L9

1 2 *W C M2 0 1 2F 2 S -1 6 1T 0 3 -sh o rt

CLICK CONN
GN D 1 G ND2 GN D 3 GN D 4

FO R CL IC K BO AR D
5 V S _T P 5 VS R9 4 *1 5m i l _s h or t _0 6 C1 6 4 R 85 J _T P 1 1 2 3 4 8 5 20 1 -04 0 5 1 4 7 p_ 5 0 V _N P O_ 0 4 4 7 p_ 5 0 V _N P O_ 0 4 1 0 K _0 4 R 84 *1 0 u _6 . 3 V _ X5 R _0 6 1 0 K _ 04 TP _ D A TA TP _ C LK C 15 9 C 15 5 28 28 1u _ 6 . 3V _ X 5 R _ 04 C 1 69

3 .3 V

3 .3 V C 1 07 7 0 -10 4 A 3 R7 4 1 0K _ 0 4 R 77 *1 0 K _ 04 U S B _ F L G# R7 3 *0 _ 04 + C1 3 6 10 0 u _6 . 3 V _ B _ A C 1 77 0 . 1 u _1 0 V _ X7 R _0 4 U S B _ V CC0 1 _ 0

Sheet 30 of 40 USB, Fan, TP, Multi Con

18

U S B _ OC # 0 1

80 mil

Port 1
J _ US B 2 1 18 18 U S B _ P N1 US B _ P P 1 4 L1 3 3 2 3 4 V+ D A TA _ L D A TA _ H G ND G ND 1 GN D 2 G ND3 GN D 4 1 2 *W C M2 0 1 2F 2 S -1 6 1T 0 3 -sh o rt

POWER SWITCH CONN.


CLOSE TO J_SW1 FO R PO WE R SW IT CH B OA RD
3 .3 VS C2 0 3 . 3V C1 9 G S D Q 6 MT N 7 0 0 2Z H S 3 J _ SW 2 1 2 3 4 5 6 7 8 AP_ KEY# AP_ KEY # 2 8 3 . 3V S 3 .3 V

G ND 1 GN D 2 G ND3 GN D 4

C 1 0 7 70 -1 0 4A 3

2 0m il
M BTN R1 7 W E B _W W W # W E B _E M A I L # L I D _S W # A P _K E Y # 1 00 K _ 0 4 M _B TN #

Audio/B

CONN.(Port 2)
F OR A UD IO B OA RD

5V

0 . 0 1u _ 5 0V _ X 7 R _ 04

0 . 01 u _ 50 V _ X 7R _0 4

1.1 A 60mils
C 2 22 0 . 0 1 u_ 5 0 V _X 7 R _ 0 4 J_ S W 1 1 2 3 4 5 6 7 8 9 10 *5 0 50 0 -01 0 4 1-0 0 1 L

2 0m il
R 20 M _ B TN # _R W E B _W W W # W E B _E MA I L # L I D _S W # A P _O N VIN 1 00 K _ 0 4 M _B T N # 31 W EB_ W W W # 2 8 W E B _ EM A IL # 2 8 L I D _ S W # 1 2, 2 8 A P _O N 31

J _ A U D I O1 R1 5 0 27 M I C 1 -R 27 M I C 1 -L 2 7 H E A D P H O N E -R 2 7 H E A D P H O N E -L 27 M I C _ S E N S E 18 18 U S B _P N 4 U SB_ PP4 R 1 69 R 1 71 *1 0 mi l _ sh o rt *1 0 mi l _ sh o rt U S B N4 _ R U S B P 4 _R 27 S P K O U T R + 27 S P K O U T R 27 H P _S E N S E * 1 5m i l_ s h ort _ 0 6 M I C 1 -R M IC1 -L H E A D P H ON E -R H E A D P H ON E -L M IC_ SE NS E SPK_ H P# H P _S E N S E U S B N4 _ R U S B P 4 _R S P K O UT R+ S P K O UT R1 2 3 4 5 6 7 8 9 10 11 12 13 14 8 7 21 3 -1 40 0 G

8 8 4 86 -0 80 1

3 , 4 , 1 2, 1 4 , 1 5, 1 6 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 9 , 3 1, 3 3 , 3 4, 3 5 3 . 3V 2, 1 3 , 1 7, 2 0 , 2 1, 2 6 , 2 7, 3 1 , 3 5, 3 6 5 V S 2 1, 2 4 , 2 7, 3 1 , 3 3, 3 4 5 V 1 2, 3 1 , 3 2, 3 3 , 3 4, 3 5 , 3 6, 3 7 V I N 2 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 6 , 2 7, 2 8 , 2 9, 3 1 , 3 5, 3 6 3 . 3V S

If system has APON function, uses J_SW1 If system has no APON function, uses J_SW2

USB, Fan, TP, Multi Con1 B - 31

Schematic Diagrams

5VS, 3VS, 1.05VS


VA V IN V IN 1

S Y S 5V PC 6 5 0 . 1 u _5 0 V _ Y 5 V _ 0 6 P C 64 0 . 1 u_ 5 0 V _ Y 5 V _ 0 6 PC 6 3 0 . 1 u _ 50 V _ Y 5V _0 6

SY S5 V

PU 3 VA V IN 30 M _B TN # P_ SW 1 *T J G -53 3 -S -T / R 2 4 6 5 1 3 30 A P _ ON 1 2 3 4 VA VIN M_ B T N # I N S T A N T -ON P 2 8 08 A 1 V IN1 D D _ ON _L A T C H P W R_ S W # GN D 8 7 6 5 V IN 1

ON D D_ON " L " TO "H " FROM E C


D D _O N _ L A T C H 28 P Q4 5 A MT D N 7 0 02 Z H S 6 R D D _O N 2 G 6

P R1 9 3 1 0 K_ 0 4 D D _ ON # D D _ ON # 3 0 ,3 3 P Q4 5 B MT D N 7 0 0 2Z H S 6 R P C1 8 9 S 1 P R 19 2 * 0 . 1 u_ 1 0 V _ X5 R _0 4 1 6 , 2 3, 2 8 S US B # 5 G 3

P R1 9 4 10 K _ 0 4 S US B

PW R _ SW # 2 8 P R 85 1 0 K _ 04 V DD 3 28

D P C1 9 0 S

*0 . 1 u_ 1 0 V _ X 5R _ 04

ON

B.Schematic Diagrams

D EB UG U SE E VT ? ? ?

O N

P R 1 95 1 0 0K _0 4

1 0 0K _ 0 4 5V

ON ON

Sheet 31 of 40 5VS, 3VS, 1.05VS


5V
S Y S 1 5 V V D D5 P Q 47 P 1 2 03 B V 8 7 3 6 2 5 1 4 5V

C2 1 2 0 . 0 1u _ 5 0 V _X 7 R _0 4

C2 7 6 0 . 0 1u _ 5 0V _X 7 R _ 0 4

C9 7 0. 0 1 u _ 50 V _ X 7 R _ 0 4

5VS
NMO S
S Y S 1 5V V D D5

1.5VS
P Q4 6 P 12 0 3 B V 8 7 3 6 2 5 1 4 5 VS SYS1 5 V 1 .5 V

NMO S
P Q1 6 P 1 20 3 B V 8 7 3 6 2 5 1

1 .5 V S

3A
PR 9 8 1 M _0 4 Z 3 5 06

3A

5V P R 97 1 M_ 0 4

Power Plane

P R1 9 7 1M _ 04 P C1 9 3 0 . 1 u _ 10 V _ X 7 R _ 0 4 1 .5 V S _ E N

P C 19 2 4 0 . 1 u_ 1 0 V _ X7 R _ 04

P C 1 91 P R 19 6 1 0 u_ 6 . 3 V _ X 5R _ 0 6 1 00 _ 1 % _0 4 3Z 3 5 1 5 D 5 G S 4 P Q 48 B M TD N 7 0 0 2Z H S 6 R

Z 3 50 7 6 D PQ 1 5 A M T D N 70 0 2 Z H S 6R G D D _ ON # 1 1

P C 74 2 4 7 0 p_ 5 0 V _ X7 R _ 04 S

P C 73 4 7 0p _ 5 0V _X 7 R _ 0 4 5

3 P Q1 5 B M T D N 7 00 2 Z H S 6R G 4 1 P C1 9 4 S USB 33 22 0 0 p _5 0 V _ X 7R _ 04 2 S 1 4 0m i l 2 D 6 P Q4 8 A M T D N 7 00 2 Z H S 6 R S US B G

S PJ 1 1 P J1 2

4 0 m il

3 .3 V S 3 .3 V

ON

ON

C 13 7 0 . 0 1 u_ 5 0 V _ X7 R _ 04

C 105 0 . 0 1 u _5 0 V _ X 7 R _ 0 4

C 1 90 0 . 0 1 u_ 5 0 V _ X 7R _ 04

1.5VS_CPU
1 .5 V PJ 4 O P E N _2 A 1 1 . 5V S _ C P U

3.3V
S Y S 1 5 V V D D3

3.3VS
P Q 41 P 1 2 03 B V 8 7 3 6 2 5 1 4 S Y S 15 V 3 .3 V VDD 3

PJ3 MUST SHORT

VA 37 1. 5V S _C P U 4, 7 1. 5V 4 , 9, 10 , 1 1 , 2 1, 2 3 , 2 7 , 2 9, 3 3 , 3 6 1. 5V S 2 0, 2 3 , 3 6 SYS5 V 3 2, 3 7 5V 2 1, 2 4 , 2 7 , 3 0, 3 3 , 3 4 3. 3V 3 , 4, 12 , 1 4 , 1 5, 1 6 , 1 8 , 1 9, 2 0 , 2 1 , 2 3, 2 4 , 2 5 , 29 , 3 0 , 3 3 , 34 , 3 5 V IN1 32 V IN 1 2, 3 0 , 3 2 , 3 3, 3 4 , 3 5 , 3 6, 3 7 V DD 5 32 V DD 3 1 4, 2 3 , 2 5 , 2 8, 2 9 , 3 2 , 3 7 3. 3V S 2 , 10 , 1 1 , 1 2 , 13 , 1 4 , 1 5 , 16 , 1 7 , 1 8, 19 , 2 0 , 2 1, 2 3 , 2 4 , 2 5, 2 6 , 2 7 , 2 8, 2 9 , 3 0 , 35 , 3 6 SYS1 5 V 32 5V S 2 , 13 , 1 7 , 2 0 , 21 , 2 6 , 2 7 , 30 , 3 5 , 3 6

NMO S
P Q1 3 P 1 2 03 B V 8 7 3 6 2 5 1 P C 70 4 PC 7 2 P R9 5 1 0 u _6 . 3 V _ X 5 R _ 0 6 * 1 00 _ 0 4 Z 35 1 0 P Q1 2 * MT N 70 0 2 Z H S 3 3. 3V S

SY S1 5 V PQ 3 * P 1 20 3 B V 8 7 3 6 2 5 1 4

3A
P R 1 74 1 M _0 4 Z 3 5 08

3A
Powe r Plane

NM OS
P R 60 *2 2 0 _ 04 Z 35 1 6 3 P Q 2A *2 N 7 00 2 K D W G SU SB 5 G 4 D P Q2 B *2 N 7 0 0 2K D W S P C2 8 PC 2 7 * 10 u _ 6 . 3 V _X 5 R _0 6

PR9 6 1 M_ 0 4

PR 6 3 * 1M _ 04

Z 35 0 9 6 PQ 1 4 A M T D N 70 0 2 Z H S 6R G S 1 D D _ ON #

0 . 1 u_ 1 0 V _ X 7R _ 04

1 .5 V S _ CP U E N

*0 . 1 u_ 1 0 V _ X5 R _ 04

2 2 0 0p _ 5 0 V _X 7 R _0 4 2

D 2 20 0 p _ 50 V _ X 7 R _ 0 4 5 S

P C 1 70

PC7 1

3 G SU SB G

PC 2 9 D * 22 0 0 p _5 0 V _ X 7R _ 04 2 S

4 P Q1 4 B M T D N 70 0 2 Z H S 6R

ON

ON

B - 32 5VS, 3VS, 1.05VS

Schematic Diagrams

Power 3.3V/5V
S Y S 5V PC 1 6 8 0 . 0 1u _ 5 0 V _ X 7R _ 04 Z 3 6 13 C PD 6 A V IN 1 Z 3 6 04 P C1 8 4 2. 2 u _ 1 6 V _ X5 R _ 06 I N TV C C 2 P R1 8 6 2_06 A P C1 8 5 1 00 0 p _ 5 0V _X 7 R _ 0 4 P R 1 78 2 _ 06 A S G ND 4 Z 3 6 05 PD 3 Z 3 60 6 P R 18 7 PR 1 7 2 1 0 K_ 0 4 P R1 7 7 20 K _ 1 % _ 0 4 S GN D 4 S G ND 4 20 Z3602 Z3603 19 18 Z3601 17 16 PC 1 7 4 1 0 0 0 p_ 5 0 V _ X 7 R _ 0 4 P C1 8 0 P R1 8 0 P C1 7 6 *0 . 1 u _1 0 V _ X 5 R _0 4 P R 17 5 7 5K _0 4 21 3 1 2 4 5 2 20 0 p _ 50 V _ X 7 R _ 0 4 RB 0 5 4 0 S 2 C SY S1 5 V P C1 6 5 C PC 1 6 9 0 . 0 1u _ 5 0 V _ X 7R _ 04 Z 3 6 14 C PD 4 A RB 0 5 4 0 S 2 2 20 0 p _ 50 V _ X 7 R _ 0 4 VI N 0 . 0 1u _ 5 0 V _ X7 R _ 04 PD 5 RB 0 5 4 0 S 2 A RB 0 5 4 0 S 2 C SY S1 0 V P C1 6 4 SY S5 V

L G ATE1 C9 4

P D 1 6 R B 0 5 4 0S 2

6 -1 3- 42 23 1 -2 8B
P R1 8 5 4 2 2 K _ 1 %_ 0 6

PU8
VIN V L DO 6 7 8 9 Z 3 60 8 Z 3 60 9 Z 3 60 7

P C4 8 0. 1u _ 5 0 V _ Y 5 V _ 06 P C1 8 2 1u _ 2 5 V _ 08

P C5 3 4 . 7u _ 2 5 V _ X 5 R _ 0 8

P C5 4 4. 7 u _ 2 5V _X 5R _ 0 8

V DD A

V O UT

PAD

FBL

N C

FB

B.Schematic Diagrams

E NL RT O N A GN D E N/P S V

P C1 7 3 1 u_ 2 5 V _ 0 8

IN T V CC 2 5 6 7 8

VDD5
S YS5 V V DD 5

SC418
PG N D V DD P RP S V

BST DH LX

4 1 2 3

PQ 1 0 I R F 8 7 07 P B F

IL IM

P G O OD

1 0 Z 3 61 0

P L8 4 . 7 U H _ 6 . 8* 7 . 3 *3 . 5 1 2

5A
P C 1 86 PR 1 9 0 9 1 K _ 1 %_ 0 6 P C 16 6 P C5 5 + P C 1 71 + P C 1 87 PR 1 8 3 1 0 K _ 1 %_ 0 4

P J 19 1 2

D L

5 6 7 8

* OP E N -5 m m C P R 19 8 PD 7 *2 . 2 _ 0 6 S K 3 4S A A P C 19 5 P R1 9 1 * 1 5m i l _ sh o rt _ 0 6 * 2 20 p _ 5 0V _0 4

LG A T E 1

P Q6 I RF 8 7 0 7 P B F 1 2 3

Sheet 32 of 40 Power 3.3V/5V

15

14

12

1 u _ 2 5V _0 8

10 K _ 0 4

1 37 K _ 1 % _ 0 4

11

13

OCP
Z3611 PR 1 6 8 11 3 K _ 1 % _ 04 Z3612 P R1 7 3 P R1 6 9 1 0K _1 % _ 0 4 *1 0 0 K _ 04 P C1 6 7 1u _ 2 5 V _ 08 P C 1 78 1 u _2 5 V _ 0 8

0 . 1 u _5 0 V _ Y 5V _0 6 *1 5 0 u _6 . 3 V _ V _ A 1 5 0 u _ 6. 3 V _ V _ A *2 2 0 0 p_ 5 0 V _ X 7R _ 0 4 * 1 00 p _ 5 0 V _ N P O _ 04

S G N D4 SG ND 4 S G ND 4 S GN D 4 S G ND 4

S GN D 4

S YS5 V

INT V C C2

P R1 8 4 0_06

P R1 8 2 *0 _ 06 PR 1 7 0 *9 . 1 K _ 0 4 SY S5 V

10 0 p _ 5 0V _N P O _0 4

OCP
P R1 7 1 Z 3 6 25 1 0 K _ 1 % _0 4 Z3618 C

P D1 7 R B 0 5 4 0S 2

P R 18 9 *1 5 m i _ l s h o rt _ 06

V IN

5 6 7 8

P C 18 8

P R1 7 6 1 0 K_ 0 4

P R 1 81 1 0 K _ 1% _ 0 4 P R1 7 9 0_04

4 PC 1 7 9 PQ 7 I R F 87 0 7 P B F 1 2 3

0. 1u _ 5 0 V _ Y 5 V _ 0 6

4 . 7 u _ 25 V _ X 5 R _ 0 8

4 . 7 u_ 2 5 V _ X 5 R _ 0 8

Ra

P C5 8

PC 5 6

P C 57

PU 9 S C 4 12 A 1 LX B ST VC C D L 2 3 4 17 PAD Z3620 Z3621 Z3622 Z3619

13

14

15

16

VDD3
S YS3 V

0 . 1 u _ 50 V _ Y 5 V _ 06 1 2

IL IM

N.C

Z3615

12 EN 11 P GD

N.C

D H

5A

PJ 1 8 1 2

V D D3

Z3616 Z3617 P C1 8 3 *4 7 p _5 0 V _ N P O_ 0 4 P C1 7 2 0 . 0 1 u _ 50 V _ X 7 R _ 0 4

10 9

V OU T FB

PL 9 4. 7 U H _ 6 . 8 *7 . 3 *3 . 5 PR 2 0 1 PD 1 4 * 2 . 2_ 0 6 S K 3 4S A + P C4 6 *1 5 0 u_ 6 . 3 V _ V _ A PC 1 9 6 + PC 4 5 1 5 0 u _6 . 3 V _ V _ A P C1 7 5

* OP E N -5 m m

4 1 2 3

P Q4 2 I RF 8 7 0 7 P B F A

5 6 7 8

N.C

Rb
P R 1 88 2 . 9 4 K _ 1% _ 0 4 P C1 7 7 0 . 0 1 u _ 50 V _ X 7 R _ 0 4

G ND

N .C

RT N

0. 1 u _ 5 0 V _ Y 5 V _ 0 6

P C 18 1 1 u_ 2 5 V _ 0 8

* 2 20 0 p _ 50 V _ X 7 R _ 0 4

20 09/11 /17

V I N1 SY S1 5 V V D D3 V D D5 SY S5 V VI N

31 31 14 , 2 3 , 2 5 , 2 8, 29 , 3 1 , 3 7 31 31 , 3 7 12 , 3 0 , 3 1 , 3 3, 34 , 3 5 , 3 6 , 37

Power 3.3V/5V B - 33

Schematic Diagrams

Power 1.5V/0.75V/1.8VS

5V V D DQ V IN

3 .3 V

P R 81

P R8 3 1 0_ 0 6 P U2 Z3 80 1 3 V D D QS P GD 7

P R7 5 1 00 K _ 0 4 P D2 R B 0 5 40 S 2

( 1 .5 V= 1 .5 17 V )
P R8 2 1 0 _0 6

1 . 5 M_ 0 4

D D R 1 . 5 V _ P W R GD

D D R 1. 5 V _ P W R GD

16 VIN

PC 5 9 1 0 0 p_ 5 0 V _ N P O _0 4

Ra
P R8 4 1K _0 4

P C6 0 1 u _ 25 V _ 0 8

P C 51 0. 1 u _ 5 0V _ Y 5 V _ 0 6 1 u_ 2 5 V _ 08 Z3 80 3 P R 73 1 0 _0 6 PC 4 4 DH 1 0 0 0 p_ 5 0 V _X 7R _ 04 Z3 80 6 1 0 V T TS Z3 80 7 P C 52 LX 1 u _2 5 V _ 0 8 4 Z3 80 9 1 4 15 1 0u _ 6 . 3V _X 5 R _0 6 V DD Q *1 0 u_ 6 . 3 V _ X 5 R _ 0 6 P C3 9 1 u _ 2 5V _ 0 8 PC 3 7 12 13 1 11 VSSA VT T VT T VDD P 2 VDD P 2 EN/P S V V T TE N S C4 8 6 1 .5 VE N P P P P GN D GN D GN D GN D 2 1 1 2 VDD P 1 20 PC4 0 1u _ 2 5 V _0 8 25 18 16 17 5V D L 5 VCC A IL IM P R 74 21 Z3816 7. 1 5 K _ 1 %_ 0 4 22 Z3817 5 6 7 8 5 6 7 8 19 Z3818 P Q 36 MD S 2 6 55 4 1 2 3 Z3 80 5 6 8 9 T ON FB RE F C O MP P R7 8 *1 5 m i _ l s h ort _ 0 6 Z 38 1 3 24 Z3812 P C 15 6 +P C 1 61 P R7 6 *1 5 m i _ l s h ort _ 0 6 23 Z3814 PC 4 7 0 . 1 u _5 0 V _ Y 5 V _ 0 6 Z 3 8 15 4 1 2 3 5 6 7 8 PQ 3 8 MD S 2 65 9 1 5 u_ 2 5 V _ 6. 3 * 4. 5 _ E L N A 0 . 1u _ 5 0V _Y 5 V _ 0 6 Z3 80 2 2

B.Schematic Diagrams

P R 72 1 0_ 0 6 Z3808

Rb
P R7 7 10 0 K _ 1 %_ 0 4 *0 . 1 u _1 0 V _ X5 R _0 4

P C 1 57

BST

1.5V
V D DQ PL 6 2 . 5 U H _ 10 * 10 * 5

OCP

VTT_MEM
V TT _ ME M

VSSA PJ 1 6 2 1 O P E N _2 A PC 1 5 8 + * 2 20 u _ 2. 5 V _ B _ A P C3 4 PR 6 6

P C1 5 0 5 60 u _ 2 . 5V _6 . 6 *6 . 6 *5 . 9

* 1 0u _ 6 . 3 V _X 5R _ 06

10 u _ 6. 3 V _ X 5 R _ 0 6

PC 3 6

P C 35

Sheet 33 of 40 Power 1.5V/0.75V/ 1.8VS

P C5 0

P C 42 1 u_ 2 5 V _ 08

P C3 8

PR 6 7

8A
+ P C 1 46 * 22 0 u _2 . 5 V _ B _ A P C 15 3 0. 1 u _ 50 V _ Y 5V _ 0 6

PJ 5 1 2 OP E N _ 8 A 1 .5 V

* 0 . 06 8 u _5 0 V _ 0 6 *1 5 m i l_ s h ort _ 0 6

P Q 37 4 *M D S 2 6 5 5 1 2 3

P C 1 55 0 . 0 1 u_ 5 0 V _ X7 R _0 4

PD 1 3 S K 34 S A A

1.5A

* 2 0K _ 1 % _ 04

P R 1 65 *1 5 m il _ s ho rt _ 0 6 V SSA

5V

P R7 9

4 7K _ 0 4 3 5 4 PJ 7 S P Q9 B MT D N 7 00 2 Z H S 6R G D D

PC 4 9 PQ 8 0 . 1 u _5 0 V _ Y 5 V _ 0 6 * MT N 70 0 2 Z H S 3

P R8 0

1 0 0 K _0 4 6 D

Z 3 81 9 1

1 6 ,2 8

S US C#

G S 1

2 4 0 m il 2 3 0 ,3 1 D D_ O N# 5V 4 , 16 , 3 4 1 . 1V S _ V TT _ P W R GD PR 6 9 PR 7 0 1 0 0K _ 0 4 *1 0 0 K _ 04 6 3 D SU SB P Q5 B 5 2 N 7 0 02 K D W 4 S G S 1 D 2 P Q5 A 2N 7 00 2 K D W P C 43 0 . 1 u_ 5 0 V _ Y 5 V _ 06 V TT E N

P Q9 A MT D N 7 0 02 Z H S 6 R

V T T _M E M

PR1 6 6

10 0 _ 04

DDR3 VDDQ --> 1.5V ( V POWER) 330uF*3 , 10uF*6 VTT-->0.75V ( VS POWER) 10uF*3, 1uF*4

31

SUS B

S USB

ON
? ? ? ? PI N6? 5V

3 .3 V
P C1 6 0

1.8VS
3A
1 0 u_ 6 . 3 V _ X 5 R _ 0 6 VS 1 .8 PJ 6 1 0 . 1 u _1 0 V _ X 7 R _ 0 4 10 u _ 6 . 3V _ X 5 R _0 6 2 O P E N _3 A 1 . 8V S

2A
3 .3 V P R6 8 PR1 6 7 1 0K _0 4 EN1 .8 VS 1 . 8V S _P W R G D 5 9 7

PU7 V IN V IN P OK V C N TL V OU T V OU T E N G ND VFB 2 6 4 3

1 u_ 2 5 V _ 08

5V

10 K _ 0 4

8 1

P R1 6 3 1 . 27 K _ 1 % _0 4

PC 3 3 P Q4

P C1 5 1

AX 6610
* 1u _ 2 5V _0 8 P C1 5 2 0 . 1 u _ 50 V _ Y 5 V _ 06 P C 15 9 8 2p _ 5 0V _ N P O_ 0 4 1 0 u_ 6 . 3 V _ X 5R _ 0 6 PR1 6 4 1K _1 % _ 04

31

S US B

PR 7 1

6 2 K _1 % _ 0 4 P C 41

G MT N 70 0 2 Z H S 3 S

P C1 4 7

P C 14 8

* 0. 1 u _ 50 V _ Y 5V _ 0 6

G S7113 6 -02-07113-32 0 A X6610 6 -02-06610-32 0

B - 34 Power 1.5V/0.75V/1.8VS

P C 1 49

7 ,2 0 1 2, 3 0 , 3 1 , 32 , 3 4 , 3 5, 3 6 , 3 7 2 1 , 24 , 2 7 , 3 0, 3 1 , 3 4 3 , 4 , 1 2 , 14 , 1 5 , 1 6, 1 8 , 1 9 , 20 , 2 1 , 2 3, 2 4 , 2 5 , 29 , 3 0 , 3 1, 3 4 , 3 5 4 , 9 , 1 0, 1 1 , 2 1 , 23 , 2 7 , 2 9, 3 1 , 3 6 1 0 , 11

1. 8 V S VIN 5V 3. 3 V 1. 5 V V T T_ M E M

Schematic Diagrams

Power 1.1VS_VTT
5V

OCP
P R8 6 6 . 4 9 K _ 1 % _ 04

V IN P D8 R B 0 5 4 0S 2 C P C1 6 3 + 5 6 7 8 5 6 7 8 P Q4 0 MD S 2 6 59 4 VTT_ SEN SE 6 2 3 1 2 3 1 P Q3 9 *I R F 7 4 1 3Z P B F 1 5 u _ 2 5V _6 . 3 * 4 . 5 _E LN A

1.1VS_VTT=0.75 X (1+PR65 / PR67)

1.1VS_VTT
25A(15A)
V T T 1 .1 V S 1 P J1 7 2 1. 1V S _ V T T

PC 6 2

ON
3 .3 V

13

15

16

14

1 .1 V S _ V T T _ E N _ R PR 9 0 1 0 K_ 0 4 12 EN 11 10 FB 9

P U4 S C4 1 2 A

0 . 1 u _ 50 V _ Y 5 V _ 0 6 PL 7 0 . 5 6U H _1 0 * 10 * 4 . 1

I LI M

G 1

G0

DH

1 LX BST 2 3 4 4 2 3 1 PQ 4 3 M D S 26 5 5 4 S K3 4 SA 17 2 3 1 2 2 0u _ 4 V _ V _ B A P Q4 4 M D S 2 65 5 C 5 6 7 8 5 6 7 8

B.Schematic Diagrams

4 , 16 , 3 3 1 . 1 V S _ V TT _ P W R G D

PG D V O UT FB D 0 D1

* OP E N -1 2 m m

VC C DL

P D1 5

+ P C 15 4

PC 6 9 0 . 1 u _ 5 0V _Y 5 V _ 0 6

+ P C 16 2 2 20 u _ 4 V _ V _ B

GN D

R TN

PA D

PC 6 1 1 u _ 25 V _ 0 8

Sheet 34 of 40 Power 1.1VS_VTT

PR 9 2 0_04

P R 88 1 0K _ 1% _ 0 4

P C6 6 *2 0 p _5 0 V _ N P O_ 0 4

5V

P R9 3

*9 0 . 9 K _ 1 % _0 4

PC 6 7 P R 89 0 . 1 u _1 0 V _ X 7 R _ 0 4 2 4K _ 1% _ 0 4

(1.1VS_VTT=1.067V)

P J1 0 2 1 PJ 9 1 4 0 mi l PR 8 7 *1 0 0 K _ 0 4 3 D G 6 D 1 6 1 .1 V S _ V T T _ E N G S 1 2 2 PQ 1 1 A * 2N 7 0 02 K D W 4 P J8 4 0 m il 1 S 5 PQ 1 1 B * 2 N 7 0 0 2K D W P R9 1 1 u _ 1 0 V _ X7 R _ 0 4 2 1. 1V S _ V T T _E N _ R

5V

PR 9 4

1 00 K _ 0 4 1 0 K_ 0 4

P C6 8 * 0 . 1 u _1 0 V _ X 5 R _ 0 4

2, 4 , 6 , 7 , 1 4 , 1 5 , 1 6, 19 , 2 0 , 2 1 , 3 5 , 3 6 1. 1V S _ V T T 3 , 4 , 12 , 1 4 , 1 5 , 1 6 , 1 8, 19 , 2 0 , 2 1 , 2 3 , 24 , 2 5 , 2 9 , 3 0 , 3 1, 33 , 3 5 3 . 3 V 2 1 , 2 4 , 2 7 , 3 0, 31 , 3 3 5 V 1 2 , 30 , 3 1 , 3 2 , 3 3 , 3 5, 36 , 3 7 V I N

Power 1.1VS_VTT B - 35

Schematic Diagrams

Power VGFX_CORE

1. 1 V S _V T T P J2 3. 3 V PR 58 7 7 7 7 7 7 7 1 0K _ 04 D F G T_ V I D _ 0 D F G T_ V I D _ 1 D F G T_ V I D _ 2 D F G T_ V I D _ 3 D F G T_ V I D _ 4 D F G T_ V I D _ 5 D F G T_ V I D _ 6 DF G DF G DF G DF G DF G DF G DF G T_ V I D _ 0 T_ V I D _ 1 T_ V I D _ 2 T_ V I D _ 3 T_ V I D _ 4 T_ V I D _ 5 T_ V I D _ 6 2 40 m li 1 1 K _0 4 1K _ 04 1K _ 0 4 *1 K _0 4 * 1K _ 04 1 K _ 04 *1 K _0 4 PJ 4 F OR CV ? ?? PJ 3 3. 3 V S P R5 9 1 K _ 04 2 40 mi l 1 D F G T_ V R _ E N

? ? JU MP? ?

B.Schematic Diagrams

3 .3VS
7 D F GT _ V R _ EN

5 VS
P R 42 V IN

PR5 0

* 0. 0 1u _ 50 V _X 7 R _ 04

1 0_ 06

PR 40 *1 0K _ 1 %_ 04 1 6 V GF X _ VO R E _ P G 7 GF X _I M ON 30 28 32 26

*4 . 7u _2 5 V _X 5 R _ 08

0. 1 u_ 5 0V _ Y 5V _ 0 6

4. 7 u _2 5 V_ X 5 R _ 08

4 . 7u _2 5 V _X 5 R _ 08

Sheet 35 of 40 Power VGFX_Core

47 0 _0 4

1 0K _ 1% _ 04 P R 49 PR 48 P R4 7 P R4 6 P R4 5 P R 44 P R4 3 P R3 7

1. 1VS_VT T

* 1K _ 04 *1K _ 0 4 *1 K _0 4 1 K _0 4 1 K _0 4 * 1K _ 0 4 1K _ 04

P R 57 PR 56 P R5 5 P R5 4 P R5 3 P R 52 P R5 1

P C2 3 1 u_ 6 . 3V _ X5 R _ 04 5 6 7 8

VGFX_CO RE
15A (7A)
(0. 7V~1 .77V)
V GF X_ C O R E GP U 2 P J 15 OP E N _8 A PL 3 1. 0 U H _ 10 *1 0 *4 . 5 1 2 * 0. 1 u_ 1 0V _ X 5R _0 4 + P C 1 30 P C1 3 7 1 + *2 20 0 p_ 5 0V _ X 7R _0 4 P C1 2 9 P C 1 38 *0 . 01 u_ 5 0V _ X 7R _0 4 *2 20 u _4 V _V _ B

P C8 5

P C5

PC 4

P C8 8

3.3 V S

EN

P R3 8 P C2 5 0. 1 u _5 0V _ Y 5 V _0 6 PR 41 * 10 K _1 % _0 4 4. 7 K _ 1% _0 4 32 11 _ C LK E N # 2 3 4 P C 20 P C 21 PC 18 10 0 0p _ 50 V _X 7 R _ 04 P C1 9 P R3 3 P R 34 1K _ 1% _ 04 47 0 p_ 50 V _ X7 R _ 04 PR 32 0_ 04 P R2 2 7. 5 K _1 % _0 4 P R3 1 *0 _ 04 2 0K _ 1% _0 4 8 47 p_ 5 0V _ N P O_ 04 6 7 22 0 p_ 5 0V _ N P O_ 04 5 1 P W RG D

VI D 6

V ID0

V ID1

V ID2

V ID3

V ID4

V ID5

G N D _ 32 1 1 V CC BST 24 23 22 21 20 19 18 2. 2 u_ 1 6V _ X5 R _ 0 6 17 4 1 2 3 33 MD S 2 6 55 3 2 11 _D R V L PC 13 P Q2 5 4 1 2 3 3 2 11 _D R V H 3 2 11 _S W P R 35 0 _ 06 PC1 7 0. 2 2 u_ 5 0V _ 06

I M ON D RV H C LK E N # F B RT N FB C OMP P G ND G PU A G ND CS RE F IL IM L LI N E R A MP I R EF RP M R T C S C OM P CS F B A G ND P U1 AD P 32 1 1 SW P V CC DR V L

P R 1 54 *2 . 2_ 0 6 P Q2 4 MD S 26 55 A C 5 6 7 8 5 6 7 8 P D1 0 S K 34 S A P C 1 28

13

11

15

10

12

14

16

GN D _ 32 11

5VS GP U 0 1 Ap p. CP U GP U
G N D _ 32 1 1

GN D _3 2 11

3 2 11 _C S C OM P

3 21 1_ C S C O MP

P R8 8 0. 6 K _ 1% _0 4

P R7 2 00 K _ 1% _0 4

P R3 3 32 K _1 % _0 6

3 21 1_ C S C O MP

RT 2 10 0 K_ N T C _ 06 _ B 2 1

Pla ce RT H1 cl os e to ind uc tor o n t he s ame l aye r

P R 1 58 1 10 K _1 % _0 6

GP U V C C S E N S E 7

GN D _3 21 1 GN D _ 32 11 GN D _ 32 11

P R2 4 22 K _ 1% _0 6

P C8 1 50 0 p_ 50 V _ 06

P C 13 4 2 2 0p _ 50 V _N P O_0 4

P R 1 57 1 80 K _1 % _0 4 P R 1 56 16 0 K _1 %_ 0 4

P R 39 P R 36

1 0 0_ 1 %_ 04 1 0 0_ 1 %_ 04

G PU VIN
GP U V SS S E N SE 7 PC7 10 0 0p _5 0 V _X 7R _0 4 P R6 1 K _1 % _0 4

di str i bute evenl y between Nside and Ssid e, prefer ab ly on seconda r y si de.

P C2 4 1 00 0 p_ 50 V _ X7 R _ 04

GN D _ 3 21G 1 N D _ 32 1 1 2 , 4, 6 , 7 , 1 4 , 15 , 1 6, 1 9, 2 0 , 21 , 34 , 3 6 1 . 1V S _ V TT 3, 4 , 12 , 1 4, 1 5 , 1 6 , 18 , 19 , 2 0, 2 1 , 2 3 , 24 , 2 5, 2 9, 3 0 , 31 , 33 , 3 4 3 . 3V 4 , 9, 1 0 , 1 1 , 21 , 2 3, 2 7, 2 9 , 31 , 33 , 3 6 1 . 5V 7 V GF X _C O R E 1 2 , 30 , 3 1, 3 2, 3 3 , 34 , 36 , 3 7 V I N 2, 1 3 , 1 7 , 20 , 2 1, 2 6, 2 7 , 30 , 31 , 3 6 5 V S 2 , 10 , 11 , 1 2, 1 3, 1 4 , 15 , 16 , 1 7, 1 8 , 1 9 , 20 , 21 , 2 3, 2 4 , 2 5 , 26 , 2 7, 2 8, 2 9 , 30 , 31 , 3 6 3 . 3V S

B - 36 Power VGFX_CORE

2 20 u _4 V _V _ B

5V S

P C 96

1 2 3

P R 21 0_ 04

31

29

27

25

P Q1 9 MD S2 6 59

Schematic Diagrams

V-Core
V IN P C 80 * 1n _ 50 V _ 04 S G ND2 P R 1 11 *4 7K _ 0 4 CS _ P H1 CS _ P H2 P R 1 13 P R 1 14 P R 1 10 RT 1 c los e t o PL6 1 RT 3 1 00 K _N TC _0 6 _B 2 P R 1 06 73 . 2 K _1 % _0 4 P C8 3 15 0 0p _ 50 V _ 06 P C 81 4 7 0p _ 50 V _ X7 R _ 04 PC7 9 1 00 0 p_ 5 0V _ X 7R _0 4 S GN D 2 2 0 0K _ 1% _ 04 2 0 0K _ 1% _ 04 VIN 16 2 K_ 1 %_ 0 6 PR1 0 4 1 K _0 4 D D P Q3 0 I R F H 7 9 23 G S PQ 35 *I R F H 7 9 23 G S

FOR EMI
0 . 1u _ 50 V _ Y 5V _ 0 6 0 . 1 u_ 5 0V _ Y 5V _ 0 6 0 . 1u _ 50 V _ Y 5V _ 0 6 0 . 1 u_ 5 0V _ Y 5V _ 0 6 0. 1 u _5 0 V _Y 5 V _ 06 0 . 1u _ 50 V _Y 5 V _ 06 0. 1 u_ 5 0V _ Y 5 V _0 6 0. 1 u _5 0 V _Y 5 V _0 6 *3 3 0u _C A R 3 15 L + P C7 7

* 15 u_ 2 5V _ 6 . 3* 4. 5 _ E LN A

*1 5 u_ 2 5V _ 6 . 3* 4. 5 _E L N A

1 5u _2 5 V _6 . 3 *4 . 5_ E L N A

* 4. 7 u _2 5 V _X 5 R _ 0 8 +

0 . 1 u_ 5 0V _ Y 5V _ 0 6

0. 1 u _5 0 V _Y 5 V _0 6

P C8 2 1u _ 25 V _ 08

P C2 2

P C3 1

PC 3

0 . 1u _ 50 V _ Y 5V _ 06

P C7 6

P C8 4

P C7 8

P C9 1

C S C OM P CS S UM CS RE F C S C OM P 68 0 K _1 % _0 4 1 62 K _ 1% _ 06 4 7 . 5K _ 1 %_ 0 4 80 . 6 K _1 % _0 4

PC1 3 2

P C 10 6

P C 1 07

P C 32

PC8 9

P C 10 2

P C 26

P C 1 43

S GN D 2

HDR 1 PL 5 0. 3 6U H _ 12 . 9 *1 4* 3. 8

VCORE
24A
5 6 0u _ 2. 5 V _ 6. 6 *6 . 6 *5. 9 3 3 0u _ 2. 5 V _V _ A *3 30 u _2 . 5 V _V _ A *3 3 0u _ 2. 5 V _ V _A P R 16 2 1 00 _ 1% _0 4 1 0 _0 6 P C 13 6 A 2 2 0p _ 50 V _ N P O_ 0 4 VIN CS RE F * 4. 7 u _2 5 V _X 5 R _ 0 8 C S _P H 1 P R 16 0 5 . 1 _0 6 P D1 2 S K 34 S A C

V CO RE

3. 3 V S

3. 3 V S

P R 10 7 1 . 6 9K _ 1 %_ 04

B.Schematic Diagrams

24 23 22 21 20 19 18 17 16 P R 1 08 1 5 P R1 0 5 1 4 P R 10 9 13 P R 1 12

P R 12 3 3 K _ 1% _ 04 4 , 1 6 D E LA Y _ P W R G D 6 2 P C9 4 10 0 0p _ 50 V _ X7 R _ 04 S GN D 2 I MON CL K E N#

P R1 2 6 3 K _1 % _0 4 V R _ ON 1 2 3 4 5 6 7 T R D E T# 8 9 5 VS 10 TT S N S 1 1 12 49 S GN D 2

0 . 2 2u _5 0 V _0 6

ADP3212
36 35 34 33 32 31 30 29 28 27 26 25 P R 1 27 2_ 0 6 P R 1 25 10 0 _0 6 P R 1 20 10 0 _0 6 CS _ P H2 C S _P H 1

5 VS G S

SW FB3 P W M3 OD 3# IL IM C S C O MP CS S UM C SR E F L L INE RA M P RT R PM IREF

P Q2 9 I R FH 79 3 2 G

P Q3 4 I R F H 7 9 32 S

33 0 u_ 2 . 5V _ V _A

P U5

P C 98

* 33 0 u_ 2. 5 V _ V _A

1 5 u_ 2 5V _ 6 . 3* 4. 5 _E L N A

4 . 7 u_ 2 5V _ X 5R _0 8

0 . 1 u_ 5 0V _ Y 5V _ 0 6

P C 97 0. 1 u _5 0 V _Y 5V _ 06

P C9 0 15 0 p_ 5 0V _ 0 6

PC9 2 12 p _5 0 V _N P O_ 04 PC9 5 15 0 p_ 5 0V _ 0 6

P C 93

P Q27 I R F H 7 92 3 G

P Q3 2 *I R F H 79 23 G

*4 . 7u _2 5 V _X 5 R _ 0 8

37 38 39 40 41 42 43 44 45 46 47 48

HD R2

PC1 1 1

P C 1 00

P C 1 33

P C 1 12

P R 12 4 5 . 49 K _ 1% _ 04

P R 1 22 1. 6 K _ 1% _ 04

P R1 2 1 3 9. 2 K _ 1% _0 4

C S _P H 2

RS N

RS P

VRT T T TS N S A GN D A GN D

VC C PH1 PH0 D P RS L P PS I# VID6 VID5 VID 4 VID3 VID2 VID 1 VID0

P R 16 1 1 0 _0 6

P R6 4

EN P W RG D I MO N CL K E N# F B RT N FB C O MP T RDET # VA RF R

BST 1 DR V H1 SW 1 SW FB1 P VCC DRVL 1 P GN D DRVL 2 SW FB2 SW 2 DR V H2 BST 2

BST 1

5 VS P C 13 9

+ P C 1 40

+ PC1 4 1

+ P C 1 44

+ P C 14 5

5 VS

PL 4 0. 3 6 U H _ 1 2. 9 *1 4 *3 . 8

24A

4 H _P R OC H OT # D P R 20 S GN D 2 G 10 _0 6 1 . 1V S _ V TT P C 12 1u _2 5 V _0 8 *6 4 9_ 1 %_ 04 64 9 _1 %_ 0 4 1K _ 0 4 1 K _0 4 1 K _0 4 * 1K _ 0 4 *1 K _0 4 1 K _0 4 * 1K _ 0 4 S GN D 2 P R1 9 P R1 8 0 _0 4 * 10 0 0p _ 50 V _ X7 R _ 04 0 _0 4 PR2 3 PR2 4 PR2 5 P R 26 PR2 7 PR2 8 P R 29 2 PR1 4 5 P R 1 46 R SN R SP P C 30 P R 62 0 _ 04 V S S _S E N S E 6 P R 65 0 _ 04 V CC_ S E NS E 6 1 . 5V 1 . 5V S P R 1 17 2_ 0 6 B ST 2 D P C8 7 0 . 22 u _5 0 V _0 6 G S P R 15 9 5 . 1 _0 6 D P Q2 8 I R F H 7 9 32 G P Q3 3 I R F H 7 9 32 S A C P D1 1 S K 34 S A P C 13 5 2 2 0p _ 50 V _ N P O_ 0 4

P Q1 8 MT N 7 00 2Z H S 3 S

6 P M_ D P R S L P V R 6 PS I#

P R 30 * R _ 04

6 6 6 6 6 6 6

H_ V ID0 H_ V ID1 H_ V ID2 H_ V ID3 H_ V ID4 H_ V ID5 H_ V ID6 *1 K _0 4 *1 K _0 4 * 1K _ 04 1 K _ 04 1K _ 0 4 *1 K _ 04 1 K _ 04

PR6 1 PJ 1 4 0m il 10 0_ 1 %_ 0 4

5V S 5 VS

P R1 1 5 0 _0 4 3. 3 V S P R 1 31 P R 14 7 10 0K _ 0 4 P Q 22 A 10 K _0 4 P Q2 2B MT D N 70 0 2Z H S 6 R G 6 D 2 1 S 1 4 P J1 4 40 mi l 2 S V R _ ON

P R 1 19 P R 11 6 5. 1 K _ 1% _ 04 7. 3 2K _ 1 %_ 0 4 T TS N S 1 R T1 10 0K _ N T C _ 0 6_ B 2 PC 86 P R 1 18 0. 0 1u _ 50 V _ X7 R _ 0 4 *R _ 0 4 28 V C OR E _ ON G M TD N 70 0 2Z H S 6R T R D E T# P R1 1 P R1 2 P R1 3 P R 14 P R1 5 P R1 6 P R 17 3 D 5 PR1 3 0 *1 0 K _0 4 4, 9 , 10 , 1 1, 2 1 , 23 , 2 7, 2 9 , 31 , 33 2 0 , 23 , 31 2 , 4 , 6, 7 , 14 , 1 5, 1 6 , 19 , 2 0, 2 1 , 34 , 35 6 12 , 3 0, 3 1 , 32 , 3 3, 3 4 , 35 , 37 2 , 13 , 17 , 2 0, 2 1 , 26 , 2 7, 3 0 , 31 , 35 2 , 10 , 1 1, 1 2 , 13 , 1 4, 1 5 , 16 , 17 , 1 8, 1 9 , 20 , 2 1, 2 3 , 24 , 25 , 2 6, 2 7 , 28 , 2 9, 3 0 , 31 , 35 1 . 5V 1 . 5V S 1 . 1V S _ V T T V CO RE V IN 5 VS 3 . 3V S S G ND2

P C 11 4 * 0. 1 u _1 0 V _X 5R _0 4

P C 14 2

Sheet 36 of 40 V-Core

V-Core B - 37

Schematic Diagrams

DC-In, Charger
CHARGER
? ? :6-20-B3410-003
JA C K 1 50 9 3 2- 00 3 0 1-0 0 1 1 2 G ND 1 G ND 2 PL 1 H C B 4 5 3 2K F -80 0 T 60 VA 8 7 6 5 4 P Q1 7 P 20 0 3 E V G 3 2 1 0 _ 04 P R9 9 0. 0 2 _ 1 %_ 3 2 0_04 2 1 4 . 7u _ 2 5V _ X 5 R _0 8 4 . 7u _ 2 5V _X 5 R _0 8 0 . 1 u _5 0 V _ Y 5 V _ 06 0 . 1 u _ 50 V _ Y 5 V _ 06 V IN 1 2 3 P Q2 6 A A P 69 0 1 GS M 7 5 6 4 . 7u _ 2 5V _ X 5 R _0 8 4 . 7u _ 2 5V _X 5 R _0 8 4 . 7u _ 2 5V _X 5 R _0 8 4 . 7u _ 2 5V _X 5 R _0 8 4. 7 u _ 25 V _ X 5 R _ 0 8 4 . 7 u_ 2 5 V _X 5 R _0 8

# Char ge Cur r en t 3.0A


VA PQ 2 3 P 2 0 0 3E V G 5 6 7 8 P R1 3 9 0 . 0 2 _ 1% _ 3 2 4

# Char ge Volt age 12.6V # To tal Pow er 60W

PL 2 4. 7 U H _ 6 . 8* 7 . 3* 3 . 5

V_ BAT

P C7 5 0 . 1u _ 5 0V _ Y 5 V _ 0 6

PC 1 0 . 1 u _5 0 V _ Y 5 V _ 06

P C2 0 . 1u _ 5 0V _Y 5 V _ 0 6 P R1

P R 10 3 1 3 0K _ 1 % _0 4

P R1 0 1 2 0 0K _ 1 % _ 04

1 0 K_ 0 4 P R 10 2 1 0 K _1 % _ 04

P R1 4 8 0_04

3 P Q 26 B A P 6 9 0 1G S M P C1 2 4 4

PC 1 6

P C1 5

P C1 0

P C1 2 7

P C1 2 5

P C1 2 6

P C1 2 3

P C1 2 2

B.Schematic Diagrams

1 0 0K _ 0 4

PC 1 4 P D1 C

0 . 1 u _ 50 V _ Y 5 V _ 0 6 *0 _ 04 P C 11 3 1 u_ 2 5 V _ 08 A R B 0 5 4 0S 2 P R5 P R1 3 6 0_ 0 4

V_ BAT

Sheet 37 of 40 DC-In, Charger


V IN

P C 1 09 0 . 1 u _5 0 V _ Y 5 V _ 06

P C1 1 0 0 . 1u _ 5 0V _ Y 5V _0 6

P C 1 20 0 . 1 u_ 5 0 V _ Y 5 V _ 06

PIN 25t h FOR 2S CON NECT T O G ND FOR 3S CON NECT N.C. FOR 4S CON NECT T O VREF PIN
PR 4 *0 _ 04

P R 10 0

VA 32 31 30 29 28 27 26 25

P U6 1 2 3 4 5 6 7 8 P R1 5 3 P R 15 5 10 K _ 1 % _0 4 S G ND 6 V DD 3

VA V IN C TL 1 G ND VR EF RT C S A DJ 3 BATT S G ND 24 23 22 21 20 19 18 17 33 P C1 0 3 0 . 1 u _5 0 V _ Y 5 V _ 06 C T L1 R1 6 0. 1u _ 5 0V _ Y 5 V _ 0 6 V OL T _ S E L 0 . 1 u_ 5 0 V _ Y 5V _0 6 P R1 4 0 S GN D 6 3 9 . 2 K _1 % _ 04 4 9. 9 K _ 1 % _0 4 S M C_ B A T 1 0 K _ 04 V D D3

P C 1 19 0 . 1u _ 5 0 V _Y 5 V _0 6

P C1 1 8 0 . 1u _ 5 0V _ Y 5V _0 6

P C 1 17 0 . 1 u _5 0 V _ Y 5 V _ 0 6

P C1 1 6 0 . 1 u _ 50 V _ Y 5 V _ 0 6

9 10 11 12 13 14 15 16

MB 3 9 A 1 3 2 P C9 9 1 0 0 p_ 5 0 V _N P O_ 0 4

-I N E 1 O UT C 1 OU T C 2 + INC 2 -I N C 2 AD J 2 C O MP 2 C OM P 3

V CC -I N C 1 +I N C 1 A CIN A CO K -I N E 3 A DJ 1 C O MP 1

CT L 2 C B OU T -1 LX VB O U T -2 P GN D C E LL S

TRE RMAL PAD

S M D_ B A T P R1 4 2 1 K _1 % _ 0 4

TOTAL POW ER A DJ

10 K _ 1 % _0 4

P R1 3 4 1 K _ 1 % _0 4

P C1 3 1 P C1 1 P R 1 32 0. 01 u _ 50 V _ X 7R _ 04 P C1 0 4 * 2 2p _ 5 0V _ N P O_ 0 4 P C1 0 1 1 0 0 0p _ 5 0V _ X 7 R _ 0 4 P R 1 3 7 2 2 K _ 1% _ 0 4 P C1 0 8 1 0 0 0p _ 5 0V _ X 7 R _ 0 4 P R 1 4 3 S G ND 6 1 0K _ 1 % _ 04 PC 6

CHA RGE CUR REN T ADJ


B A T _ DE T

P R1 4 9 1 0K _0 4 A C _I N # C C PD 9 U DZ 1 6 B A P C1 1 5 *0 . 1 u _5 0 V _ Y 5 V _ 06 E B P Q3 1 D T C 11 4 E U A 28 P R 15 2 20 K _ 1 % _0 4 S G ND 6 S G ND 6 S G ND 6 S G ND 6 2 2K _ 1 % _ 04

P R1 4 4 B A T _ V O LT

C AC A D9 B A V 9 9 R E C TI F I E R C AC A D8 B A V 9 9 R E C TI F I E R C AC A D7 B A V 9 9 R E C TI F I E R C AC A D6 B A V 9 9 R E C TI F I E R

VA

S GN D 6

0. 5V/ 1A 0. 5V/ 1A

V_ BAT T OT A L _ C U R CU R_ S E N S E P R 13 3 1 0 2K _ 1 % _ 04 V OL T _ S E L P R2 0 0 28 28 28 28 S M C_ B A T S M D_ B A T B A T _ DE T B A T_ V O LT 5 6 7 8 9

PIN17t h CON NECT T OBAT CON N.


B T D - 05 T I 1 G 10 5 1 2 3 4 S MC _ B A T_ R S MD _ B A T_ R B A T _D E T _ R B A T _V OL T _R 4 3 2 1 J BAT TA1 G S 7 6 . 8K _1 % _ 04 PQ 4 9 M TN 7 00 2 Z H S 3 V C H G_ S E L 2 8 P L C1 E F 0 8 05 V 0 5 4 00

SYS5 V PQ 2 1 A O 3 40 9 S D P R1 2 8 3 00 K _ 1 % _0 4 B A T _ V OL T _ R P R 1 41 P R1 0 20 0 K _ 1 %_ 0 4 G P R 1 38 6 0 . 4 K _ 1% _ 0 4 P R9 0 _0 4 D 28 C H G_ E N G 1 S 1 P C 10 5 MT D N 7 00 2 Z H S 6R 0 . 1 u_ 5 0 V _Y 5 V _ 06 6 D 2 G 1 0 0 K _0 4 P Q2 0 A

SY S5 V 2M _ 1% _ 0 4 P R 19 9 P R1 3 5 1 00 K _ 0 4 CT L 1 3 D 5 4 PJ 1 3 OP E N -1 m m 2 S P Q 20 B MT D N 7 0 02 Z H S 6 R D

V _B A T

P Q1 MT N 7 0 0 2Z H S 3

P R 12 9

*1 5m i l _s h o rt _ 06 S G ND 6

S Y S 5V

G S

S YS5 V V DD3 VA V IN

3 1 , 32 1 4, 2 3 , 2 5, 2 8 , 2 9 , 31 , 3 2 31 1 2, 3 0 , 3 1, 3 2 , 3 3 , 34 , 3 5 , 36

B - 38 DC-In, Charger

P C 12 1

0 . 1 u _5 0 V _ Y 5V _0 6

P R 15 1

P R 1 50

P C9

Schematic Diagrams

Click Board
CLICK BOARD

CC2 0.1u_10V_X7R_04 C5VS CGND CJ_TP1 1 CTP_DATA 2 CTP_CLK 3 4 85201-04051 CGND C5VS

CC1 0.1u_10V_X7R_04

B.Schematic Diagrams

CJ_TP2 1 2 3 4 5 6 CTP_CLK CTP_DATA CTPBUTTON_L CTPBUTTON_R

CGND

85201-06051 CGND

Sheet 38 of 40 Click Board

CSW1~2 2 1 4 3

LIFT KEY
CSW1 TJG-533-S-T/R 1 3 5 6 2 4 CTPBUTTON_L 1 3

RIGHT KEY
CSW2 TJG-533-S-T/R 2 4 5 6 CTPBUTTON_R

CGND

CGND

CH3 2 3 4 5 1 9 8 7 6 2 3 4 5

CH1 1 9 8 7 6 2 3 4 5

CH4 1 9 8 7 6 2 3 4 5

CH2 1 9 8 7 6

MTH237D91 CGND CGND CGND

MTH237D91 CGND CGND

MTH237D91 CGND CGND

MTH237D91 CGND

Click Board B - 39

Schematic Diagrams

Audio / USB / RJ11 Board

RJ-11

USB PORT
A _ US B V C C AU 1 A _ 5V 5 F L G# V O U T 1 V IN1 V IN2 E N# V O UT 2 V O UT 3 G ND 6 7 A C9 8 0. 1 u _ 16 V _ Y 5 V _ 0 4 1 A GN D A G N D A GN D 0. 1u _ 16 V _ Y 5 V _ 0 4 A C1 0 A _U S B V C C

60 mils

60 mil s
A C1 3 1 0 u _1 0 V _ Y 5 V _ 08 A G ND A GN D

2 3 4

R T 9 7 15 B G S

6-0 2-09715- 920

B.Schematic Diagrams

A_ U S B V CC A L 10 H C B 1 6 08 K F -1 2 1 T2 5 A C1 6 +

A _U S B V C C 2

60 mil s
AC 1 1 . 1 U _1 0 V _ X7 R _ 0 4 A J _ US B 1 1 10 0 U _ 6 . 3V _B 2

A R6

* 10 m i l_ s h ort A G ND

AUDIO JACK
A M IC_ SE NS E A M I C 1 -R A M I C 1 -L AL 4 AL 3 F C M1 0 05 K F -1 2 1T 0 3 F C M1 0 05 K F -1 2 1T 0 3 A C5 A _5 V A J _ A U D I O1 A MI C 1 -R A MI C 1 -L A A A A A A A H E A D P H ON E -R H E A D P H ON E -L MI C _ S E N S E S P K _ HP # HP _ S ENS E US B _ PN4 US B _ PP 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 8 7 2 13 -1 4 L A _ A U DG A G ND 1 0 0 P _5 0 V _ 0 4 1 00 P _ 5 0V _ 0 4 A C6 Z 4 10 5 Z 4 10 6 Z 4 10 7 5 A J _ MI C 1 4 R 3 2 L 6 1 2 S J- S 35 1 -S 3 0

GN D 1 G ND 2 GN D 3 G ND 4

Sheet 39 of 40 Audio / USB / RJ11 Board

M ODEM
J _MOD EM1 2 1 A J_ MO D E M 1 Z 4 0 08 2 Z 4 0 09 1 8 5 2 04 -0 2 00 1 AL 1 AL 2 MH C 1 60 8 S 1 21 P B P Z 4 0 10 1 MH C 1 60 8 S 1 21 P B P Z 4 0 11 2

RJ-11
A G ND A J _ RJ 1 T IP RIN G C 10 1 8 1-1 0 2 05 -L PIN G ND1 ~ 2 = AG ND AU SB_ PP4 A U S B _ P N4 1 A R7 * 10 m i l_ s h ort A U S B _P N 4 _R A U S B _P P 4_ R

V+ DA T A _ L DA T A _ H GN D 1 GN D 2 GN D 3 G ND 4 C 1 07 7 0-1 0 4 A 3 A G ND

2 3 4

AL 9

A U S B _P P 4 _ R A U S B _P N 4 _R

GN D

4 3 * W C M 2 01 2 F 2 S -16 1 T 03

MIC IN

3 4

BLACK
A _ A U DG A H P _S E N S E ASPK_ H P# A H E A D P H ON E -R A R3 A H E A D P H ON E -L A R2 Z 4 1 12 A L 6 6 8_ 1 % _0 4 Z 4 1 13 A L 5 6 8_ 1 % _0 4 F C M 10 0 5K F -12 1 T 03 F C M 10 0 5K F -12 1 T 03 Z4108 Z4109 5 A J _ HP 1 4 R 3 2 L 6 1 2 S J- S 35 1 -S 3 0

A S P K OU TR + A S P K OU TR -

AR 4 * 1K _0 4

AR 1 * 1K _ 0 4

A C7 1 0 0 P _5 0 V _ 0 4

A C8 1 00 P _ 5 0V _ 0 4

HEADP HONE

BLACK
A _ A U DG A S P K OU T R + AL 8 1 2 F C M 10 0 5 K F -12 1 T 03

AL 7 F C M1 0 0 5K F -1 2 1 T0 3 A S P K O UT R1 2

A C1 2 10 0 0 p_ 5 0V _X 7 R _ 0 4

A J _ S P K R1 A S P KO UT R+ _ R A S P K O U T R -_ R A C1 4 1 2

J _SPK 1 2 1

A C1 5 AH 2 C 52 D 52 AH3 2 3 4 5 1 9 8 7 6 2 3 4 5 AH1 1 9 8 7 6 A C3 A C1 A C4 MT H 27 6 D 1 1 1 A G ND A G ND A G ND MT H 27 6 D 1 1 1 A C2 A GN D A G ND A _ A UD G 0. 1 u _1 6 V _ Y 5 V _ 0 4 0. 1 u _1 6 V _ Y 5 V _ 0 4 A _ A U DG 0. 1 u _1 6 V _ Y 5 V _ 0 4 0. 1 u _1 6 V _ Y 5 V _ 0 4 AR 5 *1 0 m li _ sh o rt 1 8 0p _ 50 V _ N P O_ 04

8 5 2 04 -0 2 00 1 P C B F oo t p ri nt = 8 5 2 04 -0 2 R 1 8 0p _ 5 0V _ N P O_ 0 4

B - 40 Audio / USB / RJ11 Board

Schematic Diagrams

Power Switch & LID Board

POWER SW & LED & HOT KEY


S _3 . 3 V

LID SWITCH IC
S _ 3 . 3V S C S _ 3. 3V SR 1 SU 1 1 22 0 _ 04 SJ _ SW 2 S M _B T N # SW EB_ W W W # S W E B _ E M A IL # S L ID_ S W # SAP_ O N S _ V IN S M GN D S M GN D 1 2 3 4 5 6 7 8 8 8 2 96 -0 8 00 SC2 Z4301 0 . 1 u_ 1 0 V _ X7 R _ 0 4 S M _ B TN # S W E B _W W W # S W E B _E MA I L # S L I D _S W # S A P _O N S MG N D SD 1 L TS T -C 15 0 T B K T C SC 6 A *0 . 1 u _1 0 V _ X5 R _0 4 S MG N D SU1, SU2 3 1 2 S M GN D S M GN D S MGN D G ND VC C OU T 2 S C1 M H -2 4 8 1 0 0 p_ 5 0 V _N P O_ 0 4 S LI D _ S W # A 1 0 0K _ 0 4 AC S _ 3. 3 V S S _ 3 .3 V S R2 S _ 3 . 3V S SJ _ SW 1 1 2 3 4 5 6 7 8 9 10 * 50 5 00 -0 1 04 1 -0 01 L S _3 . 3 V

SD 2 *B A V 99 R E C T I F I E R

B.Schematic Diagrams

P OWER S WITC H L ED

20 mi l 2 0m il 2 0m il

S M GN D

Sheet 40 of 40 Power Switch & LID Board

1 0 pin & 8 pi n co -la y


S M GN D

HOT KEY
POW ER BU TTON
SPW R_ SW 1 TJ G -53 3 -S -T / R 1 3 5 6 2 4 S M_ B T N # 1 3 5 6

S _V I N

WEB_WWW#
SW W W _ SW 1 T JG -5 33 -S -T / R 2 4 S W E B _W W W # 1 3

WEB _EMA IL#


S MA I L _ S W 1 TJ G -53 3 -S -T / R 2 4 5 6 S W E B _ E MA I L #

S R3 *1 00 K _ 0 4 1 3 SR 4 0_04

AP _KEY #
SAP_ SW 1 T JG -5 33 -S -T / R 2 4 SC 5 5 6 0 . 1 u_ 1 0 V _X 7 R _ 0 4 SAP_ O N S R5 * 47 K _ 0 4

SC 4 PSW 1~8 3 4 S MG N D 1 2 S M GN D S M GN D S MG N D 0 . 1 u_ 1 0 V _X 7 R _ 0 4

S C3 0 . 1u _ 1 0V _ X 7 R _ 04

S MG N D S MGN D S M GN D

S M GN D

S M GN D

S MH 1 2 3 4 5 1 9 8 7 6 2 3 4 5

S MH 3 1 9 8 7 6 2 3 4 5

S M H4 1 9 8 7 6

MT H 2 3 7D 8 7 S M GN D S M GN D

MT H 2 3 7 D 8 7 S MG N D

M TH 23 7 D 1 1 8 S MG N D

Power Switch & LID Board B - 41

Schematic Diagrams

B.Schematic Diagrams
B - 42