BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI Second Semester 2012-2013 CS C342 Advanced Computer Organization Lab Sheet - 7

1) Let us consider a three stage pipeline with 2 sets of pipeline registers. The encoder takes an 8-bit func_code as input and produces a 3-bit ctrl output. (Use Behavioral Modelling) The first stage pipeline register stores the ctrl value.The values A and B (both 4-bit) are forwarded in the first stage for use in the second stage. (Use RTL Logic) The ALU performs the following operations on the operands A and B based on the ctrl input and produces a 4-bit output X. (Use Behavioral Modelling) ctrl = 3'b000 : add; ctrl = 3'b001 : sub; ctrl = 3'b010 : xor; ctrl = 3'b011 : or; ctrl = 3'b100 : and; ctrl = 3'b101 : nor; ctrl = 3'b110 : nand; ctrl = 3'b111 : xnor The second stage pipeline register stores this value X. (Use RTL Logic) In the third stage, the even parity generator generates the parity for the value X. (Use Dataflow Modelling)

Encoder

ALU Ctrl A X

Even Parity Gener -ator

A B

Write a system module using the modules mentioned above. (Use structural modeling).

Use the following test bench:module test; reg clk,reset; reg [7:0]func_code; reg [3:0]A,B; wire parity; wire [3:0]val; system sys(clk,reset,func_code,A,B,parity,val); initial begin clk = 1'b0; reset=1'b1; #2 reset=1'b0; #2 reset=1'b1; end initial begin #5 A=4'b0110; B=4'b0100; func_code=8'b00000001; #10 func_code=func_code<<1; #10 func_code=func_code<<1; #10 func_code=func_code<<1; #10 func_code=func_code<<1; #10 func_code=func_code<<1; #10 func_code=func_code<<1; #10 func_code=func_code<<1; #25 $finish; end always #5 clk = ~clk; initial $monitor($time,"clk=%b,reset=%b,func_code=%b,A=%b,B=%b,parity=%b,val=%b",clk ,reset,func_code,A,B,parity,val); endmodule