BLOCK DIAGRAM

1-bit Full Adder

4-bit Full Adder

BEHAVIORAL LEVEL
module fulladder(sum, cout, a, b, cin);
output [3:0] sum;
output cout;
input [3:0] a;
input [3:0] b;
input cin;
wire c1,c2,c3;
fulladd fa0(sum[0],c1,a[0],b[0],cin);
fulladd fa1(sum[1],c2,a[1],b[1],c1);
fulladd fa2(sum[2],c3,a[2],b[2],c2);
fulladd fa3(sum[3],cout,a[3],b[3],c3);
endmodule
module fulladd(sum,cout,a,b,cin);
output sum,cout;
input a,b,cin;
reg s1,c1,sum,c2,cout;
always@ (a or b)
if (a==b)
s1=0;
else
s1=1;
always@ (a or b)
if ( a==b==1)
c1=1;
else
c1=0;
always@ (s1 or cin)
if (s1==cin)
sum=0;
else
sum=1;
always@ (s1 or cin)
if ( s1==cin==1)
c2=1;
else
c2=0;
always@ (c2 or c1)
if (c2==c1)
cout=0;
else
cout=1;
endmodule

DATA FLOW:
module fulladder(sum, cout, a, b, cin);
output [3:0] sum;
output cout;
input [3:0] a;
input [3:0] b;
input cin;
wire c1,c2,c3;
fulladd fa0(sum[0],c1,a[0],b[0],cin);
fulladd fa1(sum[1],c2,a[1],b[1],c1);
fulladd fa2(sum[2],c3,a[2],b[2],c2);
fulladd fa3(sum[3],cout,a[3],b[3],c3);
endmodule
module fulladd(sum,cout,a,b,cin);
output sum,cout;
input a,b,cin;
wire s1,c1,c2;
assign s1=a^b;
assign c1=a&b;
assign sum=s1^cin;
assign c2=s1&cin;
assign cout=c2^c1;
endmodule

GATE LEVEL:
module fulladder(sum, cout, a, b, cin);
output [3:0] sum;
output cout;
input [3:0] a;
input [3:0] b;
input cin;
wire c1,c2,c3;
fulladd fa0(sum[0],c1,a[0],b[0],cin);
fulladd fa1(sum[1],c2,a[1],b[1],c1);
fulladd fa2(sum[2],c3,a[2],b[2],c2);
fulladd fa3(sum[3],cout,a[3],b[3],c3);
endmodule
module fulladd(sum,cout,a,b,cin);
output sum,cout;
input a,b,cin;
wire s1,c1,c2;
xor(s1,a,b);
and(c1,a,b);
xor(sum,s1,cin);
and(c2,s1,cin);
xor(cout,c2,c1);
endmodule

TEST BENCH:
module stimulus;
reg[3:0]a;
reg[3:0]b;
reg cin;
wire[3:0]sum;
wire cout;
fulladder Fb1(sum,cout,a,b,cin);
initial begin $monitor($time,"sum=%b",sum);end
initial begin a=0;b=0;cin=0;#2 a=11;b=5;cin=1;
#2 a=15;b=6;cin=0;#2$finish;end
endmodule

SIMULATION