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hp StorageWorks enterprise virtual array Event Text Description File (C) Copyright 2001-2009 Hewlett-Packard Company nsaprocessed hsv450v9defaultpars

efile WARNING: Modification of this file may cause Enterprise Storage Management Software to improperly translate event information Model number string: HSV450 Software version number string: 09540000 Baselevel build string: CD1A2E Structure Format: Endian Little COUPLED CRASH CONTROL CODES: Coupled Crash Control Code: 0 Other HSV450 controller should not perform a coupled crash. Coupled Crash Control Code: 1 Other HSV450 controller should perform a coupled crash. DUMP/RESTART CONTROL CODES: Dump/Restart Control Code: 0 Perform crash dump then restart. Dump/Restart Control Code: 1 Do not perform crash dump, just restart. Dump/Restart Control Code: 2 Perform crash dump and do not restart. Dump/Restart Control Code: 3 Do not perform crash dump and do not restart. SEVERITY LEVEL CODES: Severity Level Code: 0 Normal -- informational in nature. Severity Level Code: 1 Critical -- failure or failure imminent. Severity Level Code: 2 Warning -- not failed but attention recommended or required. Severity Level Code: 3 Undetermined -- more information needed to determine severity. CORRECTIVE ACTION CODES: Corrective Action Code: 0 No action necessary. Corrective Action Code: 1 An unrecoverable hardware detected fault occurred or an unrecoverable software i

nconsistency was detected, proceed with HSV450 controller support avenues. Corrective Action Code: 2 Inconsistent/erroneous information received from the operating system. Proceed w ith operating system software support avenues. Corrective Action Code: 3 Follow the recommended corrective action shown in the termination corrective act ion code of this event's detailed information. The cause of the controller termi nation associated with this controller event can only be determined by obtaining the detailed information of the associated termination event. To obtain that in formation follow Corrective Action [[06]]. Corrective Action Code: 4 Follow the recommended corrective action described in the recursing termination event. Perform these steps to obtain that termination event's information: <UL> <LI>View the termination events of the HSV450 controller shown in this terminati on event's detailed information. NOTE: If that controller is not currently opera ting, the event of interest will not be available for viewing. <LI>Locate the te rmination event that occurred closest to the date and time shown in this termina tion event's detailed information and obtain that termination event's detailed i nformation. NOTE: The termination event of interest will show termination locati on, termination code and termination parameters that are identical to the recurs ive event termination location, recursive event termination code and recursive e vent termination parameters 0 through 28 shown in this termination event. </UL> <UL> <LI>View the termination events of the HSV450 controller shown in this terminati on event's detailed information. NOTE: If that controller is not currently opera ting, the event of interest will not be available for viewing. <LI>Locate the termination event that occurred closest to the date and time show n in this termination event's detailed information and obtain that termination e vent's detailed information. NOTE: The termination event of interest will show t ermination location, termination code and termination parameters that are identi cal to the recursive event termination location, recursive event termination cod e and recursive event termination parameters 0 through 28 shown in this terminat ion event. </UL> Corrective Action Code: 5 Follow the recommended corrective action described in the termination event repo rted by the other controller that caused this termination event to occur. Perfor m these steps to obtain that termination event's information: <UL> <LI>View the termination events of the other HSV450 controller (i.e., the controller NOT show n in this termination event's detailed information). NOTE: If that controller is not currently operating, the event of interest will not be available for viewin g. <LI>Locate the termination event that occurred closest to the date and time s hown in this termination event's detailed information and obtain that terminatio n event's detailed information. NOTE: The termination event of interest will sho w a termination location and termination code that are identical to the other co ntroller termination location and other controller termination code shown in thi s termination event. </UL> <UL> <LI>View the termination events of the other HSV450 controller (i.e., the contro ller NOT shown in this termination event's detailed information). NOTE: If that controller is not currently operating, the event of interest will not be availab le for viewing. <LI>Locate the termination event that occurred closest to the date and time show n in this termination event's detailed information and obtain that termination e vent's detailed information. NOTE: The termination event of interest will show a termination location and termination code that are identical to the other contr

oller termination location and other controller termination code shown in this t ermination event. </UL> Corrective Action Code: 6 Perform these steps to obtain the termination information associated with this c ontroller event: <UL> <LI>View the termination events of the HSV450 controller s hown in this event's detailed information. NOTE: If that controller is not curre ntly operating, the event of interest will not be available for viewing. <LI>Loc ate the termination event that occurred closest to the date and time shown in th is event's detailed information and obtain that termination event's detailed inf ormation. NOTE: The termination event of interest will show software version, ba selevel ID, and uptime information identical to that shown in this event's detai led information for the terminating controller. </UL> <UL> <LI>View the termination events of the HSV450 controller shown in this event's d etailed information. NOTE: If that controller is not currently operating, the ev ent of interest will not be available for viewing. <LI>Locate the termination event that occurred closest to the date and time show n in this event's detailed information and obtain that termination event's detai led information. NOTE: The termination event of interest will show software vers ion, baselevel ID, and uptime information identical to that shown in this event' s detailed information for the terminating controller. </UL> Corrective Action Code: 7 A significant hardware detected fault occurred or a significant software inconsi stency was detected. Accumulate information to report to HSV450 controller engin eering. Corrective Action Code: 8 A significant hardware detected fault occurred or a significant software inconsi stency was detected. Accumulate information to report to HSV450 controller engin eering. Corrective Action Code: 9 Determine power loss cause and take appropriate action to ensure power is restor ed and maintained. Corrective Action Code: a A portion of low memory is purposely set to produce an uncorrectable memory erro r in order to detect low memory access violations made by the HSV450 controller' s software (e.g., access to memory address zero through an uninitialized pointer , etc.). Unfortunately, there is no method available for immediately distinguish ing a low memory access violation from an uncorrectable memory error that occurs elsewhere in memory. However, the memory diagnostics that are executed followin g controller restart will immediately terminate HSV450 controller operation if a ny portion of memory is found defective. In that case perform corrective action [[20]]. If defective memory is not found during HSV450 controller restart and th is termination event is again reported, the most likely cause is a software indu ced low memory access violation. In that case perform corrective action [[01]]. Corrective Action Code: d User intervention is required for this HSV450 controller to continue processing. Examine the events contents in order to determine how to proceed. Corrective Action Code: 20 Replace the HSV450 controller Field Replaceable Unit (FRU). Note that the FRU mu st be a single power supply type if so indicated in this event's detailed inform ation.

Corrective Action Code: 22 Replace the '1' Battery Assembly Field Replaceable Unit (FRU)--i.e., the battery assembly closest to the cache battery door hinge. CAUTION: The information desc ribed in corrective action [[38]] must be understood before attempting a cache b attery replacement. Corrective Action Code: 23 Replace the '2' Battery Assembly Field Replaceable Unit (FRU)--i.e., the battery assembly farthest from the cache battery door hinge. CAUTION: The information d escribed in corrective action [[38]] must be understood before attempting a cach e battery replacement. Corrective Action Code: 24 Replace the '1' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blower farthest from the blower door hinge. Corrective Action Code: 25 Replace the '2' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blower closest to the blower door hinge. Corrective Action Code: 26 Replace the '1' Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i.e. , the blower/power supply closest to the cache battery door hinge. Corrective Action Code: 27 Replace the '2' Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i.e. , the blower/power supply farthest from the cache battery door hinge. Corrective Action Code: 28 Reinstall the '1' Battery Assembly Field Replaceable Unit (FRU)--i.e., the batte ry assembly closest to the cache battery door hinge. Corrective Action Code: 29 Reinstall the '2' Battery Assembly Field Replaceable Unit (FRU)--i.e., the batte ry assembly farthest from the cache battery door hinge. Corrective Action Code: 2a Reinstall the '1' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blowe r farthest from the blower door hinge. Corrective Action Code: 2b Reinstall the '2' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blowe r closest to the blower door hinge. Corrective Action Code: 2c Reinstall the '1' Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i. e., the blower/power supply closest to the cache battery door hinge, or restore AC power. Corrective Action Code: 2d Reinstall the '2' Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i. e., the blower/power supply farthest from the cache battery door hinge, or resto re AC power. Corrective Action Code: 2e Reduce the ambient temperature in the vicinity of the HSV450 controller. Corrective Action Code: 2f Ensure that both batteries in the indicated HSV450 controller are installed and

functioning normally. A cache battery failure will be indicated by the red batte ry status LED located on the OCP display. If that LED is on, open the battery co mpartment door and check for the amber status LED in the lower right corner of e ach battery assembly. If the amber status LED is ONLY on in the battery assembly closest to the battery compartment door hinge, perform corrective action [[22]] . If the amber status LED is ONLY on in the battery assembly farthest from the c ache battery door hinge, perform corrective action [[23]]. If the amber status L ED is on in BOTH battery assemblies, perform [[22]] and [[23]] simultaneously. Corrective Action Code: 30 GBIC SFF Serial ID Data check code failure. Corrective action: Try re-seating th e GBIC, if failure persists, replace the GBIC, lastly perform corrective action [[20]]. Corrective Action Code: 36 The temperature on the HSV450 controller has become critical. Proceed with corre ctive action [[2e]] and restart the controller. Corrective Action Code: 37 The temperature on the HSV450 controller could not be accurately determined poss ibly due to faulty operation of a temperature sensor or the temperature acquisit ion communication path. If the problem persists, perform Corrective Action [[20] ]. Corrective Action Code: 38 Before performing cache battery replacement the following must be understood: <U L> <LI>CAUTION: Never remove batteries from the HSV450 controller while it is po wered down. Replace a cache battery only when the controller power is on. <LI>CA UTION: If the amber status LED is on in both battery assemblies, both batteries must be removed before installing either of the new batteries. If one of the bat teries is replaced while the other failed battery is still in the enclosure, the original failure may be propagated to the newly installed battery. To ensure th ere is no propagated failure, wait a minimum of 15 seconds after the removal of both batteries before inserting the new batteries. <LI>CAUTION: Never install a battery that was previously failed by any HSV450 controller. <LI>NOTE: When inst alling a cache battery, the amber status LED will initially be on. The LED may r emain on for up to two minutes, after which time it will turn off. <LI>NOTE: It will take several hours for the HSV450 controller to recognize a new battery as fully charged. If a pair of batteries has been replaced, this period will be not iceably longer. </UL> <UL> <LI>CAUTION: Never remove batteries from the HSV450 controller while it is power ed down. Replace a cache battery only when the controller power is on. <LI>CAUTION: If the amber status LED is on in both battery assemblies, both batt eries must be removed before installing either of the new batteries. If one of t he batteries is replaced while the other failed battery is still in the enclosur e, the original failure may be propagated to the newly installed battery. To ens ure there is no propagated failure, wait a minimum of 15 seconds after the remov al of both batteries before inserting the new batteries. <LI>CAUTION: Never install a battery that was previously failed by any HSV450 co ntroller. <LI>NOTE: When installing a cache battery, the amber status LED will initially b e on. The LED may remain on for up to two minutes, after which time it will turn off. <LI>NOTE: It will take several hours for the HSV450 controller to recognize a ne w battery as fully charged. If a pair of batteries has been replaced, this perio d will be noticeably longer. </UL> Corrective Action Code: 39

If this event is an isolated occurrence, then no further action is necessary. If this event occurs more than once in a three month period, perform Corrective Ac tion [[20]]. Corrective Action Code: 3a Insert and re-seat the GBIC. If failure persists, replace the GBIC, or lastly pe rform Corrective Action [[20]]. Corrective Action Code: 3b Isolated occurrences of this event may be safely ignored. If this event occurs m ore than once in a three month period, perform Corrective Action [[20]]. Corrective Action Code: 40 Replace the indicated physical disk drive. Corrective Action Code: 41 Reinstall the indicated physical disk drive or install a drive blank. Corrective Action Code: 42 Perform these steps in an attempt to clear the error: <UL> <LI>Remove and reinst all the indicated physical disk drive. <LI>Observe the drive's status LEDs to en sure that the drive is operational. <LI>Observe the Drive Enclosure Environmenta l Monitoring Unit alphanumeric display to ensure the error no longer exists. </U L>If the error persists, perform Corrective Action [[40]]. <UL> <LI>Remove and reinstall the indicated physical disk drive. <LI>Observe the drive's status LEDs to ensure that the drive is operational. <LI>Observe the Drive Enclosure Environmental Monitoring Unit alphanumeric displ ay to ensure the error no longer exists. </UL>If the error persists, perform Corrective Action [[40]]. Corrective Action Code: 44 A Fibre Channel port has failed. This may be caused by a failure on the indicate d HSV450 controller, or the coprresponding Fibre Channel Switch. Proceed with co rrective action [[01]]. Corrective Action Code: 46 Numerous transport failures occurred while attempting to communicate with a Phys ical Disk Drive on a particular Device Port. The controller will attempt to an a lternate use Device Port to communicate with the Physical Disk Drive. If communi cation fails on the alternate Device Port, that Physical Disk Drive will be rend ered inoperable. This is a preemptive action warning, no immediate action is nec essary. Corrective Action Code: 47 Dropped frames are potential indications of an impending Fibre Channel port or p hysical disk drive failure when they occur excessively. If frame drop becomes ex cessive, the indicated Fibre Channel port or the indicated physical disk drive w ill be placed in the inoperative state. This is a preemptive action warning, no immediate action is necessary. Corrective Action Code: 48 Unexpected work from a physical disk drive is an indication of an impending driv e failure. If unexpected work becomes excessive, the indicated physical disk dri ve will be placed in the inoperative state. This is a preemptive action warning, no immediate action is necessary. Corrective Action Code: 49 Bad ALPAs are indications of an impending physical disk drive failure. If the nu mber of bad ALPAs becomes excessive, the indicated physical disk drive will be p

laced in the inoperative state. This is a preemptive action warning, no immediat e action is necessary. Corrective Action Code: 4a Unable to communicate through a Fibre Channel link to a Fibre Channel port. This may be caused by a missing Fibre connection to an HSV450 controller Host Port o r Drive Enclosure, faulty GBIC, faulty Drive Enclosure, faulty Fibre Channel Cab le, faulty Drive Enclosure I/O module, or faulty Fibre Channel Switch. This is a preemptive action warning, no immediate action is necessary. Corrective Action Code: 4c This event is probably a symptom of another problem. Check nel ports and multiple instances of this event. Also check multiple occurrences of this event pertaining to physical me rack or loop. If this is an isolated occurrence of this dicated physical disk drive and remove it from the system. for failed Fibre Chan for patterns, such as disk drives on the sa event, ungroup the in

Corrective Action Code: 4d Load the latest physical disk drive firmware superfile for the physical disk dri ve type shown in the SCSI Product ID of this event's detailed information. If no such superfile exists, the physical disk drive is unsupported, and should be un grouped and removed. Using a superfile that updates the controller approved firm ware table may be sufficient to correct the problem. Corrective Action Code: 4e This event is probably a symptom of another problem. Check for failed Fibre Chan nel ports and multiple instances of this event. Also check for patterns, such as multiple occurrences of this event pertaining to physical disk drives on the sa me rack or loop. Corrective Action Code: 4f Remove the indicated physical disk drive and install a drive blank. Corrective Action Code: 50 Delete the indicated inoperative Snapshot Storage System Virtual Disk. Corrective Action Code: 51 Evaluate previously reported Physical Device, Device Enclosure, and Storage Syst em Virtual Disk events to determine root cause and corrective action. Corrective Action Code: 52 Delete the indicated inoperative Storage System Virtual Disk, unless an instant restore operation is possible. Corrective Action Code: 5f Unable to communicate to the destination controllers, or through a specific path to the destination. Check to see if the destination controllers have malfunctio ned, and perform the repair actions indicated in event reports found for the des tination controllers. In addition, check for a malfunction that may have occurre d in the Fibre Channel fabric between the sites. Corrective Action Code: 60 Unable to communicate to the indicated source virtual disk, because the virtual disk or another member in the Data Replication Group malfunctioned. Perform the repair actions indicated in event reports found for that source virtual disk or another virtual disk member in that Data Replication Group. Corrective Action Code: 61 Unable to communicate to the indicated destination virtual disk on the remote St orage System because the virtual disk malfunctioned. Perform the repair actions

indicated in event reports found for that destination virtual disk on the remote Storage System. Corrective Action Code: 62 The Data Replication Log for the specified Data Replication Group has insufficie nt space to grow the log. A copy resynchronization will be started when data rep lication can resume. Evaluate whether sufficient disk storage has been made avai lable for the log to grow in capacity. If necessary, add new volumes to the Disk Group. Corrective Action Code: 63 The Data Replication Source Site and the Data Replication Destination Site canno t communicate because the software versions are incompatible. Communication will automatically continue when both sites are at compatible software levels. Corrective Action Code: 64 Check the Data Replication Destination Site for problems with physical disk driv es or fibre channel loops. The Data Replication Destination Site may also be tem porarily experiencing higher than usual levels of disk related activity. Corrective Action Code: 65 Check the Data Replication Destination Site for slow or no response for this Dat a Replication Group. If this is not the case then restart the Data Replication D estination Site controllers. Then restart the Data Replication Source Site contr ollers. Corrective Action Code: 66 Check both the Data Replication Source Site and the Data Replication Destination Site for slow or no response for this Data Replication Group. If this is not th e case then restart the Data Replication Source Site controllers. IF you have al ready taken this action and are receiving this event for a second time then rest art the Data Replication Destination Site controllers instead. Corrective Action Code: 67 Check link speed and quality between the Data Replication Source Site controller s and the Data Replication Destination Site controllers. Corrective Action Code: 68 Reduce the number of controller pairs on the fabric to the supported maximum. Corrective Action Code: 69 Check fabric switch settings and inter site link quality between the Data Replic ation Source Site controllers and the Data Replication Destination Site controll ers. Corrective Action Code: 6a The Data Replication Source Site and the Data Replication Destination Site canno t communicate because the software settings are incompatible. Communication will automatically continue when both sites are at compatible software settings. Corrective Action Code: 6b The Data Replication Source Site and the Data Replication Destination Site have a capacity mismatch on at least one of the their volumes. Check the source and d estination volumes to ensure that they are in agreement. Corrective Action Code: 80 Perform these steps in an attempt to clear the error: <UL> <LI>Remove and reinst all the indicated drive enclosure power supply. <LI>Observe the power supply/blo wer status LED to ensure that the power supply is operational. </UL>If the error persists, immediately (within 7 minutes) perform Corrective Action [[81]]. If t

hat action cannot be performed immediately, perform Corrective Action [[85]] imm ediately. <UL> <LI>Remove and reinstall the indicated drive enclosure power supply. <LI>Observe the power supply/blower status LED to ensure that the power supply i s operational. </UL>If the error persists, immediately (within 7 minutes) perform Corrective Ac tion [[81]]. If that action cannot be performed immediately, perform Corrective Action [[85]] immediately. Corrective Action Code: 81 Replace the indicated drive enclosure power supply. Hewlett-Packard recommends n ot removing a defective drive enclosure power supply until a replacement drive e nclosure power supply is available. Corrective Action Code: 82 Perform these steps in an attempt to clear the error: <UL> <LI>Remove and reinst all the indicated drive enclosure blower. <LI>Observe the power supply/blower st atus LED to ensure that the blower is operational. </UL>If the error persists, p erform Corrective Action [[83]]. <UL> <LI>Remove and reinstall the indicated drive enclosure blower. <LI>Observe the power supply/blower status LED to ensure that the blower is oper ational. </UL>If the error persists, perform Corrective Action [[83]]. Corrective Action Code: 83 Replace the indicated drive enclosure blower. CAUTION: Removing a blower automat ically closes flaps over the power supply blower opening. However, the air flow within the enclosure changes and can cause an over temperature condition. Hewlet t-Packard recommends not removing a defective blower until a replacement blower is available. Corrective Action Code: 85 If the problem cannot be corrected, the Enterprise Virtual Array should be shut down to: <UL> <LI>Flush data from the controllers. <LI>Shut down the drive enclo sures. <LI>Shut down the controllers. </UL>CAUTION: This is a drastic measure th at will stop all Enterprise Virtual Array operations. Hewlett-Packard recommends using this procedure only when necessary to protect a drive enclosure from over heating or to clear drive enclosure errors that cannot otherwise be cleared. <UL> <LI>Flush data from the controllers. <LI>Shut down the drive enclosures. <LI>Shut down the controllers. </UL>CAUTION: This is a drastic measure that will stop all Enterprise Virtual Ar ray operations. Hewlett-Packard recommends using this procedure only when necess ary to protect a drive enclosure from overheating or to clear drive enclosure er rors that cannot otherwise be cleared. Corrective Action Code: 86 If the indicated drive enclosure element's temperature sensor is high, follow th ese steps to correct the over temperature condition: <UL> <LI>Ensure that all el ements are properly installed to maintain proper air flow. <LI>Ensure that nothi ng is obstructing the air flow at either the front of the enclosure or the rear of the blower. <LI>Ensure that both blowers are operating properly (the LEDs are on) and neither blower is operating at high speed. If a blower appears to be de fective, perform Corrective Action [[83]]. <LI>Verify that the ambient temperatu re is within the range +10C to +35C (+50F to +95F). Adjust as necessary. </UL>If the indicated drive enclosure element's temperature sensor is low, follow this step to correct the below temperature condition: <UL> <LI>Verify that the ambien

t temperature is within the range +10C to +35C (+50F to +95F). Adjust as necessa ry. </UL> <UL> <LI>Ensure that all elements are properly installed to maintain proper air flow. <LI>Ensure that nothing is obstructing the air flow at either the front of the e nclosure or the rear of the blower. <LI>Ensure that both blowers are operating properly (the LEDs are on) and neithe r blower is operating at high speed. If a blower appears to be defective, perfor m Corrective Action [[83]]. <LI>Verify that the ambient temperature is within the range +10C to +35C (+50F t o +95F). Adjust as necessary. </UL>If the indicated drive enclosure element's temperature sensor is low, follo w this step to correct the below temperature condition: <UL> <LI>Verify that the ambient temperature is within the range +10C to +35C (+50F t o +95F). Adjust as necessary. </UL> Corrective Action Code: 87 Immediately perform Corrective Action [[86]]. If the problem persists after perf orming those actions, perform Corrective Action [[85]] immediately. Corrective Action Code: 89 Replace the indicated Drive Enclosure Environmental Monitoring Unit. Corrective Action Code: 90 Perform these steps in an attempt to clear the error: <UL> <LI>Check if one of t he HSV450 controllers has suffered a power failure. If so, perform Corrective Ac tion [[09]]. <LI>Check all the transceivers and cables to ensure they are proper ly connected. Reseat any that are not properly connected. <LI>If the problem is not corrected, check all the transceivers on the loop to ensure that they are dr ive enclosure I/O module compatible. Replace any transceivers that are found to be incompatible. <LI>If the problem is not corrected, replace the input cable co nnected to the indicated transceiver. <LI>If the problem is not corrected, repla ce both transceivers attached to the cable that is connected to the indicated tr ansceiver. </UL> <UL> <LI>Check if one of the HSV450 controllers has suffered a power failure. If so, perform Corrective Action [[09]]. <LI>Check all the transceivers and cables to ensure they are properly connected. Reseat any that are not properly connected. <LI>If the problem is not corrected, check all the transceivers on the loop to e nsure that they are drive enclosure I/O module compatible. Replace any transceiv ers that are found to be incompatible. <LI>If the problem is not corrected, replace the input cable connected to the in dicated transceiver. <LI>If the problem is not corrected, replace both transceivers attached to the c able that is connected to the indicated transceiver. </UL> Corrective Action Code: 93 Replace the indicated drive enclosure I/O module. Corrective Action Code: 95 Reset the indicated device enclosure I/O module using the following procedure: < UL> <LI>Remove the I/O module. <LI>Reinsert the I/O module. </UL>If the problem persists, perform Corrective Action [[93]]. <UL> <LI>Remove the I/O module. <LI>Reinsert the I/O module.

</UL>If the problem persists, perform Corrective Action [[93]]. Corrective Action Code: 99 Ensure that each drive enclosure I/O module is connected to the correct Fibre Ch annel port. Corrective Action Code: 9a Ensure A/C input to the rack PDU is intact, otherwise perform [[81]]. Corrective Action Code: b4 Add new volumes to the Disk Group or increase the Disk Group occupancy alarm lev el threshold. Corrective Action Code: b5 Add new volumes to the Disk Group or delete unwanted logical disks from Disk Gro up. Corrective Action Code: b6 To restore the Disk Group to a Single Point of Failure Robust Configuration add more physical disk drives or rearrange the existing Single Point of Failure Robu st Configuration to ensure the physical disk drives members are on different Fib re Channel device enclosures. Corrective Action Code: b9 Evaluate previously reported events associated with this HSV450 controller to de termine root cause and corrective action. Corrective Action Code: ba Check to see if this HSV450 controller has suffered a power failure. If so, perf orm Corrective Action [[09]]. Otherwise, perform Corrective Action [[b9]]. Corrective Action Code: bf Evaluate previously reported Device or Device Enclosure events that related to t he Physical Disk Drive that is associated with this Volume to determine root cau se and corrective action. Corrective Action Code: c3 Evaluate previously reported Device, Device Enclosure, and Host events to determ ine root cause and corrective action. If the problem persists, follow Corrective Action [[20]]. Corrective Action Code: c4 Load the latest physical disk drive firmware superfile for the physical disk dri ve type shown in the SCSI Product ID of this event's detailed information. If no such superfile exists, the physical disk drive is unsupported, and should be un grouped and removed. Using a superfile that updates the controller approved firm ware table may be sufficient to correct the problem. Corrective Action Code: dd Replace the '0' Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper l eft battery assembly. CAUTION: The information described in corrective action [[ e6]] must be understood before attempting a cache battery replacement. Corrective Action Code: de Replace the '1' Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower l eft battery assembly. CAUTION: The information described in corrective action [[ e6]] must be understood before attempting a cache battery replacement. Corrective Action Code: df Replace the '2' Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper r

ight battery assembly. CAUTION: The information described in corrective action [ [e6]] must be understood before attempting a cache battery replacement. Corrective Action Code: e0 Replace the '3' Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower r ight battery assembly. CAUTION: The information described in corrective action [ [e6]] must be understood before attempting a cache battery replacement. Corrective Action Code: e1 Reinstall the '0' Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper left battery assembly. Corrective Action Code: e2 Reinstall the '1' Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower left battery assembly. Corrective Action Code: e3 Reinstall the '2' Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper right battery assembly. Corrective Action Code: e4 Reinstall the '3' Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower right battery assembly. Corrective Action Code: e5 Ensure the required number of batteries in the indicated HSV450 controller are i nstalled and functioning normally. Each battery assembly has a green LED located to the side of a battery symbol label and an amber LED located to the side of a caution symbol label. A cache battery failure will be indicated when the amber LED is on and the green LED is off. If the upper left battery assembly is failed , perform corrective action [[dd]]. If the lower left battery assembly is failed , perform corrective action [[de]]. If the upper right battery assembly is faile d, perform corrective action [[df]]. If the lower right battery assembly is fail ed, perform corrective action [[e0]]. Corrective Action Code: e6 Before performing cache battery replacement the following must be understood: <U L> <LI>CAUTION: Never remove batteries from the controller while it is powered d own. Replace a cache battery only when the controller power is on. <LI>CAUTION: Never install a battery that was previously failed by any controller. <LI>NOTE: When installing a cache battery, the amber status LED will initially be on after insertion. It will remain on for several seconds while initial battery integrit y is checked, after which time it will turn off. <LI>NOTE: It will take several hours for the EVA controller to recognize a new battery as fully charged. </UL> <UL> <LI>CAUTION: Never remove batteries from the controller while it is powered down . Replace a cache battery only when the controller power is on. <LI>CAUTION: Never install a battery that was previously failed by any controlle r. <LI>NOTE: When installing a cache battery, the amber status LED will initially b e on after insertion. It will remain on for several seconds while initial batter y integrity is checked, after which time it will turn off. <LI>NOTE: It will take several hours for the EVA controller to recognize a new b attery as fully charged. </UL> Corrective Action Code: e7 Replace the '0' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the top blo wer.

Corrective Action Code: e8 Replace the '1' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the bottom blower. Corrective Action Code: e9 Reinstall the '0' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the top b lower. Corrective Action Code: ea Reinstall the '1' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the botto m blower. Corrective Action Code: eb Verify AC connection integrity of '0' Power Supply Assembly Field Replaceable Un it (FRU)-- i.e., the left power supply. Replace assembly if AC connection is goo d and malfunction persists. Corrective Action Code: ec Verify AC connection integrity of '1' Power Supply Assembly Field Replaceable Un it (FRU)-- i.e., the right power supply. Replace assembly if AC connection is go od and malfunction persists. Corrective Action Code: ed Reinstall the '0' Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the left power supply. Corrective Action Code: ee Reinstall the '1' Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the right power supply. Corrective Action Code: ef If this event is an isolated occurrence, then no further action is necessary. Pe rform these steps in an attempt to clear persistent occurrences: <UL> <LI>If thi s event persistently occurs for each installed battery brick in the controller, then verify the correct SDC version is installed. <LI>If this event persistently occurs for the '0' Battery Assembly, perform Corrective Action [[dd]]. <LI>If t his event persistently occurs for the '1' Battery Assembly, perform Corrective A ction [[de]]. <LI>If this event persistently occurs for the '2' Battery Assembly , perform Corrective Action [[df]]. <LI>If this event persistently occurs for th e '3' Battery Assembly, perform Corrective Action [[e0]]. <LI>If all previous st eps fail to stop event from occurring, perform Corrective Action [[01]] </UL> <UL> <LI>If this event persistently occurs for each installed battery brick in the co ntroller, then verify the correct SDC version is installed. <LI>If this event persistently occurs for the '0' Battery Assembly, perform Corr ective Action [[dd]]. <LI>If this event persistently occurs for the '1' Battery Assembly, perform Corr ective Action [[de]]. <LI>If this event persistently occurs for the '2' Battery Assembly, perform Corr ective Action [[df]]. <LI>If this event persistently occurs for the '3' Battery Assembly, perform Corr ective Action [[e0]]. <LI>If all previous steps fail to stop event from occurring, perform Corrective Action [[01]] </UL> Corrective Action Code: f0 This event indicates a SLAVE ROHS compliant HSV450 controller is being force loa ded from the MASTER with code that is inappropriate for this hardware. This will continue until this controller is made MASTER or the current master is upgraded

to the appropriate level of code that will run on both controllers. Corrective Action Code: f1 Remove the indicated enclosure. Corrective Action Code: f2 The Enterprise Virtual Array needs to be restarted to load new sprite code. Corrective Action Code: f3 Unable to communicate through a Fibre Channel link to a Fibre Channel port. This may be caused by a missing Fibre connection to an HSV450 controller Host Port o r Drive Enclosure, faulty GBIC, faulty Drive Enclosure, faulty Fibre Channel Cab le, or faulty Drive Enclosure I/O module. Examine events and clear any faults th at cause loss of redundancy. Corrective Action Code: f4 Verify AC connection integrity of the Disk Enclosure Power Supply. The Power Sup ply is located on the rear side of the Disk Enclosure. It is identified by the l abel 'PS 1' for the Left side or 'PS 2' for the Right side. Replace the Power Su pply if the AC connection is good and the malfunction persists. SOFTWARE COMPONENT ID CODES: Software Component ID Code: 1 Executive Services Software Component ID Code: 2 Cache Management Component Software Component ID Code: 3 Storage System State Services Software Component ID Code: 4 Fault Manager Software Component ID Code: 6 Fibre Channel Services Software Component ID Code: 7 Container Services Software Component ID Code: 8 Raid Services Software Component ID Code: 9 Storage System Management Interface Software Component ID Code: b System Services (DFP, XMFC, etc. processing) Software Component ID Code: c Data Replication Manager Component Software Component ID Code: d Disk Enclosure Environmental Monitoring Unit Services Software Component ID Code: e System Data Center Software Component ID Code: f

Mirroring & DMA Software Component ID Code: 42 Host Port Software Component ID Code: 83 Diagnostic Operations Generator only for XL Software Component ID Code: 84 Diagnostic Runtime Services (Scrubbing, UPS, temp/battery/voltage monitoring, et c.) only for XL EVENT CODES: Event Code: 0102000d Severity: Normal -- informational in nature. A time change occurred. Event Code: 0301400b Severity: Critical -- failure or failure imminent. A physical disk drive has bee n rendered inoperable. Event Code: 03024f0b Severity: Warning -- not failed but attention recommended or required. A physica l disk drive will not be used because the maximum number of physical disk drives already exist in the current Storage System. Event Code: 0303000a Severity: Normal -- informational in nature. An HSV450 controller has begun boot ing. Event Code: 0304000a Severity: Normal -- informational in nature. An HSV450 controller has finished t he process of bringing the Storage System online. Event Code: 0305000a Severity: Normal -- informational in nature. An HSV450 controller has been joine d into the Storage System. Event Code: 0306000a Severity: Normal -- informational in nature. An HSV450 controller has been ouste d from the Storage System. Event Code: 0307000a Severity: Normal -- informational in nature. An HSV450 controller is now the Sto rage System Master. Event Code: 0308000a Severity: Normal -- informational in nature. An HSV450 controller has been broug ht into the Storage System. Event Code: 03090018 Severity: Normal -- informational in nature. The Redundant Storage Set has start ed migrating members. Event Code: 030a0018 Severity: Normal -- informational in nature. The Redundant Storage Set has finis hed migrating members. Event Code: 030b4f0b Severity: Warning -- not failed but attention recommended or required. A physica

l disk drive has failed during Storage System realization. Event Code: 030c001e Severity: Normal -- informational in nature. The DebugFlags and/or PrintFlags ha ve changed. Event Code: 030d001e Severity: Normal -- informational in nature. Process with work during CSM reset: Event Code: 030e070b Severity: Warning -- not failed but attention recommended or required. About to write ID block to wrong physical disk drive. Event Code: 030f001e Severity: Normal -- informational in nature. RoHS Status of the HSV450 controlle r has been determined. Event Code: 0310001f Severity: Normal -- informational in nature. A Storage System Virtual Disk has c hanged controller mastership. Event Code: 03114420 Severity: Critical -- failure or failure imminent. A Fibre Channel Switch respon ded to a fabric port login. The corresponding device Fibre Channel port on the s pecified HSV450 controller has been failed. Event Code: 03120021 Severity: Normal -- informational in nature. A Storage System Virtual Disk Attac h operation has completed. Event Code: 03130021 Severity: Normal -- informational in nature. A Snapclone Storage System Virtual Disk has completed the Unsharing operation. Event Code: 03140021 Severity: Normal -- informational in nature. A Mirror Clone Storage System Virtu al Disk has completed the detach operation. Event Code: 03150021 Severity: Normal -- informational in nature. A Mirror Clone Storage System Virtu al Disk has completed the Fracture operation. Event Code: 03160021 Severity: Normal -- informational in nature. A Mirror Clone Storage System Virtu al Disk has completed the Synchronization operation. Event Code: 03170021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has c ompleted the Instant Restore operation. Event Code: 03189513 Severity: Warning -- not failed but attention recommended or required. An Enclos ure Failed to initialize. Event Code: 0319000a Severity: Normal -- informational in nature. An HSV450 controller has begun disc overing devices on the backend loops. Event Code: 031a000a Severity: Normal -- informational in nature. An HSV450 controller has completed

discovering devices on the backend loops. Event Code: 031b0d23 Severity: Critical -- failure or failure imminent. The system is inoperative. Event Code: 031c4a23 Severity: Warning -- not failed but attention recommended or required. One or mo re ports has been disabled at startup. Event Code: 031d9923 Severity: Critical -- failure or failure imminent. One or more ports have been m isconfigured. Event Code: 031e0d23 Severity: Critical -- failure or failure imminent. The user is required to provi de a confirmation as to how the system should proceed. Event Code: 031f9923 Severity: Critical -- failure or failure imminent. A backend device has been mis configured. The current port states for both the master and the slave should ma tch. Event Code: 0320000a Severity: Normal -- informational in nature. The slave HSV450 controller is prev ented from joining because there are units still completing fast failover. Event Code: 0321f113 Severity: Warning -- not failed but attention recommended or required. An enclos ure will not be used because the maximum number of enclosures already exist in t he current Storage System. Event Code: 0322000f Severity: Normal -- informational in nature. The CA Port Routing value has been changed. Event Code: 0323000a Severity: Normal -- informational in nature. An HSV450 controller has successful ly completed a preserving resync after a code load operation. Event Code: 0324400b Severity: Critical -- failure or failure imminent. A physical disk drive could n ot be added to a SCELL. The device storage capacity exceeds the maximum supporte d size. Event Code: 0325000a Severity: Normal -- informational in nature. Drive reappeared with Metadata (ID buffer) Scell tag matching with deleted scell, erasing ID BLOCK. Event Code: 03260027 Severity: Normal -- informational in nature. An HSV450 controller has changed Ba ttery Cache policy Event Code: 03270129 Severity: Critical -- failure or failure imminent. A physical disk drive has exp erienced an ID block inconsistency. Event Code: 03280029 Severity: Normal -- informational in nature. A physical disk drive has experienc ed an ID block inconsistency during a periodic drive check.

Event Code: 0329002a Severity: Normal -- informational in nature. An update to the CVM data base was successfully recovered. Event Code: 032a0018 Severity: Normal -- informational in nature. The Redundant Storage Set failed to start migrating members due to insufficient capacity. Event Code: 0330000a Severity: Normal -- informational in nature. A request to scrub the Storage Syst em has been received. Event Code: 0331000a Severity: Normal -- informational in nature. The Storage System has been scrubbe d. Event Code: 0332000a Severity: Normal -- informational in nature. An invalid request to scrub the Sto rage System has been ignored. Event Code: 03400021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has c ompleted the Cache Fast Failover operation. Event Code: 03410021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has c ompleted the Clear Container operation. Event Code: 03420021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has r emoved any sharing relationships (if any existed ) during the delete process. Event Code: 03430021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has c ompleted the Set Capacity operation. Event Code: 03440021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has c ompleted the Reserve Capacity operation. Event Code: 03450021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has c ompleted the Cache Flush operation. Event Code: 03600021 Severity: Normal -- informational in nature. A Logical Disk operation has comple ted. Event Code: 0400031c Severity: Undetermined -- more information needed to determine severity. HSV450 controller operation was terminated due to an unrecoverable event detected by ei ther software or hardware or due to an action initiated via the Storage System M anagement Interface. Event Code: 0401031c Severity: Undetermined -- more information needed to determine severity. This HS V450 controller has received a last gasp message from another HSV450 controller prior to it terminating operation. Event Code: 04020101

Severity: Critical -- failure or failure imminent. A machine check occurred whil e a termination event was being processed. Event Code: 04030102 Severity: Critical -- failure or failure imminent. An unexpected event occurred while a termination event was being processed. Event Code: 04040003 Severity: Normal -- informational in nature. The Storage System Event Log valida tion completed successfully. Event Code: 04050003 Severity: Normal -- informational in nature. The Storage System Event Log valida tion failed. Event Code: 04060803 Severity: Normal -- informational in nature. Local event reports were lost due t o an insufficient supply of Event Log Packets on this HSV450 controller. Event Code: 04070803 Severity: Normal -- informational in nature. Remote event reports were lost due to an insufficient supply of Event Log Packets on this HSV450 controller. Event Code: 04080003 Severity: Normal -- informational in nature. The Storage System Termination Even t Log has become inaccessible. Event Code: 04090003 Severity: Normal -- informational in nature. The Storage System Termination Even t Log validation completed successfully. Event Code: 040a0003 Severity: Normal -- informational in nature. The Storage System Termination Even t Log validation failed. Event Code: 040b0003 Severity: Normal -- informational in nature. The Storage System Termination Even t Log has been updated with the termination event information obtained from the HSV450 controller that is not the Storage System Master. Event Code: 040c0803 Severity: Normal -- informational in nature. The Fault Manager on the Storage Sy stem Master received an invalid Event Information Packet from the remote Fault M anager. Event Code: 040d0003 Severity: Normal -- informational in nature. The Fault Manager operation was mad e quiescent. Event Code: 040e031c Severity: Undetermined -- more information needed to determine severity. An HSV4 50 controller sent a last gasp message prior to terminating operation with an in dication that both HSV450 controllers should terminate operation. Event Code: 040f0003 Severity: Normal -- informational in nature. This HSV450 controller sent its ter mination event information to the HSV450 controller that is the Storage System M aster. Event Code: 04100803

Severity: Normal -- informational in nature. Event reports were lost due to an i nsufficient supply of ISR Event Log Packets on the HSV450 controller that is the Storage System Master. Event Code: 04110803 Severity: Normal -- informational in nature. Event reports were lost due to an i nsufficient supply of ISR Event Log Packets on the HSV450 controller that is not the Storage System Master. Event Code: 04120003 Severity: Normal -- informational in nature. The last event reporting interval h as changed or last event reporting has been enabled or disabled. Event Code: 04130003 Severity: Normal -- informational in nature. Storage System event reporting is s till active. Event Code: 0414031d Severity: Undetermined -- more information needed to determine severity. HSV450 controller operation was terminated due to an unrecoverable event detected by ei ther software or hardware or due to an action initiated via the Storage System M anagement Interface. Event Code: 0415031d Severity: Undetermined -- more information needed to determine severity. This HS V450 controller has received a last gasp message from another HSV450 controller prior to it terminating operation. Event Code: 0416031d Severity: Undetermined -- more information needed to determine severity. An HSV4 50 controller sent a last gasp message prior to terminating operation with an in dication that both HSV450 controllers should terminate operation. Event Code: 04180003 Severity: Normal -- informational in nature. The Manufacturing Event Analysis Lo g validation completed successfully. Event Code: 04190003 Severity: Normal -- informational in nature. The Manufacturing Event Analysis Lo g validation failed. Event Code: 041a031c Severity: Undetermined -- more information needed to determine severity. An erro r condition was encountered while this HSV450 controller's Last Termination Even t information was being processed. Event Code: 041b031d Severity: Undetermined -- more information needed to determine severity. An erro r condition was encountered while this HSV450 controller's Last Termination Even t information was being processed. Event Code: 06000009 Severity: Normal -- informational in nature. A physical disk drive has reported that it has exceeded its failure prediction threshold. Event Code: 06014a08 Severity: Warning -- not failed but attention recommended or required. A Fibre C hannel port on the HSV450 controller has failed to respond. Event Code: 06020009

Severity: Normal -- informational in nature. A physical disk drive or an Enclosu re Link Module has reported a check condition error. Event Code: 06034713 Severity: Warning -- not failed but attention recommended or required. An exchan ge sent to a physical disk drive or another HSV450 controller via the mirror por t or a Fibre Channel port has timed out. Event Code: 06044812 Severity: Warning -- not failed but attention recommended or required. Work was unexpectedly sent to this HSV450 controller by a physical disk drive or another HSV450 controller. Event Code: 06054909 Severity: Warning -- not failed but attention recommended or required. Work has been sent to a physical disk drive or another HSV450 controller via the mirror p ort but it did not respond. Event Code: 06074709 Severity: Warning -- not failed but attention recommended or required. A Target Discovery Service Descriptor exchange sent to a physical disk drive has timed ou t. Event Code: 06080007 Severity: Normal -- informational in nature. An excessive number of link errors were detected on a HSV450 controller's Fibre Channel port. This informational ev ent is triggered by the occurrence of an excessive number of Tachyon chip link s tatus errors detected within a particular link status error type. Event Code: 06090013 Severity: Normal -- informational in nature. A physical disk drive has reported numerous failure prediction threshold exceeded errors. Event Code: 060a0013 Severity: Normal -- informational in nature. A physical disk drive has reported numerous check condition errors. Event Code: 060b4709 Severity: Warning -- not failed but attention recommended or required. A non-dat a exchange sent to a physical disk drive has timed out. Event Code: 060c0013 Severity: Normal -- informational in nature. A loop switch has been detected on a Fibre Channel port. Event Code: 061a0009 Severity: Normal -- informational in nature. A physical disk drive has exceeded its soft error threshold. Event Code: 061c4709 Severity: Warning -- not failed but attention recommended or required. An outbou nd frame targeted to a physical disk drive has timed out. Event Code: 061d4709 Severity: Warning -- not failed but attention recommended or required. A Fibre C hannel exchange to a physical disk drive has been retried. Event Code: 061e4c13 Severity: Critical -- failure or failure imminent. An HSV450 controller has dete cted only one port of a Fibre Channel device.

Event Code: 061f0013 Severity: Normal -- informational in nature. A previously reported Fibre Channel device with only one port has been corrected and redundancy has been restored. Event Code: 06204013 Severity: Critical -- failure or failure imminent. An unsupported Fibre Channel device has been detected. The device has been failed to prevent possible data co rruption or system instability. Event Code: 06210013 Severity: Normal -- informational in nature. A Fibre Channel device with incorre ct block size has been detected. Event Code: 06230013 Severity: Normal -- informational in nature. An HSV450 controller is about to re try a failed port. Event Code: 06280008 Severity: Normal -- informational in nature. The retry count for an OB task assi gned to a Drive Enclosure Environmental Monitoring Unit has been exhausted. Event Code: 06290009 Severity: Normal -- informational in nature. The HSV450 controller has sent a Ba sic Link Service command Abort Sequence Frame. Event Code: 062a0009 Severity: Normal -- informational in nature. The HSV450 controller has sent an E xtended Link Service command Reinstate Recovery Qualifier. Event Code: 062c0012 Severity: Normal -- informational in nature. One or more media defects were dete cted on a physical disk drive. Event Code: 062d0012 Severity: Normal -- informational in nature. An HSV450 controller issued a direc ted LIP to an arbitrated loop physical address. Event Code: 062e0012 Severity: Normal -- informational in nature. An HSV450 controller has detected l oop receiver failures. Event Code: 06304e13 Severity: Critical -- failure or failure imminent. An HSV450 controller has dete cted only one port of all Fibre Channel devices in an enclosure. Event Code: 06310013 Severity: Normal -- informational in nature. A previously reported Fibre Channel device enclosure with only one port has been corrected and redundancy has been restored. Event Code: 06324e13 Severity: Critical -- failure or failure imminent. An HSV450 controller has dete cted only one port of all Fibre Channel devices on a loop. Event Code: 06330013 Severity: Normal -- informational in nature. A previously reported Fibre Channel loop with only one port has been corrected and redundancy has been restored. Event Code: 06340013

Severity: Normal -- informational in nature. An HSV450 controller has been told to enable a device port, and that device port was not disabled during boot diagn ostics. Event Code: 06364d04 Severity: Critical -- failure or failure imminent. An unsupported Fibre Channel physical disk drive firmware revision has been detected by the physical disk dri ve firmware load process. Event Code: 0637c404 Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware revision has been detected by the physical disk drive firmware load pr ocess that is later than the latest known supported revision. Event Code: 0638c404 Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware revision has been detected by the physical disk drive firmware load pr ocess that has a newer supported revision available. Event Code: 06394008 Severity: Critical -- failure or failure imminent. The HSV450 controller bypasse d a device bay in an attempt to restore loop operability. Replace this drive onl y if the Loop Recovery algorithm did not abort. Event Code: 063a0008 Severity: Normal -- informational in nature. The HSV450 controller is attempting to recover devices on the indicated ports. Event Code: 063b0008 Severity: Normal -- informational in nature. The HSV450 controller has finished error recovery attempts on the indicated ports. Event Code: 063c0008 Severity: Normal -- informational in nature. The HSV450 controller been requeste d to unbypass device bays on the indicated port. Loop recovery incomplete. Event Code: 06404d04 Severity: Critical -- failure or failure imminent. A Fibre Channel physical disk drive that has new capabilities has been detected. The physical disk drive has properties that may or may not be compatible with this release of Enterprise Vir tual Array firmware -- the drive will be prevented from being used until the App roved Drive Firmware table has been updated to allow it. Event Code: 06410017 Severity: Normal -- informational in nature. The device loop configuration has c hanged on a HSV450 controller's Fibre Channel port. This informational event con tains a page of the newly genereated fibre channel loop map. Devices are listed in loop order using their ALPAs. Event Code: 06420009 Severity: Normal -- informational in nature. A user command has been sent to a p hysical disk drive. Event Code: 06440008 Severity: Normal -- informational in nature. An HSV450 controller is evaluating the next drive enclosure in the Loop Recovery Process. Event Code: 064b0008 Severity: Normal -- informational in nature. The HSV450 controller has been inst ructed to Enable or Disable Loop Recovery Operations.

Event Code: 064c0004 Severity: Normal -- informational in nature. Device Fibre Channel physical disk drive was placed on the Drive Suspect List (DSL) Look at events around this one to help determine what has happened. Fibre Channel port number used to communica te with the physical disk drive is contained in the port field. The arbitrated l oop physical address of the physical disk drive is contained in the al_pa field. Note that the content of the rack_num field will not be valid until Event Code: 064d0008 Severity: Normal -- informational in nature. The HSV450 controller has finished attempts to codeload all Drive Enclosure Environmental Monitoring Unit hardware requiring updates, and has completed staggered codeload if necessary. Event Code: 064e0009 Severity: Normal -- informational in nature. A physical disk drive has reported a non-zero RSP_CODE. in response to an I/O. This is not interesting by itself, a s the I/O will be retried if retries remain and are allowed for the particular t ype of I/O. Event Code: 064f0006 Severity: Normal -- informational in nature. An Enclosure Link Module has begun updating its code. Do not power down the Enclosure until the code update has com pleted. Event Code: 06500006 Severity: Normal -- informational in nature. An Enclosure Link Module has comple ted updating its code. It is now safe to power down the Enclosure. Event Code: 06510006 Severity: Normal -- informational in nature. A HSV450 controller has sent a SES control page to the Enclosure Link Module in the Enclosure for drive bay bypass control. Event Code: 06520006 Severity: Normal -- informational in nature. A HSV450 controller has sent a SES control page to the Enclosure Link Module in the Enclosure for drive bay power c ontrol. Event Code: 06530006 Severity: Normal -- informational in nature. A HSV450 controller has sent a SES control page to the Enclosure Link Module in the Enclosure to change the enclosu re ID number. Event Code: 06540006 Severity: Normal -- informational in nature. A HSV450 controller has discovered an Enclosure and is allocating resources for it. Event Code: 06558906 Severity: Critical -- failure or failure imminent. An Enclosure Link Module has been failed, and can no longer be used to detect drive position information, or to issue bypass/unbypass commands. Event Code: 06560006 Severity: Normal -- informational in nature. A HSV450 controller has sent a SES control page to the Enclosure Link Module in the Enclosure to shutdown the drive enclosure. Event Code: 06570006 Severity: Normal -- informational in nature. A HSV450 controller has detected an

inconsistency in the enclosure ID numbers reported by the Enclosure Link Module s in the in the Enclosure. Event Code: 06589906 Severity: Critical -- failure or failure imminent. A HSV450 controller has detec ted a potential cabling error. The Enclosure Link Module in the Enclosure is rep orting it is conencted to the wrong Fibre Channel port. Event Code: 06590006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in a physical disk drive bay condition in a Enclosure Event Code: 065a0006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in a Enclosure condition. Event Code: 065b0006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in a Enclosure power supply condition. Event Code: 065c0006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in a Enclosure fan module 1 condition. Event Code: 065d0006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in a Enclosure fan module 2 condition. Event Code: 065e0006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure A-side link module's condition. Event Code: 065f0006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure B-side link module's condition. Event Code: 06600006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure A-side link module's transceiver condition. Event Code: 06610006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure B-side link module's transceiver condition. Event Code: 06620006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure A-side link module alphanumeric display. Event Code: 06630006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure B-side link module alphanumeric display. Event Code: 06640006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure A-side link module temperature sensor. Event Code: 06650006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure B-side link module temperature sensor.

Event Code: 06660006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure midplane condition. Event Code: 06670006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure midplane temperature sensor condition. Event Code: 06684c13 Severity: Critical -- failure or failure imminent. An HSV450 controller has dete cted only one port of a Enclosure device. Event Code: 06690013 Severity: Normal -- informational in nature. A previously reported Enclosure dev ice with only one port has been corrected and redundancy has been restored. Event Code: 066a0028 Severity: Normal -- informational in nature. A Back-end Fibre Channel Port trans itioned to link up or link down. The corresponding device Fibre Channel port on the specified HSV450 controller has transitioned to a link up or link down state . Event Code: 066b0028 Severity: Normal -- informational in nature. A Back-end Fibre Channel Port is in the STO (State TimeOut) state, The corresponding device Fibre Channel port on t he specified HSV450 controller has its loop port state machine hung up for 2 sec . Event Code: 066c0008 Severity: Normal -- informational in nature. The HSV450 controller has finished codeloads to all Enclosure hardware requiring updates. Event Code: 066df308 Severity: Critical -- failure or failure imminent. The HSV450 controller cannot continue to codeload any Enclosure hardware requiring updates until backend redu ndancy is restored. Event Code: 066e0008 Severity: Normal -- informational in nature. The HSV450 controller has cleared a ny previous issues blocking codeload of any Enclosure hardware requiring updates Enclosure codeload operations will now continue Event Code: 066f0009 Severity: Normal -- informational in nature. One or more Fibre Channel devices h ave taken too long to complete the PRLI login phase in the allowed time. Event Code: 06700009 Severity: Normal -- informational in nature. One or more Fibre Channel devices h ave taken too long to complete the PLOGI login phase in the allowed time. Event Code: 0671f406 Severity: Critical -- failure or failure imminent. A HSV450 controller has detec ted a critical condition for a Disk Enclosure Power Supply. This often implies a loss in power to the Disk Enclosure Power Supply, causing a loss of redundancy in power to the Disk Enclosure. Event Code: 0700b515 Severity: Warning -- not failed but attention recommended or required. Allocatio n of a Virtual Disk has stalled due to insufficient space in the Disk Group caus ed by the failure or pulling of a physical disk drive.

Event Code: 0701b515 Severity: Warning -- not failed but attention recommended or required. Expansion of a Virtual Disk has stalled due to insufficient space in the Disk Group cause d by the failure or pulling of a physical disk drive. Event Code: 07020015 Severity: Normal -- informational in nature. Leveling of capacity in a Disk Grou p has started. Event Code: 07030015 Severity: Normal -- informational in nature. Leveling of capacity in a Disk Grou p has finished. Event Code: 07040015 Severity: Normal -- informational in nature. A member management operation has s tarted due to the appearance or disappearance of a physical disk drive. Event Code: 07050015 Severity: Normal -- informational in nature. A member management operation has f inished. Event Code: 07060015 Severity: Normal -- informational in nature. A Disk Group has started changing i ts internal structure due to the appearance or disappearance of a Volume. Event Code: 07070015 Severity: Normal -- informational in nature. A Disk Group has finished changing its internal structure due to the appearance or disappearance of a Volume. Event Code: 07080015 Severity: Normal -- informational in nature. Deallocation of a Virtual Disk has failed after three attempts due to unknown circumstances. This will more than l ikely be caused by failing physical drives. The deletion will be restarted when a resync/reboot occurs. Event Code: 0709b515 Severity: Warning -- not failed but attention recommended or required. A member management operation has stalled due to insufficient space in the Disk Group. Event Code: 070a0015 Severity: Normal -- informational in nature. A stalled member management operati on is being restarted. Event Code: 070d0015 Severity: Normal -- informational in nature. A member management operation encou nter an error while processing a Logical Disk. Processing on this logical disk will be retried again. Event Code: 070e0015 Severity: Normal -- informational in nature. An range of ebits were set or clear ed for a Logical Disk. A read of an LBA that has an ebit set will return MEDIA E RROR. A write to an LBA that has an ebit set will write the data and clear the e bit. Event Code: 070f0015 Severity: Normal -- informational in nature. A member management operation has r etried or waited too long Event Code: 07110015

Severity: Normal -- informational in nature. A Disk Group experienced an unexpec ted error during leveling or Redundant Storage Set migration and will be retried for the affected Virtual Disk. Event Code: 07120015 Severity: Normal -- informational in nature. A Virtual Disk experienced an unexp ected error during a migration operation and will be retried for the affected Di sk Group. Event Code: 07130715 Severity: Warning -- not failed but attention recommended or required. Metadata Check 0. Event Code: 07140715 Severity: Warning -- not failed but attention recommended or required. Metadata Check 1. Event Code: 07150015 Severity: Normal -- informational in nature. A Virtual Disk Expand or Shrink ope ration failed. Event Code: 09010005 Severity: Normal -- informational in nature. A physical disk drive has transitio ned to the NORMAL state. Event Code: 09020005 Severity: Normal -- informational in nature. The state of a Volume has changed. Event Code: 09040005 Severity: Normal -- informational in nature. An HSV450 controller has transition ed to the NORMAL state because the system is no longer inoperative. Event Code: 09050005 Severity: Normal -- informational in nature. The state of a battery assembly has changed. Event Code: 0906bf05 Severity: Undetermined -- more information needed to determine severity. A Volum e has transitioned to the MISSING state. Event Code: 09070005 Severity: Normal -- informational in nature. A Fibre Channel port has transition ed to the NORMAL state. Event Code: 0908b405 Severity: Warning -- not failed but attention recommended or required. A Disk Gr oup's occupancy alarm level threshold has been reached. Event Code: 09090005 Severity: Normal -- informational in nature. The resource availability state of a Volume has transitioned to the SUFFICIENT state. Event Code: 090c0005 Severity: Normal -- informational in nature. A snapclone Logical Disk has comple ted the unsharing operation. Event Code: 090d0005 Severity: Normal -- informational in nature. The state of the quorum disk flag o f a Volume has changed.

Event Code: 090e3605 Severity: Critical -- failure or failure imminent. The temperature trip point fo r a temperature sensor located within an HSV450 controller has been reached. Event Code: 090f2e05 Severity: Warning -- not failed but attention recommended or required. The tempe rature within an HSV450 controller is approaching its trip point. Event Code: 09110005 Severity: Normal -- informational in nature. An HSV450 controller's blower '1' i s now present. Event Code: 09122405 Severity: Critical -- failure or failure imminent. An HSV450 controller's blower '1' is running slower than the lowest acceptable speed. Event Code: 09132005 Severity: Critical -- failure or failure imminent. A voltage sensor has reported a voltage that is out of range. Event Code: 0914bf05 Severity: Undetermined -- more information needed to determine severity. A Volum e has transitioned to the FAILED state. Event Code: 0915b905 Severity: Undetermined -- more information needed to determine severity. An HSV4 50 controller has failed, as a result of the system becoming inoperative. Relate d events have more information. Event Code: 09160005 Severity: Normal -- informational in nature. The temperature within an HSV450 co ntroller has returned to its normal operating range. Event Code: 09172805 Severity: Critical -- failure or failure imminent. An HSV450 controller's batter y assembly '1' has been removed. Event Code: 09180005 Severity: Normal -- informational in nature. An HSV450 controller's battery asse mbly '1' is now in use. Event Code: 09190005 Severity: Normal -- informational in nature. A voltage sensor has returned to a normal range. Event Code: 091a2005 Severity: Critical -- failure or failure imminent. The battery assembly voltage regulator located within an HSV450 controller is offline. Event Code: 091b0005 Severity: Normal -- informational in nature. A Disk Group has transitioned to th e NORMAL state. Event Code: 091c0005 Severity: Normal -- informational in nature. The occupancy alarm level for a Dis k Group has returned to the normal range. Event Code: 091d2205 Severity: Critical -- failure or failure imminent. An HSV450 controller's batter y assembly '1' has malfunctioned.

Event Code: 091e0005 Severity: Normal -- informational in nature. An HSV450 controller's battery asse mbly '1' is now present. Event Code: 091f2905 Severity: Critical -- failure or failure imminent. An HSV450 controller's batter y assembly '2' has been removed. Event Code: 09200005 Severity: Normal -- informational in nature. An HSV450 controller's battery asse mbly '2' is now present. Event Code: 09210005 Severity: Normal -- informational in nature. An HSV450 controller's battery asse mbly '2' is now functioning properly. Event Code: 09222305 Severity: Critical -- failure or failure imminent. An HSV450 controller's batter y assembly has malfunctioned. Event Code: 09232b05 Severity: Critical -- failure or failure imminent. An HSV450 controller's blower '2' has been removed. Event Code: 09240005 Severity: Normal -- informational in nature. An HSV450 controller's blower assem bly '2' is now present. Event Code: 09252505 Severity: Critical -- failure or failure imminent. An HSV450 controller's blower assembly '2' is running slower than the lowest acceptable speed. Event Code: 09262c05 Severity: Critical -- failure or failure imminent. An HSV450 controller's '1' bl ower/power supply assembly has been removed or AC power has been removed from th e power supply. Event Code: 09270005 Severity: Normal -- informational in nature. An HSV450 controller's '1' blower/p ower supply assembly has been reinstalled or AC power has been restored to the p ower supply. Event Code: 09282d05 Severity: Critical -- failure or failure imminent. An HSV450 controller's '2' bl ower/power supply assembly has been removed or AC power has been removed from th e power supply. Event Code: 09290005 Severity: Normal -- informational in nature. An HSV450 controller's '2' blower/p ower supply assembly has been reinstalled or AC power has been restored to the p ower supply. Event Code: 092a2605 Severity: Critical -- failure or failure imminent. An HSV450 controller's '1' bl ower/power supply is running slower than the lowest acceptable speed. Event Code: 092b2705 Severity: Critical -- failure or failure imminent. An HSV450 controller's '2' bl ower/power supply is running slower than the lowest acceptable speed.

Event Code: 092c2f05 Severity: Warning -- not failed but attention recommended or required. An HSV450 controller's battery assembly has transitioned to the 'Battery System Hold-up T ime is zero hours' state. Event Code: 092dbf05 Severity: Undetermined -- more information needed to determine severity. The res ource availability state of a Volume has transitioned to the INSUFFICIENT state. Event Code: 092e0005 Severity: Normal -- informational in nature. An HSV450 controller has rejected a login attempt. Event Code: 092f0005 Severity: Normal -- informational in nature. An HSV450 controller has processed a Storage System Management Interface command with the result of non-success ret urn code. Event Code: 09300005 Severity: Normal -- informational in nature. An HSV450 controller has updated th e physical disk drive map for a loop pair. Event Code: 09314205 Severity: Critical -- failure or failure imminent. A physical disk drive has tra nsitioned to the DEGRADED state. Event Code: 09324005 Severity: Critical -- failure or failure imminent. A physical disk drive has tra nsitioned to the FAILED state. Event Code: 0935000e Severity: Normal -- informational in nature. A Disk Group was created. Event Code: 0936000e Severity: Normal -- informational in nature. A physical disk drive was discovere d. Event Code: 0937000e Severity: Normal -- informational in nature. A Presented Unit was created. Event Code: 0938000e Severity: Normal -- informational in nature. A Storage System Host Path was crea ted. Event Code: 0939000e Severity: Normal -- informational in nature. A Storage System Virtual Disk was c reated. Event Code: 093a000e Severity: Normal -- informational in nature. A Volume was created. Event Code: 093d000e Severity: Normal -- informational in nature. A Disk Group was deleted. Event Code: 093e420e Severity: Critical -- failure or failure imminent. A physical disk drive has dis appeared. Event Code: 093f000e

Severity: Normal -- informational in nature. A Presented Unit was deleted. Event Code: 0940000e Severity: Normal -- informational in nature. A Storage System Host Path was dele ted. Event Code: 0941000e Severity: Normal -- informational in nature. A Storage System Virtual Disk was d eleted. Event Code: 0943000e Severity: Normal -- informational in nature. An HSV450 controller has joined the Storage System. Event Code: 0944ba0e Severity: Undetermined -- more information needed to determine severity. An HSV4 50 controller has left the Storage System. Event Code: 0945000e Severity: Normal -- informational in nature. The Storage System has been deleted by an HSV450 controller. Event Code: 0946000e Severity: Normal -- informational in nature. A Data Replication Group was create d. Event Code: 0947000e Severity: Normal -- informational in nature. A Data Replication Group was delete d. Event Code: 0948000e Severity: Normal -- informational in nature. A Snapshot Storage System Virtual D isk was created. Event Code: 0949000e Severity: Normal -- informational in nature. A Clone Storage System Virtual Disk was created. Event Code: 094a000e Severity: Normal -- informational in nature. Destination Data Replication Group not deleted due to inoperative members. Event Code: 094b000e Severity: Normal -- informational in nature. A Volume was removed from a LDAD. Event Code: 094c000e Severity: Normal -- informational in nature. A new Remote Node has been discover ed. Event Code: 094d000e Severity: Normal -- informational in nature. The Remote Node object has been dis carded. Event Code: 094e000e Severity: Normal -- informational in nature. The Remote Node Storage System UUID has changed. Event Code: 094f000e Severity: Normal -- informational in nature. An Enclosure Appeared.

Event Code: 0950000e Severity: Normal -- informational in nature. An Enclosure Disappeared. Event Code: 0951000e Severity: Normal -- informational in nature. An IO Module Appeared. Event Code: 0952000e Severity: Normal -- informational in nature. An IO Module Disappeared. Event Code: 0965000f Severity: Normal -- informational in nature. A host operating system mode has ch anged. Event Code: 0966000f Severity: Normal -- informational in nature. Time was set on a Storage System. Event Code: 0967000f Severity: Normal -- informational in nature. The LUN of a Presented Unit has cha nged. Event Code: 0968000f Severity: Normal -- informational in nature. The device addition policy of a Sto rage System has changed. Event Code: 0969000f Severity: Normal -- informational in nature. The quiescent state of a Storage Sy stem Virtual Disk has changed. Event Code: 096a000f Severity: Normal -- informational in nature. The enabled/disabled state of a Sto rage System Virtual Disk has changed. Event Code: 096b000f Severity: Normal -- informational in nature. The cache policy of a Storage Syste m Virtual Disk has changed. Event Code: 096c000f Severity: Normal -- informational in nature. The usage state of a Volume changed . Event Code: 096d000f Severity: Normal -- informational in nature. The disk failure protection level o f a Disk Group has changed. Event Code: 096e000f Severity: Normal -- informational in nature. The write protected state of a Stor age System Virtual Disk has changed. Event Code: 0970460f Severity: Warning -- not failed but attention recommended or required. A HSV450 controller has declared a port on a physical disk drive unusable and will not lo g in to the device on that port due to numerous transport failures. Event Code: 0971000f Severity: Normal -- informational in nature. An HSV450 controller has received a request to shutdown. Event Code: 0972000f Severity: Normal -- informational in nature. An HSV450 controller has completed its shutdown preparations.

Event Code: 0973000f Severity: Normal -- informational in nature. The failsafe state of a Data Replic ation Group has changed. Event Code: 0974000f Severity: Normal -- informational in nature. The mode of a Data Replication Grou p has changed. Event Code: 0975000f Severity: Normal -- informational in nature. The synchronous/asynchronous operat ional state of a Data Replication Group has changed. Event Code: 0976000f Severity: Normal -- informational in nature. The read only attribute of a Data R eplication Group has changed. Event Code: 0977000f Severity: Normal -- informational in nature. A Data Replication Group failover h as occurred. Event Code: 0978000f Severity: Normal -- informational in nature. A Data Replication Group has been s uspended or resumed. Event Code: 0979000f Severity: Normal -- informational in nature. A Storage System Virtual Disk was a dded to a Data Replication Group. Event Code: 097a000f Severity: Normal -- informational in nature. A Storage System Virtual Disk was r emoved from a Data Replication Group. Event Code: 097b000f Severity: Normal -- informational in nature. The auto suspend attribute of a Dat a Replication Group has changed. Event Code: 097c000f Severity: Normal -- informational in nature. The destination presentation attrib ute of a Data Replication Group has changed. Event Code: 097d000f Severity: Normal -- informational in nature. The flags of a physical disk drive have changed because of a maintenance mode change. Event Code: 097e000f Severity: Normal -- informational in nature. The defer_copy attribute of a Data Replication Group has changed. Event Code: 097f000f Severity: Normal -- informational in nature. A Data Replication Group has been s uspended due to link down. Event Code: 0980000f Severity: Normal -- informational in nature. A Data Replication Group has been s uspended due to site failover. Event Code: 0981000f Severity: Normal -- informational in nature. A Data Replication Group has been s uspended due to defer copy.

Event Code: 0982000f Severity: Normal -- informational in nature. The split brain allow attribute of a Data Replication Group has changed. Event Code: 0983000f Severity: Normal -- informational in nature. A Data Replication Group has been s uspended due to instance restore on destination site. Event Code: 09c95105 Severity: Undetermined -- more information needed to determine severity. A Disk Group has transitioned to an INOPERATIVE state. Event Code: 09ca5105 Severity: Undetermined -- more information needed to determine severity. A Stora ge System Virtual Disk has transitioned to the FAILED state. Event Code: 09cb5005 Severity: Critical -- failure or failure imminent. A Storage System Virtual Disk has transitioned to the SNAPSHOT OVERCOMMIT state. Event Code: 09cc5105 Severity: Undetermined -- more information needed to determine severity. A Stora ge System Virtual Disk has transitioned to the DEVICE DATA LOST state. Event Code: 09cdc305 Severity: Undetermined -- more information needed to determine severity. A Fibre Channel port has transitioned to the FAILED state. Event Code: 09ce0005 Severity: Normal -- informational in nature. A Disk Group has transitioned to an INOPERATIVE MARKED state. Event Code: 09cf4105 Severity: Warning -- not failed but attention recommended or required. A physica l disk drive has transitioned to the NOT PRESENT state. Event Code: 09d00005 Severity: Normal -- informational in nature. An HSV450 controller no longer need s attention. Event Code: 09d1b905 Severity: Undetermined -- more information needed to determine severity. An HSV4 50 controller needs attention. Event Code: 09d22a05 Severity: Critical -- failure or failure imminent. An HSV450 controller's blower '1' has been removed. Event Code: 09d35105 Severity: Undetermined -- more information needed to determine severity. At leas t one Storage System Virtual Disk associated with a Data Replication Group has t ransitioned to the INOPERATIVE state. The remaining Storage System Virtual Disks associated with this Data Replication Group have been forced INOPERATIVE. Event Code: 09d40005 Severity: Normal -- informational in nature. All the Virtual Disks associated wi th a Data Replication Group have transitioned to the OPERATIVE state. Event Code: 09d50005

Severity: Normal -- informational in nature. The state of a physical disk drive has transitioned to the Single Port on Fibre state. Event Code: 09d63705 Severity: Warning -- not failed but attention recommended or required. An HSV450 controller has been powered off because the temperature sensors do not agree an d the system temperature can not be accurately determined. Event Code: 09d73705 Severity: Warning -- not failed but attention recommended or required. An HSV450 controller has been powered off because the temperature sensors can not be acce ssed and the system temperature can not be accurately determined. Event Code: 09d8b605 Severity: Undetermined -- more information needed to determine severity. A Redun dant Storage Set has two members on the same Fibre Channel device enclosure caus ing a Disk Group to lose its Single Point of Failure Robust Configuration. Event Code: 09d90005 Severity: Normal -- informational in nature. A Disk Group has attained a Single Point of Failure Robust Configuration. Event Code: 09da0005 Severity: Normal -- informational in nature. An HSV450 controller's blower '1' i s running at normal speed. Event Code: 09db0005 Severity: Normal -- informational in nature. An HSV450 controller's blower '2' i s running at normal speed. Event Code: 09dd0005 Severity: Normal -- informational in nature. An HSV450 controller receives a mai ntenance invoke call from the user Event Code: 09de5205 Severity: Critical -- failure or failure imminent. A Storage System Virtual Disk has transitioned to the INVALIDATED state. Event Code: 09e30005 Severity: Normal -- informational in nature. The state of a Storage System Virtu al Disk has changed. Event Code: 09e45105 Severity: Undetermined -- more information needed to determine severity. The dat a availability state of a Storage System Virtual Disk has transitioned to the DA TA LOST state. Event Code: 09e50005 Severity: Normal -- informational in nature. The data availability state of a St orage System Virtual Disk has transitioned to the NORMAL state. Event Code: 0b000010 Severity: Normal -- informational in nature. An HSV450 controller has begun a re synchronization operation. This is a restart of the HSV450 controller in a manne r that has little or no impact on host system connectivity. Event Code: 0b01b515 Severity: Warning -- not failed but attention recommended or required. A migrate method drive codeload has stalled due to insufficient space in the Disk Group.

Event Code: 0b040004 Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware codeload begun. Event Code: 0b050004 Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware codeload has finished. Event Code: 0b06001a Severity: Normal -- informational in nature. An HSV450 controller has begun/fini shed a code load, code use, or code burn operation as indicated, in a manner tha t has little or no impact on host system connectivity. Event Code: 0b09001e Severity: Normal -- informational in nature. Process with work, eg. during CSM H ang and Unit Stalled Too Long. Event Code: 0b0af21e Severity: Warning -- not failed but attention recommended or required. An HSV450 controller has a pending sprite code load. In order to use the new sprite versi on the controller needs to be restarted. Event Code: 0b0b0024 Severity: Normal -- informational in nature. The preserving resync process has b een initiated and is progressing. Event Code: 0c03000c Severity: Normal -- informational in nature. The specified Data Replication Grou p has transitioned to the Merging state, because the Data Replication Destinatio n Storage System is now accessible or resumed. Event Code: 0c045f0c Severity: Critical -- failure or failure imminent. A Data Replication Group has entered the Failsafe Locked state because the Data Replication Destination Stora ge System is inaccessible. Event Code: 0c05610c Severity: Critical -- failure or failure imminent. A Data Replication Group has entered the Failsafe Locked state due to an inaccessible Destination Virtual Dis k. Event Code: 0c06600c Severity: Critical -- failure or failure imminent. A Full Copy was terminated pr ior to completion: An unrecoverable read error occurred on the specified Source Virtual Disk during the Full Copy. Event Code: 0c075f0c Severity: Critical -- failure or failure imminent. A Full Copy terminated prior to completion: A remote copy error occurred due to an inaccessible alternate Sto rage System; The Full Copy will continue when the Data Replication Destination i s restored. Event Code: 0c08610c Severity: Critical -- failure or failure imminent. A Full Copy terminated prior to completion: A remote copy error occurred due to an inaccessible Destination V irtual Disk; The Full Copy will continue when the Destination Virtual Disk is re stored. Event Code: 0c09620c Severity: Warning -- not failed but attention recommended or required. A Data Re

plication Log has been reset due to insufficient Disk Group capacity; The Data R eplication Destination has been marked for a Full Copy. Event Code: 0c0a000c Severity: Normal -- informational in nature. A Data Replication Log has been res et due to a Data Replication Group failover. Event Code: 0c0b620c Severity: Warning -- not failed but attention recommended or required. An unreco verable read error occurred on the specified Data Replication Group Data Replica tion Log logical disk during a background read. Event Code: 0c0c000c Severity: Normal -- informational in nature. A Destination Data Replication Grou p has successfully completed a Merge. Event Code: 0c0f000c Severity: Normal -- informational in nature. A Data Replication Group is no long er in a Failsafe Locked state. Event Code: 0c10000c Severity: Normal -- informational in nature. A Destination Data Replication Grou p has been marked for a Full Copy. Event Code: 0c11000c Severity: Normal -- informational in nature. This Data Replication Group is tran sitioning from a Data Replication Source role to a Data Replication Destination role. Event Code: 0c12000c Severity: Normal -- informational in nature. This Data Replication Group is tran sitioning from a Data Replication Destination role to a Data Replication Source role. Event Code: 0c155f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, possibly due to a connection failure between the specified host port and the Peer Storage Syste m. Event Code: 0c160016 Severity: Normal -- informational in nature. An HSV450 controller has sent a tim e report message to this HSV450 controller. Event Code: 0c17630c Severity: Critical -- failure or failure imminent. The Data Replication Manager communications protocol version between the Data Replication Source Storage Syst em and a Data Replication Destination Storage System is mismatched. Event Code: 0c18640c Severity: Critical -- failure or failure imminent. Conditions on the Data Replic ation Destination Storage System are preventing acceptable replication throughpu t: Initiating temporary logging on the affected Data Replication Group that is f ailsafe mode disabled. Event Code: 0c19020c Severity: Critical -- failure or failure imminent. Overlapping concurrent host w rites to an Active/Active Peer Storage System violate a Data Replication Manager architectural requirement, resulting in a reparative resynchronization operatio n for the master Storage System and a Full Copy operation.

Event Code: 0c1a000c Severity: Normal -- informational in nature. The specified Destination Virtual D isk has successfully completed a Full Copy. Event Code: 0c1b5f0c Severity: Critical -- failure or failure imminent. A Data Replication Group has transitioned to the Logging state because the alternate Storage System is not ac cessible. Event Code: 0c1c610c Severity: Critical -- failure or failure imminent. The specified Source Data Rep lication Group has transitioned to the (not merging) Logging state because a Des tination Virtual Disk is not accessible. Event Code: 0c1d000c Severity: Normal -- informational in nature. Inconsistency was found in the grou p log: A Full Copy of the affected Data Replication Group will be initiated. Event Code: 0c1e5f0c Severity: Critical -- failure or failure imminent. The members of the specified Source Data Replication Group have not been presented to the host because the re mote Storage System is not accessible: Suspend Source Data Replication Group to override this behavior, which will present the members. Event Code: 0c1f000c Severity: Normal -- informational in nature. The members of the specified Source Data Replication Group have been presented to the host because the remote Stora ge System is now accessible or source group is now suspended. Event Code: 0c20650c Severity: Critical -- failure or failure imminent. Conditions on the Data Replic ation Destination Storage System are preventing replication processing: The spec ified Source Data Replication Group will remain in the Logging or the Failsafe L ocked state until corrective action is performed. Event Code: 0c21660c Severity: Critical -- failure or failure imminent. A replication operation on th e Data Replication Source Storage System or Data Replication Destination Storage System has stalled which will prevent replication processing for the specified Data Replication Group until corrective action is performed. Event Code: 0c22000c Severity: Normal -- informational in nature. A Data Replication Path between thi s Storage System and the Peer Storage System has been opened. Event Code: 0c23670c Severity: Warning -- not failed but attention recommended or required. Condition s on the inter site link are preventing acceptable replication throughput: Initi ating temporary logging on the affected Data Replication Group that is failsafe mode disabled. Event Code: 0c24000c Severity: Normal -- informational in nature. The specified Source Data Replicati on Group has transitioned to the (not merging) Logging state because a Destinati on Virtual Disk is momentarily inaccessible. Event Code: 0c25000c Severity: Normal -- informational in nature. A Full Copy terminated prior to com pletion: A remote copy error occurred due to a momentarily inaccessible Destinat

ion Virtual Disk; The Full Copy will continue when the Destination Virtual Disk is restored. Event Code: 0c26000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has been opened due to simultaneo us requests from each Storage System Event Code: 0c27000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has been opened by the Peer Stora ge System. Event Code: 0c285f0c Severity: Critical -- failure or failure imminent. A Data Replication Path to th e Peer Storage System is not currently available. Event Code: 0c29000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed in order to force Data Replication Manager traffic to the controller's Preferred Port. Event Code: 0c2a000c Severity: Normal -- informational in nature. A Data Replication Path to a Peer S torage System has been found. Event Code: 0c2b600c Severity: Critical -- failure or failure imminent. A Merge was terminated prior to completion: An unrecoverable read error occurred on the log unit of the speci fied Data Replication Group during the Merge. Event Code: 0c2c660c Severity: Critical -- failure or failure imminent. A replication operation on th e Data Replication Source Storage System or Data Replication Destination Storage System has stalled which will prevent replication processing for the specified Data Replication Group until corrective action is performed. Event Code: 0c2d000c Severity: Normal -- informational in nature. The Peer Storage System port name t hat was incorrectly associated with a host has been deleted from the specified c lient object. Event Code: 0c2e680c Severity: Warning -- not failed but attention recommended or required. Insuffici ent resources exist to discover additional remote nodes. Event Code: 0c2f000c Severity: Normal -- informational in nature. Sufficient resources now exist to a llow discovery of additional remote nodes. Event Code: 0c30000c Severity: Normal -- informational in nature. A replication operation on the Data Replication Source Storage System or Data Replication Destination Storage Syste m has stalled which will prevent replication processing for the specified Data R eplication Group until corrective action is performed. Event Code: 0c31000c Severity: Normal -- informational in nature. A stalled Full Copy has been restar ted.

Event Code: 0c325f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, because the hos t port connection has failed. Event Code: 0c335f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, because the lin k or the Storage System has become unresponsive. Event Code: 0c345f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, due to slow res ponse on the connection between the specified host port and the Peer Storage Sys tem. Event Code: 0c35070c Severity: Warning -- not failed but attention recommended or required. The Data Replication Path between this Storage System and the Peer Storage System has clo sed, because a Data Replication Group configuration change lock was not released in a timely manner. Event Code: 0c365f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, due to thrashin g of the connection between the specified host port and the Peer Storage System. Event Code: 0c375f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, because the max imum ping retry count has been exceeded. Event Code: 0c38630c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, because the Dat a Replication Path protocol version is not supported by the controller firmware. Event Code: 0c39000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed, because the Data Repl ication Path is not being used. Event Code: 0c3a5f0c Severity: Critical -- failure or failure imminent. A Data Replication Path betwe en this Storage System and the Peer Storage System could not be created, possibl y due to a connection failure between the specified host port and the Peer Stora ge System. Event Code: 0c3b000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed, because the Peer Stor age System requested the creation of a new Data Replication Path. Event Code: 0c3c000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed because the Peer Stora ge System tried to open a Data Replication Path to a different host port. Event Code: 0c3d5f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet

ween this Storage System and the Peer Storage System has closed because of a fra me retransmit limit was reached. Event Code: 0c3e000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System was closed by the Peer Storage Sy stem. Event Code: 0c3f000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed because the NPortID of the remote port changed. Event Code: 0c40690c Severity: Warning -- not failed but attention recommended or required. The Data Replication Path between this Storage System and the Peer Storage System has clo sed because an out of order frame sequence number was detected. Event Code: 0c41000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed to allow creation of a Data Replication Path that requires a lower protocol version. Event Code: 0c42000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed because Peer Storage S ystem no longer exists. Event Code: 0c43000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has been closed by user request. Event Code: 0c49000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed because the correspond ing connection data was deleted. This is typically due to a change in the fabric . Event Code: 0c4a000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the Storage System is re-starting. Event Code: 0c4b000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the Storage System is not active. Event Code: 0c4c000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the firmware has not completed Data Replication Pa th discovery. Event Code: 0c4e000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the remote port is not associated with a Enterpris e Virtual Array. Event Code: 0c4f000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the remote port world wide identifier is associate d with a host system.

Event Code: 0c50000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the supplied UUID does not match the UUID for this Storage System. Event Code: 0c51000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the requested protocol version is not compatible w ith the existing Data Replication Path. Event Code: 0c52000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the requested port was disabled by the user. Event Code: 0c53000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the insufficient resources exist to create the Dat a Replication Path. Event Code: 0c54000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected to force the use of a lower protocol version on the Data R eplication Path. Event Code: 0c550016 Severity: Normal -- informational in nature. A time synchronization message has been sent to a Alternate Site. Event Code: 0c56000c Severity: Normal -- informational in nature. The DRM Forced Logging Timeout valu e has been changed. Event Code: 0c57000c Severity: Normal -- informational in nature. The DRM Forced Logging Timeout valu e has been reset to the default value. Event Code: 0c58690c Severity: Warning -- not failed but attention recommended or required. Excessive data exchange retry rate on the inter site link is preventing acceptable replic ation throughput: Reducing data exchange resources. Event Code: 0c59690c Severity: Warning -- not failed but attention recommended or required. Excessive out of order message rate on the inter site link is impacting replication throu ghput. Event Code: 0c5a670c Severity: Warning -- not failed but attention recommended or required. Excessive PING response time on the inter site link is preventing acceptable replication throughput: Reducing data exchange resources. Event Code: 0c5b670c Severity: Warning -- not failed but attention recommended or required. Replicati on data exchange write resources on the inter site link have been reduced to the minimum allowed value. Event Code: 0c5c670c Severity: Warning -- not failed but attention recommended or required. Replicati on data exchange copy resources on the inter site link have been reduced to the

minimum allowed value. Event Code: 0c5d000c Severity: Normal -- informational in nature. Quality of service on the inter sit e link has improved: Increasing data exchange resources to improve replication t hroughput. Event Code: 0c5e000c Severity: Normal -- informational in nature. A Replication Write History Log Shr ink is in progress. Event Code: 0c5f000c Severity: Normal -- informational in nature. A Replication Write History Log Shr ink has completed. Event Code: 0c60000c Severity: Normal -- informational in nature. Excessive Vdisk response time at th e Data Replication Destination has been detected: Reducing data exchange copy re sources on the inter site link to limit replication throughput. Event Code: 0c61000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed to allow resynchroniza tion with the Peer Storage System. Event Code: 0c62000c Severity: Normal -- informational in nature. The members of the specified Source Data Replication Group have been re-presented to the host because the split bra in protection condition has been manually checked and cleared. Event Code: 0c63000c Severity: Normal -- informational in nature. The members of the specified Source Data Replication Group have not been presented to the host because the remote S torage System is not accessible: Suspend\Resume Source Data Replication Group to override this behavior, which will present the members. Event Code: 0c64000c Severity: Normal -- informational in nature. The specified Data Replication Grou p was not set on the Data Replication Destination other site since the version d oes not support the feature Event Code: 0c65000c Severity: Normal -- informational in nature. The specified Data Replication Grou p log has hit the 50 percent full mark. Event Code: 0c66000c Severity: Normal -- informational in nature. The specified Data Replication Grou p log has hit the 75 percent full mark. Event Code: 0c67000c Severity: Normal -- informational in nature. The specified Data Replication Grou p log has hit the 90 percent full mark. Event Code: 0c68000c Severity: Normal -- informational in nature. The specified Data Replication Grou p log has hit the 95 percent full mark. Event Code: 0c69000c Severity: Normal -- informational in nature. The specified Data Replication Grou p log has hit the 99 percent full mark.

Event Code: 0c6f000c Severity: Normal -- informational in nature. Excessive Vdisk response time at th e Data Replication Source has been detected: Reducing data exchange copy resourc es on the inter site link to limit replication throughput. Event Code: 0c70000c Severity: Normal -- informational in nature. The specified Destination Virtual D isk has successfully completed a Fast Resync. Event Code: 0c71000c Severity: Normal -- informational in nature. Async group removal: the Source Vir tual Disk member has been successfully removed from the Async group Data Replica tion Group. Event Code: 0c72000c Severity: Normal -- informational in nature. The removal of the Source Virtual D isk failed for the Data Replication Group. Event Code: 0c73000c Severity: Normal -- informational in nature. The removal of the Source Virtual D isk completed after a log full condition for a Data Replication Group. The desti nation member, if retained, may not have all the data. Event Code: 0c74000c Severity: Normal -- informational in nature. The Source Virtual Disk in group Da ta Replication Group has started Merge Sync. Event Code: 0c75000c Severity: Normal -- informational in nature. The Source Virtual Disk in group Da ta Replication Group has finished Merge Sync. Event Code: 0c76000c Severity: Normal -- informational in nature. The Data Replication Log of a newly created Data Replication Group has been assigned to a FATA Disk Group. Event Code: 0c77000c Severity: Normal -- informational in nature. This Data Replication Group is fail ing over during a copy operation. Event Code: 0c78000c Severity: Normal -- informational in nature. The Source Virtual Disk of a Data R eplication Group completed shrinking. Event Code: 0c79000c Severity: Normal -- informational in nature. The Source Virtual Disk of a Data R eplication Group has failed shrink. Event Code: 0c7a000c Severity: Normal -- informational in nature. The Source Virtual Disk of a Data R eplication Group will shrink immediately due to a log full condition. Event Code: 0c7b000c Severity: Normal -- informational in nature. The Data Replication Log of a newly created Data Replication Group has been assigned to a SSD Disk Group. Event Code: 0c7c000c Severity: Normal -- informational in nature. The Destination Virtual Disk of a D ata Replication Group has been assigned to a SSD Disk Group.

Event Code: 0c7d000c Severity: Normal -- informational in nature. The Source Virtual Disk of a Data R eplication Group has been assigned to a SSD Disk Group. Event Code: 0c7e5f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed because the conn ection has been logged out. Event Code: 0c7f5f0c Severity: Critical -- failure or failure imminent. The number of nPortIds suppor ting the Data Replication Manager protocol exceeds the maximum supported by the firmware. Event Code: 0c806a0c Severity: Warning -- not failed but attention recommended or required. A request to create a Data Replication Path was rejected because the communication protoc ol settings are not compatible. Event Code: 0c815f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed because the Data Replication Path is disabled or no longer available. Event Code: 0c826b0c Severity: Critical -- failure or failure imminent. The capacity of the Source Vi rtual Disk and its peer Destination Virtual Disk are different and must be corre cted. Event Code: 0c83000c Severity: Normal -- informational in nature. The Data Replication Group and its members have completed a failover between the master and slave controllers. Event Code: 0c84000c Severity: Normal -- informational in nature. A Replication Write History Log exp ansion has completed. Event Code: 0c86000c Severity: Normal -- informational in nature. The removal of the Source Virtual D isk failed on the DESTINATION for the Data Replication Group. Event Code: 0d024106 Severity: Warning -- not failed but attention recommended or required. A physica l disk drive is improperly installed or missing. This could affect the drive enc losure air flow and cause an over temperature condition. Event Code: 0d348006 Severity: Critical -- failure or failure imminent. A drive enclosure power suppl y is improperly installed or missing. This could affect the drive enclosure air flow and cause an over temperature condition. The operational power supply will automatically shut down after a short period of time, thereby disabling the driv e enclosure. This condition remains active until either the problem is corrected , or the operational power supply shuts down, whichever occurs first. Event Code: 0d359a06 Severity: Critical -- failure or failure imminent. A drive enclosure power suppl y component has failed. Event Code: 0d478306 Severity: Critical -- failure or failure imminent. A drive enclosure fan module

is not operating properly. This could affect the drive enclosure air flow and ca use an over temperature condition. A single fan operating at high speed can prov ide sufficient air flow to cool an enclosure. However, operating an enclosure at temperatures approaching an overheating threshold can damage elements and may r educe the mean time before failure of a specific element. Event Code: 0d4b8206 Severity: Critical -- failure or failure imminent. A drive enclosure fan module is improperly installed or missing. This affects the drive enclosure air flow an d can cause an over temperature condition. Event Code: 0d5b8606 Severity: Warning -- not failed but attention recommended or required. The tempe rature of a Enclosure Link Module temperature sensor or Midplane temperature sen sor of the disk enclosure is at warning level. The Enterprise Virtual Array syst em will automatically shut down if the average temperature of all the temperatur e sensors (IOA, IOB, and 2 Midplane temperature sensors) of the disk enclosure i s at or above 50C. Event Code: 0d5f8706 Severity: Critical -- failure or failure imminent. The temperature of a Enclosur e Link Module temperature sensor or Midplane temperature sensor of the disk encl osure is at critical level. The Enterprise Virtual Array system will automatical ly shut down if the average temperature of all the temperature sensors (IOA, IOB , and 2 Midplane temperature sensors) of the disk enclosure is at or above 50C. Event Code: 0d8d9006 Severity: Critical -- failure or failure imminent. A drive enclosure transceiver error has been detected. Event Code: 0ddd9306 Severity: Critical -- failure or failure imminent. A drive enclosure I/O module error has occurred. Event Code: 0dde0006 Severity: Normal -- informational in nature. A drive enclosure I/O module is not communicating with the other I/O module. Event Code: 0df00011 Severity: Normal -- informational in nature. The status has changed on one or mo re of the drive enclosures. This informational event is generated for the HSV el ement manager GUI and contains no user information. Event Code: 0e800019 Severity: Normal -- informational in nature. Battery subsystem boot time status. Event Code: 0e810019 Severity: Normal -- informational in nature. Battery assembly '0' is now present . Event Code: 0e82e119 Severity: Critical -- failure or failure imminent. Battery assembly '0' has been removed. Event Code: 0e830019 Severity: Normal -- informational in nature. The status of battery assembly '0' has changed. Event Code: 0e84dd19 Severity: Critical -- failure or failure imminent. Battery assembly '0' has malf

unctioned. Event Code: 0e850019 Severity: Normal -- informational in nature. Battery assembly '1' is now present . Event Code: 0e86e219 Severity: Critical -- failure or failure imminent. Battery assembly '1' has been removed. Event Code: 0e870019 Severity: Normal -- informational in nature. The status of battery assembly '1' has changed. Event Code: 0e88de19 Severity: Critical -- failure or failure imminent. Battery assembly '1' has malf unctioned. Event Code: 0e890019 Severity: Normal -- informational in nature. Battery assembly '2' is now present . Event Code: 0e8ae319 Severity: Critical -- failure or failure imminent. Battery assembly '2' has been removed. Event Code: 0e8b0019 Severity: Normal -- informational in nature. The status of battery assembly '2' has changed. Event Code: 0e8cdf19 Severity: Critical -- failure or failure imminent. Battery assembly '2' has malf unctioned. Event Code: 0e8d0019 Severity: Normal -- informational in nature. Battery assembly '3' is now present . Event Code: 0e8ee419 Severity: Critical -- failure or failure imminent. Battery assembly '3' has been removed. Event Code: 0e8f0019 Severity: Normal -- informational in nature. The status of battery assembly '3' has changed. Event Code: 0e90e019 Severity: Critical -- failure or failure imminent. Battery assembly '3' has malf unctioned. Event Code: 0e910019 Severity: Normal -- informational in nature. The battery subsystem has transitio ned to the good state. Event Code: 0e920019 Severity: Normal -- informational in nature. The battery subsystem has transitio ned to the low state. Event Code: 0e93e519 Severity: Warning -- not failed but attention recommended or required. The batte

ry subsystem has transitioned to the bad state. Event Code: 0e940019 Severity: Normal -- informational in nature. Blower subsystem boot time status. Event Code: 0e950019 Severity: Normal -- informational in nature. Blower assembly '0' is now present. Event Code: 0e96e919 Severity: Critical -- failure or failure imminent. Blower assembly '0' has been removed. Event Code: 0e970019 Severity: Normal -- informational in nature. The status of blower assembly '0' h as changed. Event Code: 0e98e719 Severity: Critical -- failure or failure imminent. Blower assembly '0' has malfu nctioned. Event Code: 0e990019 Severity: Normal -- informational in nature. Blower assembly '1' is now present. Event Code: 0e9aea19 Severity: Critical -- failure or failure imminent. Blower assembly '1' has been removed. Event Code: 0e9b0019 Severity: Normal -- informational in nature. The status of blower assembly '1' h as changed. Event Code: 0e9ce819 Severity: Critical -- failure or failure imminent. Blower assembly '1' has malfu nctioned. Event Code: 0e9def19 Severity: Warning -- not failed but attention recommended or required. Battery r ead memory failure has occurred. Event Code: 0e9e0019 Severity: Normal -- informational in nature. Temperature subsystem boot time sta tus. Event Code: 0e9f0019 Severity: Normal -- informational in nature. The temperature within an HSV450 co ntroller has returned to its normal operating range. Event Code: 0ea02e19 Severity: Warning -- not failed but attention recommended or required. The tempe rature within an HSV450 controller is approaching its trip point. Event Code: 0ea13619 Severity: Critical -- failure or failure imminent. The temperature trip point fo r a temperature sensor located within an HSV450 controller has been reached. Event Code: 0ea20019 Severity: Normal -- informational in nature. Power Supply subsystem boot time st atus. Event Code: 0ea30019

Severity: Normal -- informational in nature. Power Supply assembly '0' is now pr esent. Event Code: 0ea4ed19 Severity: Critical -- failure or failure imminent. Power Supply assembly '0' has been removed. Event Code: 0ea50019 Severity: Normal -- informational in nature. The status of power supply assembly '0' has changed. Event Code: 0ea6eb19 Severity: Critical -- failure or failure imminent. Power supply assembly '0' los t AC connection or has malfunctioned. Event Code: 0ea70019 Severity: Normal -- informational in nature. Power Supply assembly '1' is now pr esent. Event Code: 0ea8ee19 Severity: Critical -- failure or failure imminent. Power Supply assembly '1' has been removed. Event Code: 0ea90019 Severity: Normal -- informational in nature. The status of power supply assembly '1' has changed. Event Code: 0eaaec19 Severity: Critical -- failure or failure imminent. Power supply assembly '1' los t AC connection or has malfunctioned. Event Code: 0f004a08 Severity: Warning -- not failed but attention recommended or required. A Fibre C hannel port on the HSV450 controller has failed to respond. Event Code: 0f010007 Severity: Normal -- informational in nature. An excessive number of link errors were detected on a HSV450 controller's mirror Fibre Channel port. This informati onal event is triggered by the occurrence of an excessive number of Tachyon chip link status errors detected within a particular link status error type. Event Code: 0f020013 Severity: Normal -- informational in nature. An HSV450 controller has been told to enable a mirror port, and that mirror port was not disabled during boot diagn ostics. Event Code: 0f034709 Severity: Warning -- not failed but attention recommended or required. A non-dat a exchange sent to a mirror port has timed out. Event Code: 0f040009 Severity: Normal -- informational in nature. The HSV450 controller has sent an E xtended Link Service command Reinstate Recovery Qualifier. Event Code: 0f050009 Severity: Normal -- informational in nature. The HSV450 controller has sent a Ba sic Link Service command Abort Sequence Frame. Event Code: 0f060024 Severity: Normal -- informational in nature. The HSV450 controller has updated i

ts Mirror Transport Status. Event Code: 0f070724 Severity: Warning -- not failed but attention recommended or required. The HSV45 0 controller mirror transport performed an invalid status change. Event Code: 42000008 Severity: Normal -- informational in nature. A host Fibre Channel port transitio ned to the link down state. Event Code: 42010008 Severity: Normal -- informational in nature. A host Fibre Channel port transitio ned to the link failed state. Event Code: 42020008 Severity: Normal -- informational in nature. A host Fibre Channel port transitio ned to the link up state AND the in-band port is ready for SCSI. Event Code: 42030007 Severity: Normal -- informational in nature. An excessive number of link errors were detected on a host Fibre Channel port. Event Code: 42044a08 Severity: Warning -- not failed but attention recommended or required. A host Fi bre Channel port has failed to respond. Event Code: 42050008 Severity: Normal -- informational in nature. A host Fibre Channel port has trans itioned to a deadlocked state. Event Code: 4206001b Severity: Normal -- informational in nature. Indicated Virtual Disk has transiti oned to Stalled Too Long. Event Code: 42080008 Severity: Normal -- informational in nature. A host Fibre Channel port has been reissued a freeze command. Event Code: 42090008 Severity: Normal -- informational in nature. A host Fibre Channel port has been issued a soft reset. Event Code: 420a001b Severity: Normal -- informational in nature. Indicated Virtual Disk that previou sly entered into Stalled Too Long has now been unstalled and resumed. Event Code: 420b001b Severity: Normal -- informational in nature. Indicated Virtual Disk has transiti oned to ownership by the other HSV450 controller. Event Code: 420c001b Severity: Normal -- informational in nature. Indicated Virtual Disk has failed t o transition ownership to the other HSV450 controller. Event Code: 420e0024 Severity: Normal -- informational in nature. Generic frontend service informatio n events. Event Code: 420f0008 Severity: Normal -- informational in nature. A host Fibre Channel port is being

reset to clear a credit error which may result in a subsequent LINK DOWN and LIN K UP event. Event Code: 42100008 Severity: Normal -- informational in nature. A host Fibre Channel port has compl eted name server registration . Event Code: 83002014 Severity: Critical -- failure or failure imminent. A failure was detected during the execution of this HSV450 controller's on-board diagnostics. Event Code: 83013014 Severity: Critical -- failure or failure imminent. A GBIC SFF Serial ID Data che ck code failure was detected during the execution of this HSV450 controller's on -board diagnostics. Event Code: 83073a14 Severity: Critical -- failure or failure imminent. A GBIC SFF was determined to be not present during the execution of this HSV450 controller's on-board diagnos tics. Event Code: 83083b14 Severity: Warning -- not failed but attention recommended or required. A failure was detected during testing of this HSV450 controller's SRAM. Event Code: 83093b14 Severity: Warning -- not failed but attention recommended or required. A parity error was detected during testing of this HSV450 controller's SRAM. Event Code: 830b0026 Severity: Normal -- informational in nature. Cache memory ECC errors exceeded 25 0/day in this HSV450 controller's SDRAM. Event Code: 830c0026 Severity: Normal -- informational in nature. Policy memory ECC errors exceeded 2 50/day in this HSV450 controller's SDRAM. Event Code: 830d0026 Severity: Normal -- informational in nature. Cache memory ECC errors exceeded 75 0/week in this HSV450 controller's SDRAM. Event Code: 830e0026 Severity: Normal -- informational in nature. Policy memory ECC errors exceeded 7 50/week in this HSV450 controller's SDRAM. TERMINATION CODES: Termination Code: 00000000 Unknown termination code Termination Code: 0101011f Severity: Critical -- failure or failure imminent. Unknown fault type reported b y EXEC. Termination Code: 0102011f Severity: Critical -- failure or failure imminent. DLQ entry not properly linked . Termination Code: 0103011f Severity: Critical -- failure or failure imminent. Timer not expired as expected

. Termination Code: 0104011f Severity: Critical -- failure or failure imminent. Structure not a timer as expe cted. Termination Code: 0105011f Severity: Critical -- failure or failure imminent. DLQ entry doubly linked. Termination Code: 0106011f Severity: Critical -- failure or failure imminent. DLQ head not properly linked. Termination Code: 0107011f Severity: Critical -- failure or failure imminent. SQ entry doubly linked. Termination Code: 0108011f Severity: Critical -- failure or failure imminent. Structure not a BQUE as expec ted. Termination Code: 0109011f Severity: Critical -- failure or failure imminent. Structure not a SEM as expect ed. Termination Code: 010a011f Severity: Critical -- failure or failure imminent. Function not yet implemented. Termination Code: 010b011f Severity: Critical -- failure or failure imminent. ILF invocation not from SC. Termination Code: 010c011f Severity: Critical -- failure or failure imminent. Too many performance log inst ances. Termination Code: 010d011f Severity: Critical -- failure or failure imminent. Undefined performance log cal l. Termination Code: 010e011f Severity: Critical -- failure or failure imminent. Structure not AQUE as expecte d. Termination Code: 010f011f Severity: Critical -- failure or failure imminent. Waiter queue not empty as exp ected. Termination Code: 0110011f Severity: Critical -- failure or failure imminent. Structure not GATE as expecte d. Termination Code: 0111011f Severity: Critical -- failure or failure imminent. Receiver queue not empty as e xpected. Termination Code: 0112011f Severity: Critical -- failure or failure imminent. BQUE has unexpected items. Termination Code: 0113011f Severity: Critical -- failure or failure imminent. Structure not ASEM as expecte d.

Termination Code: 0114011f Severity: Critical -- failure or failure imminent. Unknown system trap routine. Termination Code: 0115011f Severity: Critical -- failure or failure imminent. Active DMA list is empty. Termination Code: 0116011f Severity: Critical -- failure or failure imminent. CDB address not as expected. Termination Code: 0117011f Severity: Critical -- failure or failure imminent. Attempt to allocate a buffer that is already in use. Termination Code: 0118011f Severity: Critical -- failure or failure imminent. Attempt to free a buffer that is already free. Termination Code: 0119011f Severity: Critical -- failure or failure imminent. Interrupts unexpectedly disab led. Termination Code: 011a011f Severity: Critical -- failure or failure imminent. Page zero corrupted. Termination Code: 011b011f Severity: Critical -- failure or failure imminent. DCBZ not cache line aligned. Termination Code: 011c0140 Severity: Critical -- failure or failure imminent. Console requested crash with dump (not coupled). Termination Code: 011d01c0 Severity: Critical -- failure or failure imminent. Console requested crash with dump (coupled). Termination Code: 011e0120 Severity: Critical -- failure or failure imminent. Console requested restart wit hout dump (not coupled). Termination Code: 011f01a0 Severity: Critical -- failure or failure imminent. Console requested restart wit hout dump (coupled). Termination Code: 01220105 Severity: Critical -- failure or failure imminent. Unknown SMI interrupt occurre d. Termination Code: 01250160 Severity: Critical -- failure or failure imminent. Console requested crash with dump (not coupled). Termination Code: 012601e0 Severity: Critical -- failure or failure imminent. Console requested crash with dump (coupled). Termination Code: 01400100 Severity: Critical -- failure or failure imminent. Expiration queue not BQUE. Termination Code: 015a0100 Severity: Critical -- failure or failure imminent. exc_do_preempt_high called wi

th empty subprocess queue Termination Code: 02000100 Severity: Critical -- failure or failure imminent. Initialization failed due to insufficient memory. Termination Code: 02010100 Severity: Critical -- failure or failure imminent. CACHE_get_data called with ba d get data. Termination Code: 02020100 Severity: Critical -- failure or failure imminent. Cannot allocate BQ. Termination Code: 0203010b Severity: Critical -- failure or failure imminent. Duplicate dirty data found in Buffer Metadata Array. Termination Code: 0204010a Severity: Critical -- failure or failure imminent. Invalid Primary Mirror Operat ion state. Invalid Unit Cache state. Termination Code: 0205010a Severity: Critical -- failure or failure imminent. Invalid Unit Cache state. Termination Code: 02070100 Severity: Critical -- failure or failure imminent. Mirror data structure inconsi stency. Termination Code: 02080100 Severity: Critical -- failure or failure imminent. Mirror UUID Changed. Termination Code: 02090100 Severity: Critical -- failure or failure imminent. Invalid call to CACHE_lock_me ta. Termination Code: 020a0104 Severity: Critical -- failure or failure imminent. Cannot align parity and user data. Termination Code: 020b0100 Severity: Critical -- failure or failure imminent. Invalid Pullover Memory Opera tion state. Termination Code: 020c0106 Severity: Critical -- failure or failure imminent. Invalid Group Cache Operation state for Data Replication Group. Termination Code: 020d0104 Severity: Critical -- failure or failure imminent. Process NV Data NCA corrupted . Termination Code: 020e0100 Severity: Critical -- failure or failure imminent. Process NV Data Freeing Diag Buffer. Termination Code: 020f0100 Severity: Critical -- failure or failure imminent. Improper MWB Recovery data se nt. Termination Code: 02100108

Severity: Critical -- failure or failure imminent. Mnode & MFC NCAE Difference. Termination Code: 02110100 Severity: Critical -- failure or failure imminent. Improper MWBF Recovery data s ent. Termination Code: 02120100 Severity: Critical -- failure or failure imminent. WRITE HOLE COLLISION IN RS_CR ITICAL.c Termination Code: 02150101 Severity: Critical -- failure or failure imminent. Unable to obtain free cache n odes. Termination Code: 02160102 Severity: Critical -- failure or failure imminent. Unable to obtain free volatil e cache buffers. Termination Code: 02180102 Severity: Critical -- failure or failure imminent. Invalid Proxy Write Mirror Op eration state. Termination Code: 02190103 Severity: Critical -- failure or failure imminent. Invalid Proxy Read Mirror Ope ration state. Termination Code: 021a0102 Severity: Critical -- failure or failure imminent. Invalid Proxy Verify Mirror O peration state. Termination Code: 021b0100 Severity: Critical -- failure or failure imminent. Not enough XDs for RSTORE flu sh Termination Code: 021c0102 Severity: Critical -- failure or failure imminent. Invalid Flush Node Detected Termination Code: 021e0100 Severity: Critical -- failure or failure imminent. Firmware was loaded with an i ncompatible Cache memory layout Termination Code: 021f0100 Severity: Critical -- failure or failure imminent. Unable to obtain free non-vol atile cache buffers Termination Code: 02200100 Severity: Critical -- failure or failure imminent. Requested address out of rang e for the Cache Moving Window Termination Code: 02210100 Severity: Critical -- failure or failure imminent. A node was inserted into a li st that already had an overlapping node Termination Code: 03010104 Severity: Critical -- failure or failure imminent. Logic inconsistency detected; one HSV450 controller is suspect. Termination Code: 03020184 Severity: Critical -- failure or failure imminent. Logic inconsistency detected; both HSV450 controllers are suspect.

Termination Code: 03030102 Severity: Critical -- failure or failure imminent. Invalid value in switch state ment. Termination Code: 03040102 Severity: Critical -- failure or failure imminent. The minimum number of quorum disks is no longer accessible. Backend hardware failure, backend configuration p roblems, or HSV450 controller hardware failure are all possible causes. Termination Code: 03060184 Severity: Critical -- failure or failure imminent. An error for which no recover y is possible occurred. Termination Code: 030a0102 Severity: Critical -- failure or failure imminent. Index out of bounds in scsscs db_get_scsdb_ds call. Termination Code: 030b0101 Severity: Critical -- failure or failure imminent. Area offset unknown in scsscs db_get_scsdb_ds call. Termination Code: 030c0100 Severity: Critical -- failure or failure imminent. All SCSDB cache pages in use. Termination Code: 030d0101 Severity: Critical -- failure or failure imminent. scsscsdb_free_scsdb_page cach e inconsistency. Termination Code: 030e0102 Severity: Critical -- failure or failure imminent. Caller believes cache page is dirty and in use, but cache does not. Termination Code: 030f0101 Severity: Critical -- failure or failure imminent. Call to commit SCSDB while ca che page dirty or in use. Termination Code: 03100102 Severity: Critical -- failure or failure imminent. Index out of bounds in scscvm db_get_cvmdb_ds call. Termination Code: 03110101 Severity: Critical -- failure or failure imminent. Area offset unknown in scscvm db_get_cvmdb_ds call. Termination Code: 03120100 Severity: Critical -- failure or failure imminent. All CVMDB cache pages in use. Termination Code: 03130101 Severity: Critical -- failure or failure imminent. scscvmdb_free_cvmdb_page cach e inconsistency. Termination Code: 03140102 Severity: Critical -- failure or failure imminent. Caller believes cache page is dirty and in use, but cache does not. Termination Code: 03150101 Severity: Critical -- failure or failure imminent. Call to commit CVMDB while ca che page dirty or in use.

Termination Code: 03160100 Severity: Critical -- failure or failure imminent. Unable to allocate login maps . Termination Code: 031f0100 Severity: Critical -- failure or failure imminent. Unable to allocate tdsd pool. Termination Code: 032a0000 Severity: Normal -- informational in nature. Both HSV450 controllers registered as Storage System Master. Termination Code: 033c0106 Severity: Critical -- failure or failure imminent. Invalid port login state in r emote port object. Termination Code: 033d0105 Severity: Critical -- failure or failure imminent. Remote port logged_in timer e xpired in inappropriate login state. Termination Code: 03500020 Severity: Normal -- informational in nature. Crash forced by maintenance invoke CRASH or SCS_DEBUG command. Termination Code: 03510141 Severity: Critical -- failure or failure imminent. Crash forced by other HSV450 controller. <UL> <LI>TP[0] contains the reason code for the kill. </UL> Termination Code: 03520144 Severity: Critical -- failure or failure imminent. This controller killed other controller and CPLD_CRASH_ALWAYS set. <UL> <LI>TP[1] contains the reason code for the kill. </UL> Termination Code: 03640021 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation and then restart. Termination Code: 03650061 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation and then not restart. Termination Code: 03660061 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation and then power off. Termination Code: 03670000 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation, perform a crash dump and then restart. Termination Code: 03680040 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation, perform a crash dump and then not restart. Termination Code: 03690080 Severity: Normal -- informational in nature. Both HSV450 controllers were reques ted to terminate operation, perform a crash dump and then restart.

Termination Code: 036a00c0 Severity: Normal -- informational in nature. Both HSV450 controllers were reques ted to terminate operation, perform a crash dump and then not restart. Termination Code: 036c01c8 Severity: Critical -- failure or failure imminent. This special termination even t is for engineering debug purpose. Termination Code: 036f0061 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation, not restart, and indicate its location. Termination Code: 03700022 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation in order to recover from a fast failover by remaining i n single controller mode until the failover data in the cache can be completely flushed. Termination Code: 03780101 Severity: Critical -- failure or failure imminent. Unable to realize the CVMDB o r SCSDB during Storage System Master failover. Backend hardware failure, backend configuration problems, or HSV450 controller hardware failure are all possible causes. Termination Code: 03790020 Severity: Normal -- informational in nature. This HSV450 controller is restartin g in order to use a new version of firmware. Termination Code: 0400011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap (i.e., SIMM operand of twi instr uction not a recognized FM_TRAP_TYPE_xxx variant or tw instruction executed). Termination Code: 0401011f Severity: Critical -- failure or failure imminent. Machine Check Interrupt Vecto r Service Routine (MCIVSR) entered; termination processing interrupted before fm _decode_machine_check could be performed. Termination Code: 0402011f Severity: Critical -- failure or failure imminent. DEBUG statement executed. Termination Code: 0403047f Severity: Undetermined -- more information needed to determine severity. Termina tion event is recursive -- i.e., the Termination Event Information contained in multiple recent Termination Events array entries is identical and the terminatio ns occurred within a short interval of time. Termination Code: 04050101 Severity: Critical -- failure or failure imminent. Out of range event data block index encountered in fm_update_scelaba_entry. Termination Code: 0406017f Severity: Critical -- failure or failure imminent. The EDC used to test the vali dity of the Last Termination Event area in nonvolatile memory was bad. Either th e EDC was not updated due to premature termination of post-termination operation s or the memory area was corrupted in an unexplained manner. A power supply inte rnal failure could cause this termination. Note: The in progress event informati on may not describe the event that caused the HSV450 controller to terminate ope ration depending on how far termination processing got before the event occurred

. Termination Code: 0407016a Severity: Critical -- failure or failure imminent. An unexpected event array ent ry indicated that post-termination operations were terminated prematurely before or during the event report block load. Termination Code: 04080582 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV450 controller with the coupled cras h flag set. Termination Code: 040905a2 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV450 controller with the coupled cras h flag set. Termination Code: 040a05c2 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV450 controller with the coupled cras h flag set. Termination Code: 040b05e2 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV450 controller with the coupled cras h flag set. Termination Code: 040c0582 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV450 controller with the coupled cras h flag set and an unrecognized Dump/Restart code. Termination Code: 040d0101 Severity: Critical -- failure or failure imminent. Unrecognized fm_update_scelab a_entry operation code encountered. Termination Code: 040e0100 Severity: Critical -- failure or failure imminent. This HSV450 controller is not the Storage System Master when conditions dictate that it should be. Termination Code: 040f0100 Severity: Critical -- failure or failure imminent. This HSV450 controller is the Storage System Master when conditions dictate that it should not be. Termination Code: 04100182 Severity: Critical -- failure or failure imminent. The Storage System Terminatio n Event Log or Storage System Event Log is not active when conditions dictate th at it should be. Termination Code: 04110181 Severity: Critical -- failure or failure imminent. The Storage System Terminatio n Event Log or Storage System Event Log is inaccessible. Termination Code: 04120123 Severity: Critical -- failure or failure imminent. An invalid entry or an incons istency between entries was found in the Last Termination Event array following a controller resynchronization operation; all entries in the array were reset. Termination Code: 04130107 Severity: Critical -- failure or failure imminent. Structure type is not as expe

cted. Termination Code: 04140104 Severity: Critical -- failure or failure imminent. Event Information Packet type is out of range. Termination Code: 04150104 Severity: Critical -- failure or failure imminent. Event Information Packet size is too big. Termination Code: 04160103 Severity: Critical -- failure or failure imminent. Event Information Packet size is not a longword multiple. Termination Code: 04170107 Severity: Critical -- failure or failure imminent. Invalid Storage System Termin ation Event Log or Storage System Event Log I/O request, no data mapped (unalloc ated) or object is unknown. Termination Code: 04180107 Severity: Critical -- failure or failure imminent. Unrecognized status returned following a Storage System Termination Event Log or Storage System Event Log I/O request. Termination Code: 04190100 Severity: Critical -- failure or failure imminent. The restartdebug routine was invoked without a termination having been performed. Termination Code: 041a0100 Severity: Critical -- failure or failure imminent. The Fault Manager's active qu eue is unexpectedly empty. Termination Code: 041b0105 Severity: Critical -- failure or failure imminent. The Fault Manager detected th at the correct event data block was not cached. Termination Code: 041c0100 Severity: Critical -- failure or failure imminent. Calling process is not the St orage System Management Interface or Host Port SCSI as it should be. Termination Code: 041d0100 Severity: Critical -- failure or failure imminent. Calling process is not the St orage System Management Interface as it should be. Termination Code: 041e0102 Severity: Critical -- failure or failure imminent. Termination Event Information Store Packet content is not as expected. Termination Code: 041f0a1f Severity: Critical -- failure or failure imminent. Either a low memory access vi olation made by the HSV450 controller's software (e.g., access to memory address zero through an uninitialized pointer, etc.) or an uncorrectable memory error w as detected. Termination Code: 0420011f Severity: Critical -- failure or failure imminent. The HSV450 controller inactiv ity watchdog timer expired. Termination Code: 04210107 Severity: Critical -- failure or failure imminent. Drive Broken status returned

following a Storage System Termination Event Log or Storage System Event Log I/O request. Termination Code: 04220102 Severity: Critical -- failure or failure imminent. The Software Component ID spe cified in an Event Code is illegal. Termination Code: 04240960 Severity: Warning -- not failed but attention recommended or required. Power fai led. Termination Code: 043f011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 0, Reserved exception. Termination Code: 0440011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 100, System Reset exception. Termination Code: 0441011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 200, Machine Check exception. Termination Code: 0442011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 300, DSI exc eption (i.e., a data memory access cannot be performed). Termination Code: 0443011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 400, ISI exc eption (i.e., an attempt to fetch the next instruction to be executed failed). Termination Code: 0444011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 500, Externa l Interrupt exception. Termination Code: 0445011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 600, Alignme nt exception (i.e., a memory access cannot be performed because the address alig nment or mode is incompatible for the instruction that was about to be executed) . Termination Code: 0446011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 700, Program exception (i.e., execution of an illegal or privileged instruction was attempte d). Termination Code: 0447011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 800, Floatin g-Point Unavailable exception (i.e., an attempt was made to execute a floating-p oint instruction and the floating-point available bit in the MSR was cleared).

Termination Code: 0448011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 900, Decreme nter exception. Termination Code: 0449011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector A00, Reserve d exception. Termination Code: 044a011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector B00, Reserve d exception. Termination Code: 044b011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector C00, System Call exception. Termination Code: 044c011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector D00, Trace e xception. Termination Code: 044d011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector E00, Floatin g-Point Assist exception. Termination Code: 044e011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector F00, Reserve d exception. Termination Code: 044f011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1000, Instru ction Translation Miss exception. Termination Code: 0450011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1100, Data L oad Translation Miss exception. Termination Code: 0451011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1200, Data S tore Translation Miss exception. Termination Code: 0452011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1300, Instru ction Address Break exception. Termination Code: 0453011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1400, System Management exception.

Termination Code: 04540101 Severity: Critical -- failure or failure imminent. Event data block count unexpe cted. Termination Code: 04550101 Severity: Critical -- failure or failure imminent. FM_locate_event_info received unexpected event retrieval status. Termination Code: 04560102 Severity: Critical -- failure or failure imminent. FM_activeq_read_event was una ble to satisfy an active queue event request due to an internal inconsistency. Termination Code: 04570105 Severity: Critical -- failure or failure imminent. A direct call to FM_x_termina te_ctl was made. FM_terminate_ctl_user or FM_terminate_ctl_isr must be used inst ead. Termination Code: 0458011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1500, Reserv ed exception. Termination Code: 0459011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1600, Altive c exception. Termination Code: 045a011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1700, Reserv ed exception. Termination Code: 045b011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1800, Reserv ed exception. Termination Code: 045c011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1900, Reserv ed exception. Termination Code: 045d011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1A00, Reserv ed exception. Termination Code: 045e011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1B00, Reserv ed exception. Termination Code: 045f011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1C00, Reserv ed exception. Termination Code: 0460011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1D00, Reserv

ed exception. Termination Code: 0461011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1E00, Reserv ed exception. Termination Code: 0462011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1F00, Reserv ed exception. Termination Code: 0463011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2000, Reserv ed exception. Termination Code: 0464011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2100, Reserv ed exception. Termination Code: 0465011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2200, Reserv ed exception. Termination Code: 0466011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2300, Reserv ed exception. Termination Code: 0467011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2400, Reserv ed exception. Termination Code: 0468011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2500, Reserv ed exception. Termination Code: 0469011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2600, Reserv ed exception. Termination Code: 046a011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2700, Reserv ed exception. Termination Code: 046b011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2800, Reserv ed exception. Termination Code: 046c011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2900, Reserv

ed exception. Termination Code: 046d011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2A00, Reserv ed exception. Termination Code: 046e011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2B00, Reserv ed exception. Termination Code: 046f011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2C00, Reserv ed exception. Termination Code: 0470011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2D00, Reserv ed exception. Termination Code: 0471011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2E00, Reserv ed exception. Termination Code: 0472011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2F00, Reserv ed exception. Termination Code: 04730167 Severity: Critical -- failure or failure imminent. Error encountered while build ing ADDRESS_MAP. Termination Code: 04740160 Severity: Critical -- failure or failure imminent. Fault Manager Event Log Packe t Management Area not allocated. Termination Code: 0476013f Severity: Critical -- failure or failure imminent. The EDC used to test the vali dity of the Last Termination Event area in nonvolatile memory was bad; terminati on processing was completed. Termination Code: 0477013f Severity: Critical -- failure or failure imminent. The EDC used to test the vali dity of the Last Termination Event area in nonvolatile memory was bad; terminati on processing was initiated but not completed. Termination Code: 0478393f Severity: Warning -- not failed but attention recommended or required. The EDC u sed to test the validity of the Last Termination Event area in nonvolatile memor y was bad; termination processing was not initiated, the HSV450 controller's Pow erPC was spontaneously reset. Termination Code: 04790020 Severity: Normal -- informational in nature. The EDC used to test the validity o f the Last Termination Event area in nonvolatile memory was bad; manufacturing f ull memory test was executed.

Termination Code: 047a013f Severity: Critical -- failure or failure imminent. The EDC used to test the vali dity of the Last Termination Event area in nonvolatile memory was bad; unexpecte d termination processing state. Termination Code: 047b0025 Severity: Normal -- informational in nature. The HSV450 controller has been requ ested to be uninitialized by the user. Termination Code: 04810111 Severity: Critical -- failure or failure imminent. The HSV450 controller inactiv ity watchdog timer expired. Termination Code: 04822070 Severity: Critical -- failure or failure imminent. Cache Memory VTT Voltage Fail ure. Termination Code: 04832070 Severity: Critical -- failure or failure imminent. Non-Volatile Cache Memory Vol tage Failure. Termination Code: 04842070 Severity: Critical -- failure or failure imminent. Volatile Cache Memory Voltage Failure. Termination Code: 04852010 Severity: Critical -- failure or failure imminent. PowerPC Bus Data Parity Error . Termination Code: 04862011 Severity: Critical -- failure or failure imminent. PowerPC Bus Address Parity Er ror. Termination Code: 0487390f Severity: Warning -- not failed but attention recommended or required. PowerPC L 1 Instruction Cache Error. Termination Code: 0488390f Severity: Warning -- not failed but attention recommended or required. PowerPC L 1 Data Cache Error. Termination Code: 0489390f Severity: Warning -- not failed but attention recommended or required. PowerPC L 2 Cache Tag Parity or L2 Cache Data Parity Error. Termination Code: 048a2016 Severity: Critical -- failure or failure imminent. Sprite PowerPC Transfer TimeO ut Error. Termination Code: 048b0031 Severity: Normal -- informational in nature. Killed by Other Controller. Termination Code: 048c0026 Severity: Normal -- informational in nature. Software Restart. Termination Code: 048d0026 Severity: Normal -- informational in nature. Button Reset. Termination Code: 048e0115

Severity: Critical -- failure or failure imminent. Atlantis CPU Address Out of R ange Error. Termination Code: 048f2016 Severity: Critical -- failure or failure imminent. Atlantis Transfer Type/Initia l Value Violation Error. Termination Code: 04900115 Severity: Critical -- failure or failure imminent. Atlantis Access to a Protecte d Region Error. Termination Code: 04913916 Severity: Warning -- not failed but attention recommended or required. Atlantis Integrated SRAM Parity Error. Termination Code: 04922016 Severity: Critical -- failure or failure imminent. Uncorrectable Policy Memory E CC Error. Termination Code: 04930113 Severity: Critical -- failure or failure imminent. Atlantis Device Burst Violati on Error. Termination Code: 04942014 Severity: Critical -- failure or failure imminent. Atlantis Device Ready Timeout Error. Termination Code: 04952014 Severity: Critical -- failure or failure imminent. Atlantis Device Address or Da ta Parity Error. Termination Code: 04960113 Severity: Critical -- failure or failure imminent. Atlantis DMA Failure to Decod e Address Error. Termination Code: 04970113 Severity: Critical -- failure or failure imminent. Atlantis DMA Access Protectio n Violation Error. Termination Code: 04980113 Severity: Critical -- failure or failure imminent. Atlantis DMA Write Protect Vi olation Error. Termination Code: 04990113 Severity: Critical -- failure or failure imminent. Atlantis DMA Attempt to Acces s the Descriptor Owned by the CPU. Termination Code: 049a0110 Severity: Critical -- failure or failure imminent. Sprite PowerPC Transfer Timeo ut on PCIX Error. Termination Code: 049b2011 Severity: Critical -- failure or failure imminent. Sprite PowerPC Last Entry Err or. Termination Code: 049c2011 Severity: Critical -- failure or failure imminent. Sprite PowerPC Alignment Erro r. Termination Code: 049d3911

Severity: Warning -- not failed but attention recommended or required. Sprite Qu eue Read Data Parity Error. Termination Code: 049e0110 Severity: Critical -- failure or failure imminent. Sprite PCIX Access Error - No t a 4-Byte Access. Termination Code: 049f2012 Severity: Critical -- failure or failure imminent. Sprite Queue Detected an Inva lid Destination Error. Termination Code: 04a0011c Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - TimeOut Erro r. Termination Code: 04a1011c Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - Start Frame Error. Termination Code: 04a2011c Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - End Frame Er ror. Termination Code: 04a3391d Severity: Warning -- not failed but attention recommended or required. Sprite XO R-DMA - Parity Error. Termination Code: 04a4011c Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - Invalid Opco de Error. Termination Code: 04a5011c Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - Count Error. Termination Code: 04a62012 Severity: Critical -- failure or failure imminent. Sprite Bad Write Data Error. Termination Code: 04a73912 Severity: Warning -- not failed but attention recommended or required. Sprite Co mmand/Data Parity Error. Termination Code: 04a82012 Severity: Critical -- failure or failure imminent. Sprite New Command Bad Error. Termination Code: 04a92017 Severity: Critical -- failure or failure imminent. Uncorrectable Cache Memory EC C Error. Termination Code: 04aa2013 Severity: Critical -- failure or failure imminent. Sprite No Beginning-Of-Frame or Invalid Single Destination Error. Termination Code: 04ab2013 Severity: Critical -- failure or failure imminent. Sprite Transaction Length Mis Match Error. Termination Code: 04ac3913 Severity: Warning -- not failed but attention recommended or required. Sprite Tr ansaction Entry Read Parity Error.

Termination Code: 04ad0112 Severity: Critical -- failure or failure imminent. Sprite Bite-Count (BC) MisMat ch Error (Transaction BC != BC in FIFO). Termination Code: 04ae0112 Severity: Critical -- failure or failure imminent. Sprite Target Retry-Count Exc eeded Error. Termination Code: 04af0112 Severity: Critical -- failure or failure imminent. Sprite Initiator Retry-Count Exceeded Error. Termination Code: 04b00112 Severity: Critical -- failure or failure imminent. Sprite Split-Completion Count Exceeded Error. Termination Code: 04b10112 Severity: Critical -- failure or failure imminent. Sprite Split-Completion Error Message Received Error. Termination Code: 04b20112 Severity: Critical -- failure or failure imminent. Sprite UnExpected Split-Compl etion Error. Termination Code: 04b30112 Severity: Critical -- failure or failure imminent. Sprite Split-Completion Inval id Termination Error. Termination Code: 04b40112 Severity: Critical -- failure or failure imminent. Sprite Split-Completion Witho ut a Previous Split-Response Error. Termination Code: 04b52013 Severity: Critical -- failure or failure imminent. Sprite PCIX PERR Asserted Err or. Termination Code: 04b60113 Severity: Critical -- failure or failure imminent. Sprite performed a Master Abo rt Error. Termination Code: 04b72013 Severity: Critical -- failure or failure imminent. Sprite received a Target Abor t Error. Termination Code: 04b82014 Severity: Critical -- failure or failure imminent. Sprite asserted SERR. Termination Code: 04b92013 Severity: Critical -- failure or failure imminent. Sprite detected SERR. Termination Code: 04ba011c Severity: Critical -- failure or failure imminent. Tachyon Unsupported Byte Enab le Error. Termination Code: 04bb391c Severity: Warning -- not failed but attention recommended or required. Tachyon O utbound Parity Error. Termination Code: 04bc391c Severity: Warning -- not failed but attention recommended or required. Tachyon I

nbound Parity Error. Termination Code: 04bd201d Severity: Critical -- failure or failure imminent. Tachyon Detected Parity Error . Termination Code: 04be201d Severity: Critical -- failure or failure imminent. Tachyon Signaled System Error (SERR). Termination Code: 04bf011c Severity: Critical -- failure or failure imminent. Tachyon Received Master Abort Error. Termination Code: 04c0201d Severity: Critical -- failure or failure imminent. Tachyon Received Target Abort Error. Termination Code: 04c1201d Severity: Critical -- failure or failure imminent. Tachyon Signaled Target Abort Error. Termination Code: 04c2201d Severity: Critical -- failure or failure imminent. Tachyon Master Data Parity Er ror. Termination Code: 04c3011c Severity: Critical -- failure or failure imminent. Tachyon Unexpected Split-Comp letion Error. Termination Code: 04c4011c Severity: Critical -- failure or failure imminent. Tachyon Split-Completion Disc arded Error. Termination Code: 04c5391d Severity: Warning -- not failed but attention recommended or required. Tachyon P arity Error on Split Related Transaction. Termination Code: 04c6391d Severity: Warning -- not failed but attention recommended or required. Tachyon P arity Error on Incoming Data. Termination Code: 04c7391d Severity: Warning -- not failed but attention recommended or required. Tachyon P arity Error on Outgoing Data. Termination Code: 04c8201d Severity: Critical -- failure or failure imminent. Tachyon Attribute Parity Erro r. Termination Code: 04c9011c Severity: Critical -- failure or failure imminent. Tachyon Split-Completion Byte Count Excessive. Termination Code: 04ca011c Severity: Critical -- failure or failure imminent. Tachyon Read Byte Count Exces sive Error. Termination Code: 04cb011c Severity: Critical -- failure or failure imminent. Tachyon Read FIFO Parity Erro

r. Termination Code: 04cc011c Severity: Critical -- failure or failure imminent. Tachyon Write FIFO Parity Err or. Termination Code: 04cd011c Severity: Critical -- failure or failure imminent. Tachyon Reserved Region Acces s Error. Termination Code: 04ce010e Severity: Critical -- failure or failure imminent. Tachyon Parity Error on Split Completion Error. Termination Code: 04cf011b Severity: Critical -- failure or failure imminent. Undecoded machine check. Termination Code: 04d00180 Severity: Critical -- failure or failure imminent. Manufacturing Event Analysis Log Commit Packet unexpectedly in use. Termination Code: 04e2096a Severity: Warning -- not failed but attention recommended or required. Power fai led and was detected by the Offload PIC auxiliary processor. Termination Code: 04e3096a Severity: Warning -- not failed but attention recommended or required. The HSV45 0 controller was removed and detected by the Offload PIC auxiliary processor. Termination Code: 04e4096a Severity: Warning -- not failed but attention recommended or required. The syste m watchdog timer expired and was detected by the Offload PIC auxiliary processor . Termination Code: 04e5096a Severity: Warning -- not failed but attention recommended or required. An unknow n or unexpected event was detected and logged by the Offload PIC auxiliary proce ssor. Termination Code: 04e80100 Severity: Critical -- failure or failure imminent. The Sprite FPGA has failed ch ecksum verification. Termination Code: 04f6013f Severity: Critical -- failure or failure imminent. User termination test all par ameters. Termination Code: 04f70000 Severity: Normal -- informational in nature. Console requested restart with dump (not coupled) via CTRL-Z. Termination Code: 04f9017f Severity: Critical -- failure or failure imminent. Poweroff test. Termination Code: 04fa0100 Severity: Critical -- failure or failure imminent. User termination test no para meters. Termination Code: 04fb011f Severity: Critical -- failure or failure imminent. User termination test all par

ameters. Termination Code: 04fc0100 Severity: Critical -- failure or failure imminent. ISR termination test no param eters. Termination Code: 04fd011f Severity: Critical -- failure or failure imminent. ISR termination test all para meters. Termination Code: 04fe0100 Severity: Critical -- failure or failure imminent. Function not yet implemented. Termination Code: 04ff011f Severity: Critical -- failure or failure imminent. EXEC_BUGCHECK statement execu ted. Termination Code: 06040100 Severity: Critical -- failure or failure imminent. Failed memory allocation for SFQ. Termination Code: 06150100 Severity: Critical -- failure or failure imminent. Failed memory allocation for Fibre Channel Services Crash Dump structure. Termination Code: 061c0100 Severity: Critical -- failure or failure imminent. Failed memory allocation for IBQ. Termination Code: 06280100 Severity: Critical -- failure or failure imminent. Invalid Port Event Type. Termination Code: 06290100 Severity: Critical -- failure or failure imminent. Unknown FED type found. Termination Code: 062a0100 Severity: Critical -- failure or failure imminent. Unknown FED found during Link Down cleanup. Termination Code: 062b0100 Severity: Critical -- failure or failure imminent. Fail status returned for time r start. Termination Code: 062c0100 Severity: Critical -- failure or failure imminent. Unexpected loop state. Termination Code: 062f0100 Severity: Critical -- failure or failure imminent. SEST programming error. Termination Code: 06320100 Severity: Critical -- failure or failure imminent. Port chip failed to go Offlin e. Termination Code: 06330100 Severity: Critical -- failure or failure imminent. Out of Reserved FEDs. Termination Code: 06340100 Severity: Critical -- failure or failure imminent. Unsupported ELS requested. Termination Code: 06360100

Severity: Critical -- failure or failure imminent. Unsupported drive initializat ion sequence command. Termination Code: 063c0100 Severity: Critical -- failure or failure imminent. Command issued to an illegal LBA. Termination Code: 06480100 Severity: Critical -- failure or failure imminent. Failed memory allocation for Enclosure Management Request. Termination Code: 065a010e Severity: Critical -- failure or failure imminent. PMC-Sierra TSDK FC layer fail ed ASSERT. Termination Code: 07000100 Severity: Critical -- failure or failure imminent. Initialization failed due to insufficient memory. Termination Code: 07010100 Severity: Critical -- failure or failure imminent. LMAP allocation failed. Termination Code: 07020100 Severity: Critical -- failure or failure imminent. LMAP allocation failed. Termination Code: 07030100 Severity: Critical -- failure or failure imminent. Invalid RAID type. Termination Code: 07070100 Severity: Critical -- failure or failure imminent. Failed reading QS. Termination Code: 070a0100 Severity: Critical -- failure or failure imminent. RSD allocation failed. Termination Code: 070b0100 Severity: Critical -- failure or failure imminent. LDSB ref_count is off Termination Code: 070c0100 Severity: Critical -- failure or failure imminent. Invalid Object Class for I/O request. Termination Code: 070d0100 Severity: Critical -- failure or failure imminent. Invalid I/O range for given o bject. Termination Code: 07130100 Severity: Critical -- failure or failure imminent. Invalid RAID type. Termination Code: 07150100 Severity: Critical -- failure or failure imminent. Invalid structure - Zero proc ess. Termination Code: 07160100 Severity: Critical -- failure or failure imminent. Invalid structure - ODWORK p rocess. Termination Code: 07170100 Severity: Critical -- failure or failure imminent. Program buffer leak detected. Termination Code: 07190100

Severity: Critical -- failure or failure imminent. Code not yet implemented. Termination Code: 071a0102 Severity: Critical -- failure or failure imminent. Wrong LDSB returned to waitin g abort requester. Termination Code: 071b0100 Severity: Critical -- failure or failure imminent. Wrong LDAD returned to waitin g abort requester. Termination Code: 071c0100 Severity: Critical -- failure or failure imminent. Bad map type for read merge. Termination Code: 071d0100 Severity: Critical -- failure or failure imminent. Cache hit occurred while perf orming read merge. Termination Code: 071e0100 Severity: Critical -- failure or failure imminent. PSAR indicates invalid usage. Termination Code: 071f0100 Severity: Critical -- failure or failure imminent. Bad object class in Regen/Rep lace. Termination Code: 07200100 Severity: Critical -- failure or failure imminent. No Free CMAPs. Termination Code: 07220100 Severity: Critical -- failure or failure imminent. Invalid CS Drive Request. Termination Code: 07240100 Severity: Critical -- failure or failure imminent. No Free CS Req items. Termination Code: 07260100 Severity: Critical -- failure or failure imminent. Invalid Volnoid encountered. Termination Code: 072a0100 Severity: Critical -- failure or failure imminent. I/O Failed in CS_recover_tran sactions. Termination Code: 072b0100 Severity: Critical -- failure or failure imminent. Invalid Transaction type. Termination Code: 072d0100 Severity: Critical -- failure or failure imminent. No Transaction was found. Termination Code: 072f0100 Severity: Critical -- failure or failure imminent. Member State not supported in zero_rsdm. Termination Code: 07300100 Severity: Critical -- failure or failure imminent. Regen of Member should be com plete, but is not. Termination Code: 07340100 Severity: Critical -- failure or failure imminent. Bad CS Req Object Class in ha ndle CS Req. Termination Code: 07350100 Severity: Critical -- failure or failure imminent. Invalid CS Req Operation in h

andle CS Req. Termination Code: 07370100 Severity: Critical -- failure or failure imminent. Invalid Volnoid in Sparing Pr ocess. Termination Code: 07380100 Severity: Critical -- failure or failure imminent. No XDs available for cs_req o peration Termination Code: 07390100 Severity: Critical -- failure or failure imminent. Invalid Raid Type in Regen/Re assign. Termination Code: 073b0100 Severity: Critical -- failure or failure imminent. Unknown CS Transaction type f or Journaling. Termination Code: 073c0100 Severity: Critical -- failure or failure imminent. CS Journal Transaction incons istency. Termination Code: 073e0100 Severity: Critical -- failure or failure imminent. Invalid structure - LD Level ing process. Termination Code: 073f0100 Severity: Critical -- failure or failure imminent. Invalid structure - RStore S paring process. Termination Code: 07400100 Severity: Critical -- failure or failure imminent. Invalid structure - CS Req p rocess. Termination Code: 07410100 Severity: Critical -- failure or failure imminent. Invalid structure - PLDMC pr ocess. Termination Code: 07420100 Severity: Critical -- failure or failure imminent. No Free RLBs (RSD Lock Blocks ). Termination Code: 07430100 Severity: Critical -- failure or failure imminent. RLB List is inconsistent. Termination Code: 07440100 Severity: Critical -- failure or failure imminent. RLB state is inconsistent. Termination Code: 07450100 Severity: Critical -- failure or failure imminent. Invalid structure - CS CSLD process. Termination Code: 07460100 Severity: Critical -- failure or failure imminent. Invalid structure - CS E-bit handler. Termination Code: 07480100 Severity: Critical -- failure or failure imminent. Illegal QS I/O by Non Storage System Master.

Termination Code: 07490100 Severity: Critical -- failure or failure imminent. Illegal CSLD I/O by Non Stora ge System Master. Termination Code: 074a0100 Severity: Critical -- failure or failure imminent. Invalid structure - ACBW pro cess. Termination Code: 074b0100 Severity: Critical -- failure or failure imminent. Invalid ACBW Opcode. Termination Code: 074c0100 Severity: Critical -- failure or failure imminent. Invalid structure - Unsharing process. Termination Code: 074f0100 Severity: Critical -- failure or failure imminent. Invalid structure - RSS Migr ation process. Termination Code: 07500100 Severity: Critical -- failure or failure imminent. Invalid structure - RStore M igration process. Termination Code: 07510100 Severity: Critical -- failure or failure imminent. Member State not supported. Termination Code: 07520100 Severity: Critical -- failure or failure imminent. Metadata is inaccessible; an inoperative condition has occurred. Termination Code: 07530100 Severity: Critical -- failure or failure imminent. An invalid structure was enco untered on an ALB list. Termination Code: 07540114 Severity: Critical -- failure or failure imminent. LMAP does not point to RStore , and RStore not being allocated. Termination Code: 07550100 Severity: Critical -- failure or failure imminent. Invalid structure - LD Alloc ation work process. Termination Code: 07570100 Severity: Critical -- failure or failure imminent. Realize or realize_temp faile d. Termination Code: 07580100 Severity: Critical -- failure or failure imminent. Unrealize or unrealize_temp f ailed. Termination Code: 075a0100 Severity: Critical -- failure or failure imminent. Force a crash for testing pur poses. Termination Code: 075b0104 Severity: Critical -- failure or failure imminent. Metadata I/O failed. Termination Code: 075d0100 Severity: Critical -- failure or failure imminent. Invalid structure - CS C-bit handler.

Termination Code: 075e0100 Severity: Critical -- failure or failure imminent. Invalid structure - OD bg alo c process. Termination Code: 075f0100 Severity: Critical -- failure or failure imminent. DUB and RSS do not agree with each other. Termination Code: 07600100 Severity: Critical -- failure or failure imminent. Invalid LD type Termination Code: 07610100 Severity: Critical -- failure or failure imminent. Invalid DIP State in LD Termination Code: 07620100 Severity: Critical -- failure or failure imminent. Deallocation failed Termination Code: 07630100 Severity: Critical -- failure or failure imminent. Failure to validate reserved capacity on each rss member Termination Code: 07640100 Severity: Critical -- failure or failure imminent. Invalid structure - REBUILD PARITY MAIN Termination Code: 07650100 Severity: Critical -- failure or failure imminent. An unexpected status was retu rned to the caller Termination Code: 07680100 Severity: Critical -- failure or failure imminent. An RSS member has been remove d unexpectedly. Termination Code: 07690102 Severity: Critical -- failure or failure imminent. An unsupported member manager state has occurred. Termination Code: 076a0100 Severity: Critical -- failure or failure imminent. No Quorum Disks have been dis covered. Termination Code: 076b0100 Severity: Critical -- failure or failure imminent. Invalid/unknown pseg allocati on type Termination Code: 076c0100 Severity: Critical -- failure or failure imminent. XMFC Failure - other controll er gone during communication with it. Termination Code: 076d0100 Severity: Critical -- failure or failure imminent. Invalid XMFC operation. Termination Code: 07700105 Severity: Critical -- failure or failure imminent. CHKDSK test failed Termination Code: 07710100 Severity: Critical -- failure or failure imminent. Invalid structure - Unsharing process.

Termination Code: 07720100 Severity: Critical -- failure or failure imminent. Invalid structure - Unsharing process. Termination Code: 07730100 Severity: Critical -- failure or failure imminent. The RSD pointer should have b een NULL but wasn't Termination Code: 0775011a Severity: Critical -- failure or failure imminent. The LD should have not been r ealized but was Termination Code: 07760120 Severity: Critical -- failure or failure imminent. Force a crash for testing pur poses without an ILF dump. Termination Code: 08010100 Severity: Critical -- failure or failure imminent. Bad status from CS_SET_EBIT Termination Code: 08020100 Severity: Critical -- failure or failure imminent. An abnormal member's member_s tate is not supported Termination Code: 08030100 Severity: Critical -- failure or failure imminent. A request was made to do I/O for an undefined RAID type. Termination Code: 08040100 Severity: Critical -- failure or failure imminent. Drive rewrite function is not supported Termination Code: 08070100 Severity: Critical -- failure or failure imminent. Cannot dynamically allocate e nough memory to store waiters for ptr 9687 fix. Termination Code: 08080100 Severity: Critical -- failure or failure imminent. Unsupported structure type pa ssed into RS function Termination Code: 08110120 Severity: Critical -- failure or failure imminent. Force a crash for testing pur poses without an ILF dump. Termination Code: 09010100 Severity: Critical -- failure or failure imminent. EXEC_init_bque failed. Termination Code: 09040100 Severity: Critical -- failure or failure imminent. Storage System Management Int erface detected an internal inconsistency. Termination Code: 09060100 Severity: Critical -- failure or failure imminent. Memory allocation failed for return buffer. Termination Code: 09080100 Severity: Critical -- failure or failure imminent. Insufficient resources availa ble for SCMI Command Lock dynamic allocation. Termination Code: 09090100 Severity: Critical -- failure or failure imminent. Insufficient resources availa

ble for SCMI Command Lock initial allocation. Termination Code: 0b000100 Severity: Critical -- failure or failure imminent. Invalid XMFC Response Packet. Termination Code: 0b010100 Severity: Critical -- failure or failure imminent. Invalid MFC Vector (Index). Termination Code: 0b020100 Severity: Critical -- failure or failure imminent. Invalid System Activity Colle ction state. Termination Code: 0b040100 Severity: Critical -- failure or failure imminent. Invalid System Utility (Code Load or Resynchronization) state. Termination Code: 0b052001 Severity: Critical -- failure or failure imminent. Attempt to access EEPROM for UUID Range failed. Termination Code: 0b062001 Severity: Critical -- failure or failure imminent. UUID Range overflow. Termination Code: 0b080100 Severity: Critical -- failure or failure imminent. A resynchronization was reque sted at an inappropriate time. Termination Code: 0b092003 Severity: Critical -- failure or failure imminent. Attempt to access Operator Co ntrol Panel failed. Termination Code: 0b0a0100 Severity: Critical -- failure or failure imminent. Invalid XMFC State. Termination Code: 0b0f0122 Severity: Critical -- failure or failure imminent. File is larger than predefine d code load buffer. Termination Code: 0b100021 Severity: Normal -- informational in nature. New glue code available, attempting a force load which requires a restart after the load is successful. Termination Code: 0b110020 Severity: Normal -- informational in nature. New boot code available, attempting a force load following restart. Termination Code: 0b130021 Severity: Normal -- informational in nature. New sprite code available, attempti ng a force load which requires a restart after the load is successful. Termination Code: 0b140021 Severity: Normal -- informational in nature. New glue and sprite code available, attempting a force load which requires two back to back restarts, one for each image. One successful load flowing into the next load. Glue first then sprite. Termination Code: 0b150020 Severity: Normal -- informational in nature. Allow optional parts to be loaded d uring this resync/restart because the slave controller has not yet joined the sc ell.

Termination Code: 0b16f060 Severity: Warning -- not failed but attention recommended or required. Attempt t o load code that can not handle single rank dimms on a controller with single ra nk dimms installed. Please upgrade to code that is capable of supporting single rank dimms. Termination Code: 0c010102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t command. Termination Code: 0c03010e Severity: Critical -- failure or failure imminent. Invalid state exists for dele ting a Group State Block. Termination Code: 0c040101 Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: The group sequ ence number node already exists. Termination Code: 0c050106 Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: The recovery w rite data was not in cache as expected. Termination Code: 0c060106 Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: The recovery w rite data found in cache was not marked dirty write-back cached data as expected . Termination Code: 0c070106 Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: Lookup of grou p sequence number node failed. Termination Code: 0c080106 Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the mirror cache when the mirror was declared invalid: A recovery write was found, but its associated RIE was no t marked free as expected. Termination Code: 0c090106 Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the mirror cache when the mirror was declared invalid: Not all group members were processed. Termination Code: 0c0a0106 Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the primary cache when the prima ry was declared invalid: A recovery write was found, but its associated RIE was not marked free as expected. Termination Code: 0c0b0106 Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the primary cache when the prima ry was declared invalid: Not all group members were processed. Termination Code: 0c0c0104 Severity: Critical -- failure or failure imminent. A software problem was found

when deleting the Group State Block: Transfers were not completely run down. Termination Code: 0c0d0104 Severity: Critical -- failure or failure imminent. A software problem was found when inserting a Group State Block into the active list: A Group State Block wit h this same Universal Unique Identifier is already on the active list. Termination Code: 0c0e0106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order was detected in the transfer path upon remote write completion after the mirror controller was updated; A Full Copy of the affected Data Replication Gro up may be initiated upon the next controller restart. Termination Code: 0c0f0105 Severity: Critical -- failure or failure imminent. Setting the e-bit failed for a write long command on the destination unit. Termination Code: 0c110105 Severity: Critical -- failure or failure imminent. A Group Sequence Number Node was lost during mirror synchronization. Termination Code: 0c130105 Severity: Critical -- failure or failure imminent. An unexpected I/O failure occ urred: Container Services was unable to write to the PLDMC on media. Termination Code: 0c140106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order was detected in the transfer path on the mirror side upon remote write c ompletion; A Full Copy of the affected Data Replication Group may be initiated u pon controller restart. Termination Code: 0c150106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order was detected upon controller restart or failover when building the list of incomplete writes; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c160106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order was detected upon controller restart or failover when completing previou sly incomplete writes; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c170106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the received group sequence number was detected after a controller restarted, when synchonizing the group sequence numbers with the mirror side; A Full Copy of the affected Data Replication Group may be initiated upon controlle r restart. Termination Code: 0c180106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use and sent group sequence numbers was detected after a contro ller restarted, when synchronizing the group sequence numbers with the mirror si de; A Full Copy of the affected Data Replication Group may be initiated upon con troller restart. Termination Code: 0c190106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the received group sequence number was detected after a controller

restarted, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon control ler restart. Termination Code: 0c1a0106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use and sent group sequence number was detected after a control ler restart, when synchronizing the group sequence numbers with the primary side ; A Full Copy of the affected Data Replication Group may be initiated upon contr oller restart. Termination Code: 0c1b0106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use group sequence number was detected after a controller resta rt, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller res tart. Termination Code: 0c1c0107 Severity: Critical -- failure or failure imminent. A group sequence number out o f order was detected after a controller restart when synchronizing the mirror wr ites with the primary side; A Full Copy of the affected Data Replication Group m ay be initiated upon controller restart. Termination Code: 0c200106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use group sequence number was detected after a controller resta rt, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller res tart. Termination Code: 0c210113 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use group sequence number was detected to be too high; A Full C opy of the affected Data Replication Group may be initiated upon controller rest art. Termination Code: 0c220108 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use group sequence number was detected to be too low; A Full Co py of the affected Data Replication Group may be initiated upon controller resta rt. Termination Code: 0c230108 Severity: Critical -- failure or failure imminent. A Data Replication Group memb er was detected to be in an unexpected cache state. Termination Code: 0c240107 Severity: Critical -- failure or failure imminent. Secondary controller selectio n failed. Termination Code: 0c270106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use group sequence number was detected to be too low. A Full Co py of the affected Data Replication Group may be initiated upon controller resta rt. Termination Code: 0c280106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use group sequence number was detected to be too low. A Full Co

py of the affected Data Replication Group may be initiated upon controller resta rt. Termination Code: 0c290105 Severity: Critical -- failure or failure imminent. Data Replication Manager Dual State was not idle for MFC communication between the dual controllers during an add member operation. Termination Code: 0c2a0106 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t ADD SOURCE command. Termination Code: 0c2b0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t command when a process is waiting for the ACK. Termination Code: 0c2c0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t command when a process is waiting for a DONE response. Termination Code: 0c2d0105 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while creating an ADD SOURCE dual controller management command. Termination Code: 0c2e0105 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while creating an SITE FAILOVER dual controller managem ent command. Termination Code: 0c2f0106 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t command requiring a DRRW response. Termination Code: 0c300105 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while creating a multi-destinaton dual controller manag ement command. Termination Code: 0c310105 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while creating a dual controller management command tha t has only an ACK as a response and passes a group object as a parameter. Termination Code: 0c320101 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found in the main dispatch function for dual controller manag ement commands. Termination Code: 0c330103 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found in the main processing function for dual controller man agement commands. Termination Code: 0c360102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana

ger Dual State was found while issuing a simple dual controller management comma nd. Termination Code: 0c370102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing the response to a simple dual controll er management command. Termination Code: 0c380102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while building a simple dual controller management comm and. Termination Code: 0c390102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while building a dual controller management command whi ch uses an SCVD object. Termination Code: 0c3a0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a unit related dual control ler management command that does not require an additional response. Termination Code: 0c3b0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a unit related dual control ler management command that requires an additional response. Termination Code: 0c410102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while initiating a site failover. Termination Code: 0c420102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t synchronize buffers command. Termination Code: 0c430102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t MDW command. Termination Code: 0c450100 Severity: Critical -- failure or failure imminent. We should not have gone down this path. Termination Code: 0c460103 Severity: Critical -- failure or failure imminent. MFC frame corruption detected . Termination Code: 0c480100 Severity: Critical -- failure or failure imminent. Insufficient free memory avai lable to allocate required DDCB structures. Termination Code: 0c490100 Severity: Critical -- failure or failure imminent. Insufficient free memory avai lable to allocate required RNSB structures. Termination Code: 0c4b0100 Severity: Critical -- failure or failure imminent. Insufficient free memory avai

lable to allocate required Data Replication Manager Discovery structures. Termination Code: 0c4c0100 Severity: Critical -- failure or failure imminent. Invalid DRM MFC Vector (Index ). Termination Code: 0c4d0100 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger RXMFC Response Packet. Termination Code: 0c4e0106 Severity: Critical -- failure or failure imminent. Invalid RNSB pointer detected in DDCB. Termination Code: 0c4f0101 Severity: Critical -- failure or failure imminent. Insufficient free memory avai lable to allocate required Data Replication Manager communications structures. Termination Code: 0c500106 Severity: Critical -- failure or failure imminent. A group sequence number for a write command that has already completed has been received. A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0e000020 Severity: Normal -- informational in nature. Found invalid battery subsystem sta te. Termination Code: 0e010020 Severity: Normal -- informational in nature. Found invalid battery system hold u p time. Termination Code: 0e020020 Severity: Normal -- informational in nature. Found invalid battery brick number. Termination Code: 0e030020 Severity: Normal -- informational in nature. Found invalid battery brick state. Termination Code: 0e050020 Severity: Normal -- informational in nature. Found invalid blower number. Termination Code: 0e060020 Severity: Normal -- informational in nature. Found invalid blower state. Termination Code: 0e080020 Severity: Normal -- informational in nature. Found invalid temperature subsystem state. Termination Code: 0e090020 Severity: Normal -- informational in nature. Found invalid power supply number. Termination Code: 0e0a0020 Severity: Normal -- informational in nature. Found invalid power supply state. Termination Code: 0e0b0020 Severity: Normal -- informational in nature. A command was sent to the SDC micro controller while it was still busy processing a previous command. Termination Code: 0f000100 Severity: Critical -- failure or failure imminent. A DMA transaction completed w ith an interrupt but the DMA context queue was empty.

Termination Code: 0f010101 Severity: Critical -- failure or failure imminent. The DMA context queue is out of sync with interrupts. Termination Code: 0f020100 Severity: Critical -- failure or failure imminent. Unable to save DMA context be cause the queue is full. Termination Code: 0f100100 Severity: Critical -- failure or failure imminent. A DMA transaction followed an unsupported code path. Termination Code: 0f110100 Severity: Critical -- failure or failure imminent. A call to EXEC_allocate retur ned a NULL pointer. Termination Code: 0f150102 Severity: Critical -- failure or failure imminent. Target Read Entry header addr ess bad. Termination Code: 0f160101 Severity: Critical -- failure or failure imminent. Unknown FED type found. Termination Code: 0f170100 Severity: Critical -- failure or failure imminent. Fail status returned for time r start. Termination Code: 0f18011f Severity: Critical -- failure or failure imminent. FED for handling MFC ACK was not on the In-process Queue as expected. Termination Code: 0f190100 Severity: Critical -- failure or failure imminent. Failed memory allocation for MFC copy buffer. Termination Code: 0f1a0100 Severity: Critical -- failure or failure imminent. Failed memory allocation for SFQ. Termination Code: 0f1b0100 Severity: Critical -- failure or failure imminent. Failed memory allocation for ELSDs. Termination Code: 0f1e0100 Severity: Critical -- failure or failure imminent. Failed memory allocation for IBQ. Termination Code: 0f1f0101 Severity: Critical -- failure or failure imminent. Invalid Port Event Type. Termination Code: 0f200100 Severity: Critical -- failure or failure imminent. Out of Reserved FEDs. Termination Code: 0f210100 Severity: Critical -- failure or failure imminent. Invalid Completion Message ty pe. Termination Code: 0f220100 Severity: Critical -- failure or failure imminent. SEST programming error.

Termination Code: 0f230100 Severity: Critical -- failure or failure imminent. Class 2 Failure for outbound sequence. Termination Code: 0f24011f Severity: Critical -- failure or failure imminent. Host Programming error. Termination Code: 0f250080 Severity: Normal -- informational in nature. Remote couple crash requested. Termination Code: 0f260100 Severity: Critical -- failure or failure imminent. Unsupported ELS requested. Termination Code: 0f270100 Severity: Critical -- failure or failure imminent. Sprite returned an error that we don't know how to handle yet Termination Code: 0f280100 Severity: Critical -- failure or failure imminent. Sprite CDB memory has been co rrupted Termination Code: 0f290101 Severity: Critical -- failure or failure imminent. Unknown FED found during Link Down cleanup. Termination Code: 0f2b0100 Severity: Critical -- failure or failure imminent. Unexpected loop state. Termination Code: 0f2c0100 Severity: Critical -- failure or failure imminent. Unknown exchange type found. Termination Code: 0f2d0106 Severity: Critical -- failure or failure imminent. Invalid port login state in r emote port object. Termination Code: 0f2e0105 Severity: Critical -- failure or failure imminent. Remote port logged_in timer e xpired in inappropriate login state. Termination Code: 0f2f0dc6 Severity: Critical -- failure or failure imminent. The two controllers do not ha ve matching Cache or Policy memory configurations. Replace a controller so that both controllers match. Termination Code: 42000101 Severity: Critical -- failure or failure imminent. No memory for HP_init. Termination Code: 42050103 Severity: Critical -- failure or failure imminent. Unexpected Cache Node lock st ate for WRITE LONG. Termination Code: 42060105 Severity: Critical -- failure or failure imminent. Unexpected outstanding SCSI c ommand on unit. Termination Code: 42070123 Severity: Critical -- failure or failure imminent. DD CDB function 0X42 received .

Termination Code: 420801a3 Severity: Critical -- failure or failure imminent. DD CDB function 0X43 received . Termination Code: 420901c3 Severity: Critical -- failure or failure imminent. DD CDB function 0X86 received . Termination Code: 420c0184 Severity: Critical -- failure or failure imminent. Unknown build context receive d in remote SCSI MFC build routine. Termination Code: 420d0182 Severity: Critical -- failure or failure imminent. Unknown context received in r emote SCSI MFC receive routine. Termination Code: 420e0181 Severity: Critical -- failure or failure imminent. ICOPS could not allocate nece ssary memory. Termination Code: 420f0182 Severity: Critical -- failure or failure imminent. Unknown build context in the ICOPS build routine. Termination Code: 42100182 Severity: Critical -- failure or failure imminent. Unknown receive context in th e ICOPS receive routine. Termination Code: 42120104 Severity: Critical -- failure or failure imminent. Illegal structure on in proce ss queue. Termination Code: 42130101 Severity: Critical -- failure or failure imminent. No host port command HTBs. Termination Code: 42140102 Severity: Critical -- failure or failure imminent. Invalid Context in hp_call_ge t_scsi_data. Termination Code: 42150102 Severity: Critical -- failure or failure imminent. HP_change_host_mode ACB-- not found. Termination Code: 42160102 Severity: Critical -- failure or failure imminent. HP_present_lun-- ACB not foun d. Termination Code: 42190104 Severity: Critical -- failure or failure imminent. CCB either already in use or improperly marked not used. Termination Code: 421a0183 Severity: Critical -- failure or failure imminent. An HTB has an invalid NULL fl ow value. Termination Code: 421b0102 Severity: Critical -- failure or failure imminent. A work request has an invalid type. Termination Code: 421c0101

Severity: Critical -- failure or failure imminent. Work request resources have r un out. Termination Code: 421e0102 Severity: Critical -- failure or failure imminent. Allocated command HTB is alre ady in use. Termination Code: 42230102 Severity: Critical -- failure or failure imminent. HP_unpresent_lun ACB not foun d. Termination Code: 42250104 Severity: Critical -- failure or failure imminent. Could not delete the ACB. Termination Code: 42260104 Severity: Critical -- failure or failure imminent. Did not have a Unit Attention table and units are presented. Termination Code: 42270108 Severity: Critical -- failure or failure imminent. Port event handler had an unk nown port event. Termination Code: 42280102 Severity: Critical -- failure or failure imminent. Unknown completion message fr om the Tachyon. Termination Code: 42290103 Severity: Critical -- failure or failure imminent. Received an illegal SEST id. Termination Code: 422c0003 Severity: Normal -- informational in nature. Received an unknown error idle stat us from the Tachyon. Termination Code: 422d010a Severity: Critical -- failure or failure imminent. Received an unknown I/O error value. Termination Code: 422e0104 Severity: Critical -- failure or failure imminent. Had a LUN with write only acc ess. Termination Code: 422f0103 Severity: Critical -- failure or failure imminent. Received an unknown FCP inbou nd completion status. Termination Code: 42300103 Severity: Critical -- failure or failure imminent. Received an illegal script re sponse. Termination Code: 42310102 Severity: Critical -- failure or failure imminent. Received an illegal error sta tus in the error routine. Termination Code: 42320104 Severity: Critical -- failure or failure imminent. Requested to present a LUN th at is already in existence or is illegal Termination Code: 4233010a Severity: Critical -- failure or failure imminent. An internal request was made to return a status of Not Ready for work created in the controller.

Termination Code: 42340104 Severity: Critical -- failure or failure imminent. The state for a command with the Immed bit set in the CDB is incorrect. Termination Code: 42350104 Severity: Critical -- failure or failure imminent. A unit unquiesce was called w ithout the corresponding quiesce. Termination Code: 42360102 Severity: Critical -- failure or failure imminent. A call to notify of new ELP e ncountered an invalid CSEL state. Termination Code: 42370183 Severity: Critical -- failure or failure imminent. Gap in Sequence Numbers for E vent Logs. Termination Code: 4238011f Severity: Critical -- failure or failure imminent. The host port has detected a CSM reset after 60 minutes. Termination Code: 42390184 Severity: Critical -- failure or failure imminent. Invalid proxy io operation st ate Termination Code: 423a0102 Severity: Critical -- failure or failure imminent. Logical port number out of ra nge to access S_pcb[] Termination Code: 423b0102 Severity: Critical -- failure or failure imminent. The tachyon chip is not respo nding. The controller will be restarted so that diagnostics can be executed. Termination Code: 423e0107 Severity: Critical -- failure or failure imminent. Host Transaction Block on fre e queue is not marked free. Termination Code: 423f010c Severity: Critical -- failure or failure imminent. Host Transaction Block freed twice Termination Code: 42400104 Severity: Critical -- failure or failure imminent. HP_present_lun-- Lun, via lut _idx yielded VDSB NULL, Not yet set. Termination Code: 42410106 Severity: Critical -- failure or failure imminent. HTB incorrectly linked or mis sing from queue. Termination Code: 42420105 Severity: Critical -- failure or failure imminent. Illegal structure on connecti on pending queue. Termination Code: 83002061 Severity: Critical -- failure or failure imminent. DOG cannot branch to this rou tine. Termination Code: 83012079 Severity: Critical -- failure or failure imminent. DOG unexpected vector to erro r.

Termination Code: 8302206c Severity: Critical -- failure or failure imminent. DOG non-fault tolerant hard e rror. Termination Code: 84032069 Severity: Critical -- failure or failure imminent. Excessive correctable errors have been seen in cache memory. Termination Code: 84042065 Severity: Critical -- failure or failure imminent. Excessive correctable errors have been seen in policy memory. EVENT INFORMATION PACKETS: Event Information Packet Type: 1 EIP01 - Fault Manager Termination Processing Recursive Entry Event A machine check occurred while a termination event was being processed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)}

<byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> union hdu Termination Event Information Header <byte 76> {lteihd (Active if Termination Event Information Header revision is greater than 3)} <byte 76> {flags (Last Termination Event flags)} <byte 76> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 rsvd Pad to fill byte tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 77> utiny revision Structure revision number <byte 78> ushort size Structure size {} or hdu Termination Event Information Header <byte 76> {lteihd0 (Active if Termination Event Information Header revision is less than o r equal to 3)} <byte 76> {flags (Last Termination Event flags)} <byte 76> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved

{} <byte 77> utiny revision Structure revision number <byte 78> ushort size Structure size {} endunion hdu Termination Event Information Header <byte 80> union ru Termination Event Reporting Information <byte 80> {lter (Active if Termination Event Information Header revision greater than 3)} <byte 80> ulong seq Sequence number assigned to the termination event <byte 84> char[8] sw_version HSV450 controller software version number string <byte 92> char[12] baselevel_id HSV450 controller baselevel build string <byte 104> char[8] ctrlr_model_id HSV450 controller model string <byte 112> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV 450 controller that terminated operation <byte 132> scmitim termination_time Time termination event occurred <byte 140> {termination_event (Termination event information)} <byte 140> ulong termination_location Location of termination event report call <byte 144> union u Termination Code Union <byte 144> {code (Termination Code)} <byte 144> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 145> cacode cac Corrective Action Code <byte 146> utiny evnum Event Number <byte 147> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 144> ulong value Termination Code Value endunion u Termination Code Union {} <byte 148> utiny[2] reserved Reserved <byte 150> {flags (Other Last Termination Event flags)} <byte 150> tbits:1 lg_send_sts Last Gasp send status tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved tbits:3 rsvd Pad to fill byte {}

<byte 151> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected nt array index <byte 152> ulonglong uptime Number of seconds HSV450 controller has run functional code {} or ru Termination Event Reporting Information <byte 80> {lter0 (Active if Termination Event Information Header revision is less than equal to 3)} <byte 80> ulong seq Sequence number assigned to the termination event <byte 84> char[4] sw_version HSV450 controller software version number string <byte 88> char[12] baselevel_id HSV450 controller baselevel build string <byte 100> char[8] ctrlr_model_id HSV450 controller model string <byte 108> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of 450 controller that terminated operation <byte 128> scmitim termination_time Time termination event occurred <byte 136> {termination_event (Termination event information)} <byte 136> ulong termination_location Location of termination event report call <byte 140> union u Termination Code Union <byte 140> {code (Termination Code)} <byte 140> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 141> cacode cac Corrective Action Code <byte 142> utiny evnum Event Number <byte 143> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 140> ulong value Termination Code Value endunion u Termination Code Union {} <byte 144> utiny[2] reserved Reserved <byte 146> utiny lg_send_sts Last Gasp send status <byte 147> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected nt array index <byte 148> ulonglong uptime Number of seconds HSV450 controller has run functional code {} <byte 156> do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) endunion ru Termination Event Reporting Information

Eve

or

HSV

Eve

<byte 160> {rei (Recursive Entry Event Information)} <byte 160> ulong tt Trap type <byte 164> ulong tc Termination code <byte 168> ulong srr0 SRR0 register <byte 172> ulong lr LR register <byte 176> ulong exception Exception code {} {} Event Information Packet Type: 2 EIP02 - Fault Manager Termination Processing Unexpected Event An unexpected event occurred while a termination event was being processed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)}

<byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> union hdu Termination Event Information Header <byte 76> {lteihd (Active if Termination Event Information Header revision is greater than 3)} <byte 76> {flags (Last Termination Event flags)} <byte 76> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 rsvd Pad to fill byte tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 77> utiny revision Structure revision number <byte 78> ushort size Structure size {} or hdu Termination Event Information Header <byte 76> {lteihd0 (Active if Termination Event Information Header revision is less than o r equal to 3)} <byte 76> {flags (Last Termination Event flags)} <byte 76> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved

{} <byte 77> utiny revision Structure revision number <byte 78> ushort size Structure size {} endunion hdu Termination Event Information Header <byte 80> union ru Termination Event Reporting Information <byte 80> {lter (Active if Termination Event Information Header revision greater than 3)} <byte 80> ulong seq Sequence number assigned to the termination event <byte 84> char[8] sw_version HSV450 controller software version number string <byte 92> char[12] baselevel_id HSV450 controller baselevel build string <byte 104> char[8] ctrlr_model_id HSV450 controller model string <byte 112> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV 450 controller that terminated operation <byte 132> scmitim termination_time Time termination event occurred <byte 140> {termination_event (Termination event information)} <byte 140> ulong termination_location Location of termination event report call <byte 144> union u Termination Code Union <byte 144> {code (Termination Code)} <byte 144> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 145> cacode cac Corrective Action Code <byte 146> utiny evnum Event Number <byte 147> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 144> ulong value Termination Code Value endunion u Termination Code Union {} <byte 148> utiny[2] reserved Reserved <byte 150> {flags (Other Last Termination Event flags)} <byte 150> tbits:1 lg_send_sts Last Gasp send status tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved tbits:3 rsvd Pad to fill byte {}

<byte 151> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected nt array index <byte 152> ulonglong uptime Number of seconds HSV450 controller has run functional code {} or ru Termination Event Reporting Information <byte 80> {lter0 (Active if Termination Event Information Header revision is less than equal to 3)} <byte 80> ulong seq Sequence number assigned to the termination event <byte 84> char[4] sw_version HSV450 controller software version number string <byte 88> char[12] baselevel_id HSV450 controller baselevel build string <byte 100> char[8] ctrlr_model_id HSV450 controller model string <byte 108> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of 450 controller that terminated operation <byte 128> scmitim termination_time Time termination event occurred <byte 136> {termination_event (Termination event information)} <byte 136> ulong termination_location Location of termination event report call <byte 140> union u Termination Code Union <byte 140> {code (Termination Code)} <byte 140> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 141> cacode cac Corrective Action Code <byte 142> utiny evnum Event Number <byte 143> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 140> ulong value Termination Code Value endunion u Termination Code Union {} <byte 144> utiny[2] reserved Reserved <byte 146> utiny lg_send_sts Last Gasp send status <byte 147> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected nt array index <byte 148> ulonglong uptime Number of seconds HSV450 controller has run functional code {} <byte 156> do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) endunion ru Termination Event Reporting Information

Eve

or

HSV

Eve

<byte 160> {uei (Unexpected Event Information)} <byte 160> ulong type Unexpected event type <byte 164> ulong pto Post-Termination Operation Indicator <byte 168> ulong[5] param Unexpected event parameters {} {} Event Information Packet Type: 3 EIP03 - Fault Manager Management Event An event that affects Fault Manager operation occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code

<byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> union ainfo Ancillary Information Union <byte 76> ulong events_not_reported Number of events not reported <byte 80> do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) or ainfo Ancillary Information Union <byte 76> ulong quiesce_type Quiesce type <byte 80> do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) or ainfo Ancillary Information Union <byte 76> {remote_event (Remote event header information)} <byte 76> union u Event Code Union <byte 76> {ec (Event Code)} <byte 76> utiny eiptype Event Information Packet Type Code <byte 77> cacode cac Corrective Action Code <byte 78> utiny evnum Event Number <byte 79> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 76> ulong value Event Code Value endunion u Event Code Union <byte 80> utiny revision Packet revision number <byte 81> utiny type Packet type <byte 82> ushort count Number of bytes in packet {} endunion ainfo Ancillary Information Union <byte 84> union cinfo Control Block Information Union <byte 84> {scelcbi (Storage System Event Log Control Block Information)} <byte 84>

ushort current_offset Current offset within event buffer <byte 86> {flags (Flags)} <byte 86> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Sequence number reset occurred tbits:1 wrapped All event data blocks in use tbits:4 rsvd Pad to fill byte {} <byte 87> utiny status Maintenance status <byte 88> ulong current_edbn Current event data block number <byte 92> ulong start_edbn Storage System State Logical Disk-Storage System Event Log star ting event data block number <byte 96> ulong end_edbn Storage System State Logical Disk-Storage System Event Log ending event data block number <byte 100> ulong seq_reset_edbn Event data block number where sequence number reset occurre d <byte 104> ulong event_count Number of events contained in Storage System State Logical Dis k-Storage System Event Log <byte 108> ulong event_count_wraps Event count overflow <byte 112> ulong sequence_number Last event sequence number used {} <byte 116> do_not_display[12] union_pad Union Element Padding (DO NOT DISPLAY!) or cinfo Control Block Information Union <byte 84> {sctelcbi (Storage System Termination Event Log Control Block Information)} <byte 84> ushort reserved Reserved for future use <byte 86> {flags (Flags)} <byte 86> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 bctrlr_wrapped All termination event data blocks in use for 'B' HSV450 c ontroller tbits:1 bctrlr_valid 'B' HSV450 controller's Storage System State Logical Disk-S torage System Termination Event Log information is valid tbits:1 actrlr_wrapped All termination event data blocks in use for 'A' HSV450 c ontroller tbits:1 actrlr_valid 'A' HSV450 controller's Storage System State Logical Disk-S torage System Termination Event Log information is valid tbits:2 rsvd Pad to fill byte {} <byte 87> utiny status Maintenance status <byte 88> uuid actrlr_id 'A' HSV450 controller's UUID <byte 104>

ulong actrlr_mru_edbn 'A' HSV450 controller's Storage System State Logical DiskStorage System Termination Event Log most recently used event data block number <byte 108> uuid bctrlr_id 'B' HSV450 controller's UUID <byte 124> ulong bctrlr_mru_edbn 'B' HSV450 controller's Storage System State Logical DiskStorage System Termination Event Log most recently used event data block number {} or cinfo Control Block Information Union <byte 84> {stats30 (Last 30 seconds activity summary)} <byte 84> {host (Host Activity,)} <byte 84> ulong rps Requests Per Second, <byte 88> ulong kbs KB/Second. {} <byte 92> {mirror (Mirror Activity,)} <byte 92> ulong rps Requests Per Second, <byte 96> ulong kbs KB/Second. {} <byte 100> {backend (Backend Activity,)} <byte 100> ulong rps Requests Per Second, <byte 104> ulong kbs KB/Second. {} <byte 108> {total (Total Activity,)} <byte 108> ulong rps Requests Per Second, <byte 112> ulong kbs KB/Second. {} <byte 116> {background (Background Activity.)} <byte 116> ulong rps Requests Per Second, <byte 120> ulong kbs KB/Second. {} {} <byte 124> do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) or cinfo Control Block Information Union <byte 84> {mealcbi (Manufacturing Event Analysis Log Control Block information)} <byte 84> ushort current_offset Current offset within event buffer <byte 86> {flags (Flags)} <byte 86> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System

tbits:1 seq_reset Sequence number reset occurred tbits:1 wrapped All event data blocks in use tbits:4 rsvd Pad to fill byte {} <byte 87> utiny status Maintenance status <byte 88> ulong current_edbn Current event data block number <byte 92> ulong start_edbn Manufacturing Event Analysis Log starting event data block numb er <byte 96> ulong end_edbn Manufacturing Event Analysis Log ending event data block number <byte 100> ulong seq_reset_edbn Event data block number where sequence number reset occurre d <byte 104> ulong event_count Number of events contained in Manufacturing Event Analysis Log <byte 108> ulong event_count_wraps Event count overflow <byte 112> ulong sequence_number Last event sequence number used {} <byte 116> do_not_display[12] union_pad Union Element Padding (DO NOT DISPLAY!) endunion cinfo Control Block Information Union <byte 128> union minfo Maintenance Information Union <byte 128> {scelmi (Storage System Event Log Maintenance Information)} <byte 128> ulong index Loop index <byte 132> *ptr *utp Zero test buffer pointer <byte 136> ulong current_eventp Pointer to the current event <byte 140> ulong current_edbn Current event data block number <byte 144> ulong current_seqn Current sequence number <byte 148> ushort previous_offset Previous event buffer offset <byte 150> ushort current_offset Current event buffer offset <byte 152> ulong previous_edbn Previous event data block number <byte 156> ulong previous_seqn Previous sequence number <byte 160> ulong end_found End of Storage System State Logical Disk-Storage System Event Lo g found flag <byte 164> ulong accept_new_to_old New to old transition acceptable flag <byte 168> ulong unequal_found Sequence number not as expected flag <byte 172> ulong iostatus I/O status {} or minfo Maintenance Information Union <byte 128>

{sctelmi (Storage System Termination Event Log Maintenance Information)} <byte 128> ulong index Loop index <byte 132> ulong current_edbn Current event data block number <byte 136> ulong end_edbn End event data block number <byte 140> ulong actrlr If 'A' HSV450 controller, TRUE <byte 144> ulong iostatus I/O status <byte 148> ulong hold_offset Hold buffer current offset {} <byte 152> do_not_display[24] union_pad Union Element Padding (DO NOT DISPLAY!) or minfo Maintenance Information Union <byte 128> {lerinfo (Last Event Reported Information)} <byte 128> ulong reporting_interval Last event reporting interval <byte 132> ulong sequence_number Sequence number assigned to the event <byte 136> scmitim report_time Time event was reported <byte 144> {header (Event Header)} <byte 144> union u Event Code Union <byte 144> {ec (Event Code)} <byte 144> utiny eiptype Event Information Packet Type Code <byte 145> cacode cac Corrective Action Code <byte 146> utiny evnum Event Number <byte 147> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 144> ulong value Event Code Value endunion u Event Code Union <byte 148> utiny revision Packet revision number <byte 149> utiny type Packet type <byte 150> ushort count Number of bytes in packet {} {} <byte 152> do_not_display[24] union_pad Union Element Padding (DO NOT DISPLAY!) or minfo Maintenance Information Union <byte 128> {mealmi (Manufacturing Event Analysis Log Maintenance Information)} <byte 128> ulong index Loop index <byte 132>

*ptr *utp Zero test buffer pointer <byte 136> ulong current_eventp Pointer to the current event <byte 140> ulong current_edbn Current event data block number <byte 144> ulong current_seqn Current sequence number <byte 148> ushort previous_offset Previous event buffer offset <byte 150> ushort current_offset Current event buffer offset <byte 152> ulong previous_edbn Previous event data block number <byte 156> ulong previous_seqn Previous sequence number <byte 160> ulong end_found End of Manufacturing Event Analysis Log found flag <byte 164> ulong accept_new_to_old New to old transition acceptable flag <byte 168> ulong unequal_found Sequence number not as expected flag <byte 172> ulong first_seqn First sequence number {} endunion minfo Maintenance Information Union {} Event Information Packet Type: 4 EIP04 - Fibre Channel Services Physical Disk Drive Error An error was encountered while accessing a physical disk drive. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36>

scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag device UUID of physical disk drive associated with the event <byte 92> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port attach ed to the physical disk drive or mirror port <byte 100> ulong al_pa AL_PA of the physical disk drive or mirror port <byte 104> ushort dencl_num Enclosure where the physical disk drive is located <byte 106> ushort port HSV450 controller internal Fibre Channel port number attached to the physical disk drive or mirror port <byte 108> ushort rack_num Rack where physical disk drive is located <byte 110> ushort bay Enclosure bay where the physical disk drive is located <byte 112> char[16] pid Physical disk drive product identification string <byte 128> char[4] rev Current firmware level of physical disk drive <byte 132> {enclosures[1] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} <byte 132> utiny rack_num Rack were enclosure is located <byte 133> utiny dencl_num Enclosure number {}

<byte 134> {enclosures[0] (Enclosure available on the Fibre cerp_id and port fields)} <byte 134> utiny rack_num Rack were enclosure is located <byte 135> utiny dencl_num Enclosure number {} <byte 136> {enclosures[3] (Enclosure available on the Fibre cerp_id and port fields)} <byte 136> utiny rack_num Rack were enclosure is located <byte 137> utiny dencl_num Enclosure number {} <byte 138> {enclosures[2] (Enclosure available on the Fibre cerp_id and port fields)} <byte 138> utiny rack_num Rack were enclosure is located <byte 139> utiny dencl_num Enclosure number {} <byte 140> {enclosures[5] (Enclosure available on the Fibre cerp_id and port fields)} <byte 140> utiny rack_num Rack were enclosure is located <byte 141> utiny dencl_num Enclosure number {} <byte 142> {enclosures[4] (Enclosure available on the Fibre cerp_id and port fields)} <byte 142> utiny rack_num Rack were enclosure is located <byte 143> utiny dencl_num Enclosure number {} <byte 144> {enclosures[7] (Enclosure available on the Fibre cerp_id and port fields)} <byte 144> utiny rack_num Rack were enclosure is located <byte 145> utiny dencl_num Enclosure number {} <byte 146> {enclosures[6] (Enclosure available on the Fibre cerp_id and port fields)} <byte 146> utiny rack_num Rack were enclosure is located <byte 147> utiny dencl_num Enclosure number {} <byte 148> ushort unused <byte 150> {enclosures[8] (Enclosure available on the Fibre

Channel port identified in the

Channel port identified in the

Channel port identified in the

Channel port identified in the

Channel port identified in the

Channel port identified in the

Channel port identified in the

Channel port identified in the

cerp_id and port fields)} <byte 150> utiny rack_num Rack were enclosure is located <byte 151> utiny dencl_num Enclosure number {} <byte 152> ulong bypass_reason Reason the physical disk drive at this location has been byp assed <byte 156> char[4] new_rev Latest known firmware level of physical disk drive <byte 160> ushort bypassb Mask showing bypass state for each slot in a shelf <byte 162> ushort bypassa Mask showing bypass state for each slot in a shelf {} Event Information Packet Type: 5 EIP05 - Storage System Management Interface Entity State Change The state of a Storage System Management Interface entity has changed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union

<byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {event_type (Entity and Event type)} <byte 76> ushort scmi_object_type Entity type <byte 78> ushort scmi_object_event_type Event Information Packet type {} <byte 80> {value (New entity state)} <byte 80> ulong ul1 Additional information longword 1 <byte 84> ulong ul2 Additional information longword 2 {} <byte 88> scmi_obj_hnd handle Storage System Management Interface Handle of affected entit y <byte 108> ulong secondary_id Alternate entity identification <byte 112> {attribute (Entity attributes)} <byte 112> ulong type Datatype used <byte 116> union value SCMI Attribute Union <byte 116> ushort[12] u16 As 16 bit words, or value SCMI Attribute Union <byte 116> ulong[6] u32 As 32 bit words, or value SCMI Attribute Union <byte 116> double_word[3] u64 As 64 bit words, or value SCMI Attribute Union <byte 116> {obj (As typed Storage System Management Interface object handle,)} <byte 116> ulong value

<byte 120> scmi_obj_hnd handle {} or value SCMI Attribute Union <byte 116> char[24] str As character string endunion value SCMI Attribute Union {} <byte 140> scmi_obj_hnd add_handle Additional entity identification (Storage System Managem ent Interface Handle) <byte 160> ulong[6] add_data Additional Data {} Event Information Packet Type: 6 EIP06 - Fibre Channel Services Enclosure or Enclosure Link Module Status Change Status of an Enclosure or Enclosure Link Module has changed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)}

<byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {enc_wwn (World Wide Name of Enclosure)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> char[8] vendor_id Vendor Identification of Enclosure <byte 92> char[16] product_id Product Identification of Enclosure <byte 108> char[4] product_rev Product Revision Level of Enclosure <byte 112> char[4] enc_hw_type Hardware Type of Enclosure <byte 116> char[4] enc_hw_rev Hardware Revision of Enclosure <byte 120> char[16] enc_serial_num Serial Number of Enclosure <byte 136> char[4] fan_module_1_fw_rev Firmware Revision of Fan Module 1 <byte 140> char[4] fan_module_1_hw_rev Hardware Revision of Fan Module 1 <byte 144> char[16] fan_module_1_serial_num Serial Number of Fan Module 1 <byte 160> char[4] fan_module_2_fw_rev Firmware Revision of Fan Module 2 <byte 164> char[4] fan_module_2_hw_rev Hardware Revision of Fan Module 2 <byte 168> char[16] fan_module_2_serial_num Serial Number of Fan Module 2 <byte 184> char[4] loop_a_elmo_fw_rev Firmware Revision of Loop A Enclosure Link Module <byte 188> char[4] loop_a_elmo_hw_type Hardware Type of Loop A Enclosure Link Module <byte 192> char[4] loop_a_elmo_hw_rev Hardware Revision of Loop A Enclosure Link Module <byte 196> char[16] loop_a_elmo_serial_num Serial Number of Loop A Enclosure Link Module

<byte 212> char[4] loop_a_elmo_transceiver_1_hw_type Hardware Type of Loop A Enclosure Link Module Transceiver 1 <byte 216> char[4] loop_a_elmo_transceiver_2_hw_type Hardware Type of Loop A Enclosure Link Module Transceiver 2 <byte 220> char[4] loop_a_elmo_alphanum_disp_product_rev Product Revision of Loop A Enclosu re Link Module Alphanumeric Display <byte 224> char[16] loop_a_elmo_alphanum_disp_product_id Product Identification of Loop A E nclosure Link Module Alphanumeric Display <byte 240> char[4] loop_b_elmo_fw_rev Firmware Revision of Loop B Enclosure Link Module <byte 244> char[4] loop_b_elmo_hw_type Hardware Type of Loop B Enclosure Link Module <byte 248> char[4] loop_b_elmo_hw_rev Hardware Revision of Loop B Enclosure Link Module <byte 252> char[16] loop_b_elmo_serial_num Serial Number of Loop B Enclosure Link Module <byte 268> char[4] loop_b_elmo_transceiver_1_hw_type Hardware Type of Loop B Enclosure Link Module Transceiver 1 <byte 272> char[4] loop_b_elmo_transceiver_2_hw_type Hardware Type of Loop B Enclosure Link Module Transceiver 2 <byte 276> char[4] loop_b_elmo_alphanum_disp_product_rev Product Revision of Loop B Enclosu re Link Module Alphanumeric Display <byte 280> char[16] loop_b_elmo_alphanum_disp_product_id Product Identification of Loop B E nclosure Link Module Alphanumeric Display <byte 296> char[4] midplane_logic_fw_rev Firmware Revision of Midplane Logic <byte 300> char[4] midplane_logic_hw_type Hardware Type of Midplane Logic <byte 304> char[4] midplane_logic_hw_rev Hardware Revision of Midplane Logic <byte 308> char[16] midplane_logic_serial_num Serial Number of Midplane Logic <byte 324> char[4] backplane_hw_rev Hardware Revision of Backplane <byte 328> ulong loop_a_elmo_n_port_id Arbitrated Loop Physical Address or AL_PA acquired b y the port of Loop A Enclosure Link Module in the Enclosure <byte 332> {loop_a_elmo_n_port_name (World Wide Name of Loop A Enclosure Link Module in the Enclosure)} <byte 332> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 336> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 340> ulong loop_b_elmo_n_port_id Arbitrated Loop Physical Address or AL_PA acquired b y the port of Loop B Enclosure Link Module in the Enclosure <byte 344> {loop_b_elmo_n_port_name (World Wide Name of Loop B Enclosure Link Module in the Enclosure)}

<byte 344> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 348> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 352> ulong enc_num Enclosure Number of Enclosure <byte 356> ulong port Port Number <byte 360> ulong bypass_bay Drive bay to control bypass in Enclosure <byte 364> ulong power_bay Drive bay to control power in Enclosure <byte 368> ulong data Generic data field to be used by caller. <byte 372> ulong data2 Second field of generic data to be used by the caller {} Event Information Packet Type: 7 EIP07 - Fibre Channel Services Fibre Channel Port Link Error Excessive link errors were detected on a Fibre Channel port. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68>

{header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port <byte 84> ushort reserved Reserved <byte 86> ushort port HSV450 controller internal Fibre Channel port number <byte 88> ulong loss_of_signal Number of times a loss of signal was detected <byte 92> ulong bad_rx_char Bad received character count <byte 96> ulong loss_of_sync Loss of synchronization count <byte 100> ulong link_fail Link failure count <byte 104> ulong rx_eofa The number of frames that have been received with an EOFa delimite r <byte 108> ulong dis_frm The number of frames that have been received and then discarded <byte 112> ulong bad_crc The number of frames that have been received with a Bad_CRC and a valid EOF <byte 116> ulong proto_err The number of N_Port protocol errors detected <byte 120> ulong exp_frm The number of outbound frames that have expired and therefore were discarded. {} Event Information Packet Type: 8 EIP08 - Fibre Channel Services Fibre Channel Port Link Failure A Fibre Channel port link has failed or a Drive Enclosure Environmental Monitori ng Unit task has failed. {Event Log Packet Event Specific Information}

<byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {}

<byte 76> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port <byte 84> char[8] other_cerp_id HSV450 controller enclosure rear panel Fibre Channel port attached to the physical disk drive or mirror port <byte 92> {peb[0] (Fibre Channel port Event Blocks)} <byte 92> ulong type Error type code <byte 96> ulong context Error context {} <byte 100> {peb[1] (Fibre Channel port Event Blocks)} <byte 100> ulong type Error type code <byte 104> ulong context Error context {} <byte 108> {peb[2] (Fibre Channel port Event Blocks)} <byte 108> ulong type Error type code <byte 112> ulong context Error context {} <byte 116> {peb[3] (Fibre Channel port Event Blocks)} <byte 116> ulong type Error type code <byte 120> ulong context Error context {} <byte 124> {peb[4] (Fibre Channel port Event Blocks)} <byte 124> ulong type Error type code <byte 128> ulong context Error context {} <byte 132> {peb[5] (Fibre Channel port Event Blocks)} <byte 132> ulong type Error type code <byte 136> ulong context Error context {} <byte 140> {peb[6] (Fibre Channel port Event Blocks)} <byte 140> ulong type Error type code <byte 144> ulong context Error context {} <byte 148> {peb[7] (Fibre Channel port Event Blocks)} <byte 148> ulong type Error type code <byte 152> ulong context Error context

{} <byte 156> ushort peq_prod_index Producer index <byte 158> ushort peq_frz_prod_index Error idle or freeze producer index <byte 160> ushort failure_cause Code indicating path to link failure <byte 162> ushort peq_cons_index Consumer index <byte 164> ushort reserved1 Reserved <byte 166> utiny other_port HSV450 controller internal Fibre Channel port number <byte 167> utiny port HSV450 controller internal Fibre Channel port number <byte 168> ulong time Used to represent a retry time or other time based element in the eve nt. <byte 172> {recovery (Loop Recovery Operations)} <byte 172> ulong progress EWE Step for recovery process <byte 176> ulong shelf Physical Shelf being evaluated. <byte 180> ulong slot Physical Slot being evaluated. <byte 184> ulong cab Cabinet rack being evaluated. {} {} Event Information Packet Type: 9 EIP09 - Fibre Channel Services Physical Disk Drive/Mirror Port Error An error was encountered while attempting to access a physical disk drive or the mirror port. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string

<byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag device UUID of physical disk drive associated with the event <byte 92> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port attach ed to the physical disk drive or mirror port <byte 100> ushort exch_type Frame exchange type <byte 102> ushort port HSV450 controller internal Fibre Channel port number attached to the physical disk drive or mirror port <byte 104> ulong al_pa AL_PA of the physical disk drive or mirror port <byte 108> ushort dencl_num Enclosure where the physical disk drive is located <byte 110> ushort reserved Reserved <byte 112> ushort rack_num Rack where physical disk drive is located <byte 114> ushort bay Enclosure bay where the physical disk drive is located <byte 116> ulong fed_class Fibre Channel Exchange Descriptor class <byte 120>

union cmd Command Descriptor Block issued <byte 120> utiny[16] bytes CDB as bytes or cmd Command Descriptor Block issued <byte 120> ulong[4] lw CDB as longwords or cmd Command Descriptor Block issued <byte 120> {cdb10 (10 Byte CDB by field)} <byte 120> utiny lba1 Offset 3 -- Logical Block Address[1] byte 4 <byte 121> utiny lba0 Offset 2 -- Logical Block Address[0] byte 3 <byte 122> tbits:5 reserved Offset 1, Bits 0-4 -- Reserved byte 2 tbits:3 lun Offset 1, Bits 5-7 -- Logical Unit Number (obsolete method -- unused ) <byte 123> utiny opcode Offset 0 -- Operation Code byte 1 <byte 124> utiny length0 Offset 7 -- Length[0] byte 8 <byte 125> utiny reserved6 Offset 6 -- Reserved byte 7 <byte 126> utiny lba3 Offset 5 -- Logical Block Address[3] byte 6 <byte 127> utiny lba2 Offset 4 -- Logical Block Address[2] byte 5 <byte 128> ushort padding Offsets 10-11 -- Pad to longword align <byte 130> utiny control Offset 9 -- Control byte 10,11 <byte 131> utiny length1 Offset 8 -- Length[1] byte 9 {} <byte 132> do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) endunion cmd Command Descriptor Block issued <byte 136> union error Sense data reported by the physical disk drive <byte 136> utiny[20] bytes Sense data as bytes or error Sense data reported by the physical disk drive <byte 136> ulong[5] lw Sense data as longwords or error Sense data reported by the physical disk drive <byte 136> {sense_data (Sense data from SCSI spec)} <byte 136> utiny info_0 Byte 4 <byte 137> tbits:4 sense_key Byte 3 tbits:1 reserved_1 tbits:1 ili tbits:1 eom tbits:1 filemark <byte 138> utiny segment Byte 2 <byte 139> tbits:7 error_code Byte 1 tbits:1 valid

<byte 140> utiny add_length Byte 8-11 <byte 141> utiny info_3 Byte 7 <byte 142> utiny info_2 Byte 6 <byte 143> utiny info_1 Byte 5 <byte 144> utiny[4] cmd_specific Byte 12-13 <byte 148> tbits:3 bit_ptr Byte 16 tbits:1 bpv tbits:2 reserved tbits:1 cd tbits:1 sksv <byte 149> utiny fru_code Byte 15 <byte 150> union sns Byte 14 <byte 150> {bytes (No description available)} <byte 150> utiny asq Byte 13 <byte 151> utiny asc Byte 12 {} or sns Byte 14 <byte 150> ushort asc_asq endunion sns Byte 14 <byte 152> ushort big_endian_padding <byte 154> ushort field_ptr Byte 17 {} endunion error Sense data reported by the physical disk drive <byte 156> {enclosures[1] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} <byte 156> utiny rack_num Rack were enclosure is located <byte 157> utiny dencl_num Enclosure number {} <byte 158> {enclosures[0] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} <byte 158> utiny rack_num Rack were enclosure is located <byte 159> utiny dencl_num Enclosure number {} <byte 160> {enclosures[3] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} <byte 160> utiny rack_num Rack were enclosure is located <byte 161> utiny dencl_num Enclosure number

{} <byte 162> {enclosures[2] (Enclosure available on the Fibre Channel port identified cerp_id and port fields)} <byte 162> utiny rack_num Rack were enclosure is located <byte 163> utiny dencl_num Enclosure number {} <byte 164> {enclosures[5] (Enclosure available on the Fibre Channel port identified cerp_id and port fields)} <byte 164> utiny rack_num Rack were enclosure is located <byte 165> utiny dencl_num Enclosure number {} <byte 166> {enclosures[4] (Enclosure available on the Fibre Channel port identified cerp_id and port fields)} <byte 166> utiny rack_num Rack were enclosure is located <byte 167> utiny dencl_num Enclosure number {} <byte 168> {enclosures[7] (Enclosure available on the Fibre Channel port identified cerp_id and port fields)} <byte 168> utiny rack_num Rack were enclosure is located <byte 169> utiny dencl_num Enclosure number {} <byte 170> {enclosures[6] (Enclosure available on the Fibre Channel port identified cerp_id and port fields)} <byte 170> utiny rack_num Rack were enclosure is located <byte 171> utiny dencl_num Enclosure number {} <byte 172> ushort unused <byte 174> {enclosures[8] (Enclosure available on the Fibre Channel port identified cerp_id and port fields)} <byte 174> utiny rack_num Rack were enclosure is located <byte 175> utiny dencl_num Enclosure number {} <byte 176> ushort bypassb Mask showing bypass state for each slot in a shelf <byte 178> ushort bypassa Mask showing bypass state for each slot in a shelf <byte 180> char[8] drv_fw_rev The FW revision on the drive {} Event Information Packet Type: a

in the

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EIP0A - Storage System State Services State Change A Storage System state change occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73>

utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {node_name (World Wide Name of HSV450 controller)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> tag scell_tag UUID of Storage System <byte 100> ulong dimm_size Size of this HSV450 controller's DIMM in megabytes <byte 104> ulong debug_flags DebugFlags of HSV450 controller <byte 108> ulong print_flags PrintFlags of HSV450 controller <byte 112> ulong pc Program counter <byte 116> ulong scrub_type Scrub type <byte 120> ulong reboot_flags Reboot flags of HSV450 controller <byte 124> utiny[3] reserved Reserved for future use <byte 127> utiny fm_fatal_scrub Value of fm_fatal_scrub <byte 128> ulong scrub_valid Value of scrub_valid {} Event Information Packet Type: b EIP0B - Storage System State Services Physical Disk Drive State Change A physical disk drive state change occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event

<byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> uuid device UUID of physical disk drive <byte 92> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port attach ed to the physical disk drive <byte 100> ushort reason_code Code identifying cause of the physical disk drive being marke d inoperative or why event is being reported <byte 102> ushort port HSV450 controller internal Fibre Channel port number attached to the physical disk drive or mirror port <byte 104> ushort dencl_num Enclosure where the physical disk drive is located <byte 106> {rss_flags (Redundant Storage Set member state flags)} <byte 106> tbits:1 member_migrating Migrating tbits:1 member_missing Missing or never existed tbits:1 member_abnormal Abnormal tbits:5 reserved Reserved for future use {}

<byte 107> {flags (Information validity flags)} <byte 107> tbits:1 inq_state SCSI INQUIRY data is valid tbits:1 quorum_disk Is Storage System quorum disk tbits:6 reserved Reserved for future use {} <byte 108> ushort rack_num Rack where the physical disk drive is located <byte 110> ushort bay Enclosure bay where the physical disk drive is located <byte 112> {inq_data (Last SCSI INQUIRY data read during discovery (Note: The inquiry data is truncated after the Version Descriptor 1 field.))} <byte 112> tbits:4 response_data Response data format ( 1 = SCSI-1, 2 = SCSI-2, 3 = SCSI-3) tbits:1 hisup Hierarchical Support bit tbits:1 normaca Normal ACA bit tbits:1 obsolete Obsolete tbits:1 aerc Asynchronous Event Reporting Capability bit <byte 113> tbits:8 version Version <byte 114> tbits:7 reserved_1 Reserved tbits:1 rmb Removable Medium bit <byte 115> tbits:5 per_dev_typ Peripheral Device-type tbits:3 per_qual Peripheral Qualifier <byte 116> tbits:1 vs Vendor Specific tbits:1 cmdque Command Queuing bit tbits:1 reserved_2 Reserved tbits:1 linked Linked Command bit tbits:1 sync Synchronous Transfer bit tbits:1 wbus16 Wide Bus 16 bit tbits:1 wbus32 Wide Bus 32 bit tbits:1 reladr Relative Addressing bit <byte 117> tbits:1 addr16 Address 16 bit tbits:2 obsolete_1 Reserved tbits:1 mchngr Medium Changer bit tbits:1 multip Multiport bit tbits:1 vs_1 Vendor Specific tbits:1 encserv Enclosure Services bit tbits:1 bque Basic Queuing bit <byte 118> tbits:7 reserved_3 Reserved tbits:1 sccs SCC Supported bit <byte 119> utiny add_length Additional Length <byte 120> char[8] vendor_id Vendor Identification <byte 128> char[16] product_id Product Identification <byte 144> char[4] product_rev Product Revision Level <byte 148> ulong[5] vendor_36_55 Vendor-specific <byte 168> ushort reserved_56_57 Reserved

<byte 170> ushort vd1 Version Descriptor 1 {} <byte 172> ulong quorum_sequence Quorum Space Write Sequence (i.e., quorum disk 1, 2, or 3) <byte 176> ulong capacity LUN capacity (blocks) <byte 180> ulong supported_capacity Max supporetd LUN capacity (blocks) <byte 184> ulong member_state Redundant Storage Set member state <byte 188> uuid second_device UUID of other physical disk drive <byte 204> ulong second_fnb_ptr Address of fnb for other physical disk drive <byte 208> ushort volnoid Volume of other physical disk drive <byte 210> ushort poid NOID of other physical disk drive {} Event Information Packet Type: c EIP0C - Data Replication Manager State Change A Data Replication Manager state change occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call

<byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag group_name_uuid Group Name UUID <byte 92> tag peer_scell_uuid Peer Storage System UUID <byte 108> tag group_uuid Data Replication Group UUID <byte 124> tag source_scvd_uuid Source Storage System Virtual Disk UUID <byte 140> tag dest_scvd_uuid If eip0c.flags.remote_adapter_wwn is set equal to 1, this fie ld contains the WWN of the remote adapter. Otherwise, this field contains the De stination Storage System Virtual Disk UUID. <byte 156> ushort blocks Number of blocks in error <byte 158> ushort status Error status value <byte 160> ulonglong vda Virtual Disk Address in error <byte 168> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port <byte 176> utiny extra Used for miscellaneous information <byte 177> {flags (Field use flags)} <byte 177> tbits:7 reserved Reserved for future use tbits:1 remote_adapter_wwn dest_scvd_uuid contains remote adapter WWN {} <byte 178> utiny side Remote HSV450 controller used by Data Replication Manager tunnel: 0 = > A; 1 => B <byte 179> utiny port HSV450 controller internal Fibre Channel port number <byte 180>

ulong[2] reserved1 Reserved for future use {} Event Information Packet Type: d EIP0D - Executive Services System Time Change A change in system time occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value

endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> utiny[3] unused Unused <byte 79> utiny action Action code <byte 80> ulong[2] reserved Reserved <byte 88> scmitim ctime Current time value <byte 96> scmitim ptime Previous time value {} Event Information Packet Type: e EIP0E - Storage System Management Interface Entity Creation or Deletion A Storage System Management Interface entity was created or deleted. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68>

{header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {event_type (Entity and Event type)} <byte 76> ushort scmi_object_type Entity type <byte 78> ushort scmi_object_event_type Event Information Packet type {} <byte 80> scmi_obj_hnd handle Storage System Management Interface Handle of affected entit y <byte 100> scmi_obj_hnd add_handle Additional entity identification (Storage System Managem ent Interface Handle) <byte 120> {attribute (Entity attributes)} <byte 120> ulong type Datatype used <byte 124> union value SCMI Attribute Union <byte 124> ushort[12] u16 As 16 bit words, or value SCMI Attribute Union <byte 124> ulong[6] u32 As 32 bit words, or value SCMI Attribute Union <byte 124> double_word[3] u64 As 64 bit words, or value SCMI Attribute Union <byte 124> {obj (As typed Storage System Management Interface object handle,)} <byte 124> ulong value <byte 128> scmi_obj_hnd handle {}

or value SCMI Attribute Union <byte 124> char[24] str As character string endunion value SCMI Attribute Union {} <byte 148> scmi_obj_hnd add_handle2 Additional SCMI object handle (2) <byte 168> ulong[4] add_data Additional Data {} Event Information Packet Type: f EIP0F - Storage System Management Interface Entity Attribute Change An attribute of a Storage System Management Interface entity has changed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code

<byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {event_type (Entity and Event type)} <byte 76> ushort scmi_object_type Entity type <byte 78> ushort scmi_object_event_type Event Information Packet type {} <byte 80> union secondary_id Secondary identification <byte 80> ulong Id Alternate entity identification or secondary_id Secondary identification <byte 80> {rss_data (Redundant Storage Set information)} <byte 80> ushort Id Redundant Storage Set identification <byte 82> ushort Index Redundant Storage Set index {} endunion secondary_id Secondary identification <byte 84> {old_attr (Old attribute information)} <byte 84> ulong type Datatype used <byte 88> union value SCMI Attribute Union <byte 88> ushort[12] u16 As 16 bit words, or value SCMI Attribute Union <byte 88> ulong[6] u32 As 32 bit words, or value SCMI Attribute Union <byte 88> double_word[3] u64 As 64 bit words, or value SCMI Attribute Union <byte 88> {obj (As typed Storage System Management Interface object handle,)} <byte 88> ulong value <byte 92> scmi_obj_hnd handle {} or value SCMI Attribute Union <byte 88>

char[24] str As character string endunion value SCMI Attribute Union {} <byte 112> {new_attr (New attribute information)} <byte 112> ulong type Datatype used <byte 116> union value SCMI Attribute Union <byte 116> ushort[12] u16 As 16 bit words, or value SCMI Attribute Union <byte 116> ulong[6] u32 As 32 bit words, or value SCMI Attribute Union <byte 116> double_word[3] u64 As 64 bit words, or value SCMI Attribute Union <byte 116> {obj (As typed Storage System Management Interface object handle,)} <byte 116> ulong value <byte 120> scmi_obj_hnd handle {} or value SCMI Attribute Union <byte 116> char[24] str As character string endunion value SCMI Attribute Union {} <byte 140> scmi_obj_hnd handle Storage System Management Interface Handle of affected entit y <byte 160> scmi_obj_hnd add_handle Additional entity identification (Storage System Managem ent Interface <byte 180> ulong reserved reserved for future use {} Event Information Packet Type: 10 EIP10 - System Services HSV450 Controller State Change A controller state change occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {}

<byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {node_name (World Wide Name of HSV450 controller)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> {information (State change information)} <byte 84> ulong pc Program counter <byte 88> ulong flags Flags <byte 92>

ulong code Code {} {} Event Information Packet Type: 11 EIP11 - Disk Enclosure Environmental Monitoring Unit Services Status Change. Status of a disk enclosure element has changed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68>

ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {event_type (Entity and Event type)} <byte 76> ushort scmi_object_type Entity type <byte 78> ushort scmi_object_event_type Event Information Packet type {} <byte 80> scmi_obj_hnd handle Storage System Management Interface Handle of affected disk enclosure <byte 100> ulong rack_num Rack number <byte 104> ulong dencl_num Disk enclosure number <byte 108> union alarm_error_code Alarm code <byte 108> ulong value As longword or alarm_error_code Alarm code <byte 108> {field (By field)} <byte 108> utiny reserved Reserved for future use <byte 109> utiny ec Error code <byte 110> utiny en Element number <byte 111> utiny et Element type code {} endunion alarm_error_code Alarm code <byte 112> utiny[3] rsvd1 Reserved for future use <byte 115> utiny loop Loop number <byte 116> {enclosures[1] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} <byte 116> utiny rack_num Rack were enclosure is located <byte 117> utiny dencl_num Enclosure number {} <byte 118> {enclosures[0] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} <byte 118> utiny rack_num Rack were enclosure is located <byte 119> utiny dencl_num Enclosure number {}

<byte 120> {enclosures[3] (Enclosure available on the Fibre the loop field)} <byte 120> utiny rack_num Rack were enclosure is located <byte 121> utiny dencl_num Enclosure number {} <byte 122> {enclosures[2] (Enclosure available on the Fibre the loop field)} <byte 122> utiny rack_num Rack were enclosure is located <byte 123> utiny dencl_num Enclosure number {} <byte 124> {enclosures[5] (Enclosure available on the Fibre the loop field)} <byte 124> utiny rack_num Rack were enclosure is located <byte 125> utiny dencl_num Enclosure number {} <byte 126> {enclosures[4] (Enclosure available on the Fibre the loop field)} <byte 126> utiny rack_num Rack were enclosure is located <byte 127> utiny dencl_num Enclosure number {} <byte 128> {enclosures[7] (Enclosure available on the Fibre the loop field)} <byte 128> utiny rack_num Rack were enclosure is located <byte 129> utiny dencl_num Enclosure number {} <byte 130> {enclosures[6] (Enclosure available on the Fibre the loop field)} <byte 130> utiny rack_num Rack were enclosure is located <byte 131> utiny dencl_num Enclosure number {} <byte 132> ushort unused <byte 134> {enclosures[8] (Enclosure available on the Fibre the loop field)} <byte 134> utiny rack_num Rack were enclosure is located <byte 135> utiny dencl_num Enclosure number {} <byte 136> ulong[12] rsvd Reserved for future use

Channel loop pair identified in

Channel loop pair identified in

Channel loop pair identified in

Channel loop pair identified in

Channel loop pair identified in

Channel loop pair identified in

Channel loop pair identified in

{} Event Information Packet Type: 12 EIP12 - Fibre Channel Services Physical Disk Drive/Mirror Port Unexpected Work E ncountered Unexpected work was received from a physical disk drive or the mirror port. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value

endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag device UUID of the physical disk drive or HSV450 controller associated with the event <byte 92> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port attach ed to the physical disk drive or mirror port <byte 100> ulong al_pa AL_PA of the physical disk drive or the mirror port <byte 104> ushort dencl_num Enclosure where the physical disk drive is located <byte 106> ushort port HSV450 controller internal Fibre Channel port number attached to the physical disk drive or mirror port <byte 108> ushort rack_num Rack where the physical disk drive is located <byte 110> ushort bay Enclosure bay where the physical disk drive is located <byte 112> ulong[14] hdr_cdb Command Descriptor Block issued and Fibre Channel Header <byte 168> ushort bypassb Mask showing bypass state for each slot in a shelf <byte 170> ushort bypassa Mask showing bypass state for each slot in a shelf {} Event Information Packet Type: 13 EIP13 - Fibre Channel Services Physical Disk Drive/Mirror Port/Drive Enclosure E nvironmental Monitoring Unit Error summary. Summary of errors encountered while attempting to access a physical disk drive, the mirror port, or a Drive Enclosure Environmental Monitoring Unit. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4>

ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag device UUID of the physical disk drive, HSV450 controller, or Drive Enclosur e Environmental Monitoring Unit associated with the event <byte 92> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port attach ed to the physical disk drive or mirror port <byte 100> ulong al_pa AL_PA of the physical disk drive or the mirror port <byte 104> ushort dencl_num Enclosure where the physical disk drive is located <byte 106> ushort port HSV450 controller internal Fibre Channel port number attached to the physical disk drive or mirror port <byte 108> ushort rack_num Rack where the physical disk drive is located <byte 110> ushort bay Enclosure bay where the physical disk drive is located <byte 112> ulong fed_class Fibre Channel Exchange Descriptor class <byte 116>

ulong num_times Number of occurrences of the error. <byte 120> {enclosures[1] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 120> utiny rack_num Rack were enclosure is located <byte 121> utiny dencl_num Enclosure number {} <byte 122> {enclosures[0] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 122> utiny rack_num Rack were enclosure is located <byte 123> utiny dencl_num Enclosure number {} <byte 124> {enclosures[3] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 124> utiny rack_num Rack were enclosure is located <byte 125> utiny dencl_num Enclosure number {} <byte 126> {enclosures[2] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 126> utiny rack_num Rack were enclosure is located <byte 127> utiny dencl_num Enclosure number {} <byte 128> {enclosures[5] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 128> utiny rack_num Rack were enclosure is located <byte 129> utiny dencl_num Enclosure number {} <byte 130> {enclosures[4] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 130> utiny rack_num Rack were enclosure is located <byte 131> utiny dencl_num Enclosure number {} <byte 132> {enclosures[7] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 132> utiny rack_num Rack were enclosure is located <byte 133> utiny dencl_num Enclosure number {} <byte 134> {enclosures[6] (Enclosure available on the Fibre Channel cerp_id and port fields)}

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<byte 134> utiny rack_num Rack were enclosure is located <byte 135> utiny dencl_num Enclosure number {} <byte 136> ushort bypass_reason Reason for Drive Enclosure Environmental Monitoring Unit by pass <byte 138> {enclosures[8] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} <byte 138> utiny rack_num Rack were enclosure is located <byte 139> utiny dencl_num Enclosure number {} <byte 140> char[8] missing_cerp_id HSV450 controller enclosure rear panel Fibre Channel por t that cannot connect to physical disk drive or mirror port <byte 148> ushort bypassa Mask showing bypass state for each slot in a shelf <byte 150> ushort missing_port HSV450 controller internal Fibre Channel port number that ca nnont connect to the physical disk drive or mirror port <byte 152> ushort switch_type Used to represent the type of switch detected (SES or non-SES compliant) <byte 154> ushort bypassb Mask showing bypass state for each slot in a shelf {} Event Information Packet Type: 14 EIP14 - Diagnostic Operations Generator Detected Failure. A failure was detected during the execution of a diagnostic. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16>

char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {eep_error (Diagnostic error EEPROM data)} <byte 76> utiny padding Pad to longword align this structure <byte 77> utiny count Duplicate error count <byte 78> utiny test_num Test number <byte 79> utiny TE_num TE number <byte 80> ulong Z_code Z's code <byte 84> ulong error_code Error code <byte 88> ulong address Address of Error <byte 92> ulong expected Expected Data <byte 96> ulong actual Actual Data <byte 100> ulonglong uptime Uptime of error {} <byte 108>

ulong dimm_size Size of this HSV450 controller's DIMM in megabytes {} Event Information Packet Type: 15 EIP15 - Container Services Management Operation has started or completed. An operation on a Disk Group has started or completed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value

endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag tag1 UUID of the Virtual Disk, physical disk drive, or Disk Group associated with the event <byte 92> tag tag2 UUID of the Virtual Disk, physical disk drive, or Disk Group associated with the event <byte 108> ulong state Event-specific state value <byte 112> ulong status Event-specific operation status {} Event Information Packet Type: 16 EIP16 - Data Replication Manager Time Report. An Data Replication Manager time synchronization event has occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68>

{header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> uuid sender Enterprise Virtual Array controller initiating time report message <byte 92> uuid receiver Peer controller receiving time report message <byte 108> uuid receiver_partner Other controller in sending or receiving Storage System <byte 124> scmitim sent_time Time message was sent <byte 132> scmitim received_time Time message was received {} Event Information Packet Type: 17 EIP17 - Fibre Channel Services Fibre Channel Port Loop Config A new device map has been generated on a Fibre Channel port. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2>

ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port <byte 84> ulong map_id Multi-page map identifier (all pages containing this identifier com prise this map) <byte 88> utiny entries Number of map entries (AL_PAs) in this map <byte 89> utiny total_pages Total pages containing portions of this map <byte 90> utiny page Page number of this loop map event <byte 91> utiny port HSV450 controller internal Fibre Channel port number <byte 92> utiny[92] loop_map Loop configuration information {} Event Information Packet Type: 18

EIP18 - Storage System State Services Redundant Storage Set State Change A Redundant Storage Set state change occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73>

utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag ldad_tag Tag of the Disk Group associated with the event <byte 92> ushort target_rss Migration target <byte 94> ushort source_rss Migration source <byte 96> ushort target_migr Migration flags for target <byte 98> ushort source_migr Migration flags for source <byte 100> utiny[16] smembers Volumes in source <byte 116> utiny[16] tmembers Volumes in target {} Event Information Packet Type: 19 EIP19 - System Data Center Services Status Change Status of a System Data Center element has changed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68>

{header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {event_type (Entity and Event type)} <byte 76> ushort scmi_object_type Entity type <byte 78> ushort scmi_object_event_type Event Information Packet type {} <byte 80> scmi_obj_hnd handle Storage System Management Interface ------------------------------------------------------------------------- XL only - not used in LE <byte 100> {state (State of SDC monitored component)} <byte 100> ulong old Previous State <byte 104> ulong cur Current State {} <byte 108> {status_code (Status code of SDC monitored component)} <byte 108> ulong old Previous Status Code <byte 112> ulong cur Current Status Code {} <byte 116> {status_data (Status data of SDC monitored component)} <byte 116> ulong old Previous Additional Status Data <byte 120> ulong cur Current Additional Status Data {} <byte 124> ulong[4] comp_states States of SDC monitored components <byte 140> ulong[4] comp_status_codes Status codes of SDC monitored components

<byte 156> ulong[4] comp_status_data Status data of SDC monitored components <byte 172> utiny reserved3 <byte 173> utiny reserved2 <byte 174> utiny reserved1 <byte 175> utiny controller_number <byte 176> {component (Component status)} <byte 176> utiny sub_condition Component sub-condition <byte 177> utiny condition Component condition <byte 178> utiny state Component State <byte 179> utiny number Component number <byte 180> utiny[4] data Additional data <byte 184> char[8] label Component label {} <byte 192> char[16] assembly_part_number <byte 208> char[16] assembly_serial_number <byte 224> char[4] hardware_revision <byte 228> char[4] firmware_revision <byte 232> char[16] salable_product_number <byte 248> char[12] salable_serial_number <byte 260> char[16] spare_part_number <byte 276> char[8] vendor_id <byte 284> char[16] product_id <byte 300> char[64] degraded_subcomponents {} Event Information Packet Type: 1a EIP1A - System Services Code Load Operation Update A code load operation has occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re

conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> char[40] state State information <byte 116> char[36] hardware Hardware information <byte 152> char[32] versions Version information <byte 184> char[32] code_version New code version.

{} Event Information Packet Type: 1b EIP1B - Host Port Event A Host Port Event Occurred {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union

<byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag scvd_tag Associated Storage System Virtual Disk UUID <byte 92> ulong data Event specific data New fields for revision 4 // <byte 96> tag lun_wwid Lun WWID for this vdisk <byte 112> utiny active IO on active queue <byte 113> utiny host Pending Host Quiesces <byte 114> utiny deferred Pending Deferred Quiesces <byte 115> utiny pending Pending Quiesces <byte 116> utiny presented_other Presented to other controller <byte 117> utiny presented_this Presented to reporting controller <byte 118> utiny suspended IO on suspended queue <byte 119> utiny inactive IO on inactive queue <byte 120> ulong vdsb_flags VDSB Flags <byte 124> ushort drmio DRM IO count outstanding <byte 126> ushort group DRM Unit <byte 128> ushort reserved Reserved for future use. <byte 130> utiny drmcmprefetch DRM CM Prefetch <byte 131> utiny drmcmflushing DRM CM Flushing {} Event Information Packet Type: 1c EIP1C - Fault Manager Termination Event HSV450 controller operation terminated event report. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un

til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {lteihd (Last Termination Event Information Header)} <byte 76> {flags (Last Termination Event flags)} <byte 76> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 rsvd Pad to fill byte tbits:1 labcode Event reported using LAB code

tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 77> utiny revision Structure revision number <byte 78> ushort size Structure size {} <byte 80> {lter (Last Termination Event Report Block)} <byte 80> ulong seq Sequence number assigned to the termination event <byte 84> char[8] sw_version HSV450 controller software version number string <byte 92> char[12] baselevel_id HSV450 controller baselevel build string <byte 104> char[8] ctrlr_model_id HSV450 controller model string <byte 112> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV 450 controller that terminated operation <byte 132> scmitim termination_time Time termination event occurred <byte 140> {termination_event (Termination event information)} <byte 140> ulong termination_location Location of termination event report call <byte 144> union u Termination Code Union <byte 144> {code (Termination Code)} <byte 144> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 145> cacode cac Corrective Action Code <byte 146> utiny evnum Event Number <byte 147> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 144> ulong value Termination Code Value endunion u Termination Code Union <byte 148> {params (Termination Parameters)} <byte 148> ulong[31] param Termination Parameters {} {} <byte 272> utiny[2] reserved Reserved <byte 274> {flags (Other Last Termination Event flags)} <byte 274> tbits:1 lg_send_sts Last Gasp send status tbits:1 stack_bad Stack contains pointer outside stack area

tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved tbits:3 rsvd Pad to fill byte {} <byte 275> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Eve nt array index <byte 276> ulonglong uptime Number of seconds HSV450 controller has run functional code {} {} Event Information Packet Type: 1d EIP1D - Fault Manager Termination Event (old Termination Event Information Heade r) HSV450 controller operation terminated event report. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68>

utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {lteihd (Last Termination Event Information Header)} <byte 76> {flags (Last Termination Event flags)} <byte 76> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved {} <byte 77> utiny revision Structure revision number <byte 78> ushort size Structure size {} <byte 80> {lter (Nonstandard Last Termination Event Report Block)} <byte 80> ulong seq Sequence number assigned to the termination event <byte 84> char[4] sw_version HSV450 controller software version number string <byte 88> char[12] baselevel_id HSV450 controller baselevel build string <byte 100> char[8] ctrlr_model_id HSV450 controller model string <byte 108> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV 450 controller that terminated operation <byte 128> scmitim termination_time Time termination event occurred <byte 136> {termination_event (Termination event information)} <byte 136> ulong termination_location Location of termination event report call <byte 140> union u Termination Code Union

<byte 140> {code (Termination Code)} <byte 140> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 141> cacode cac Corrective Action Code <byte 142> utiny evnum Event Number <byte 143> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 140> ulong value Termination Code Value endunion u Termination Code Union {} <byte 144> utiny[2] reserved Reserved <byte 146> utiny lg_send_sts Last Gasp send status <byte 147> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Eve nt array index <byte 148> ulonglong uptime Number of seconds HSV450 controller has run functional code {} {} Event Information Packet Type: 1e EIP1E - General Storage System State Services State Information Event General Storage System state information to be reported. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string

<byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> char[12] info Informational String <byte 88> ulong[24] data Informational Data {} Event Information Packet Type: 1f EIP1F - A Storage System Virtual Disk has changed controller mastership. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {}

<byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag ld_tag Logical disk <byte 92> tag du_tag Derived unit <byte 108> tag scvd_tag Storage System Virtual Disk <byte 124> {prev_wwn (Previous Controller)} <byte 124> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 128> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 132>

{current_wwn (Current Controller)} <byte 132> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 136> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} {} Event Information Packet Type: 20 EIP20 - Storage System State Services Controller FC Port event {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71>

utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {node_name (World Wide Name of HSV450 controller)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> ulong port Loop port number <byte 88> ulong data Event-specific data {} Event Information Packet Type: 21 EIP21 - General purpose SCS Logical Disk synchronization event {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45

0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag target_tag Target Tag <byte 92> tag parent_tag Parent Tag <byte 108> ulong operation Operation <byte 112> ulong status Status <byte 116> ulong prev_state Previous State <byte 120> ulong new_state New State <byte 124> ulong redundancy Redundancy Type <byte 128> ulonglong size SCVD Size <byte 136> tag aux_tag Auxillary Tag {} Event Information Packet Type: 23 EIP23 - State configuration error events {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t

he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {device_wwn (World Wide Name of relevant HSV450 controller or physical disk driv e)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B

its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> ulong scs_flags SCS flags <byte 88> ulong scs_flags2 SCS flags2 <byte 92> ulong data Generic data <byte 96> ulong data2 Generic data <byte 100> ulong[8] port_state Current port states <byte 132> ulong[8] master_port_state Current port connectivity on master. <byte 164> ulong[8] slave_port_state Current port connectivity on slave. <byte 196> ulong[8] master_prev_port_state Previous port connectivity on master. <byte 228> ulong[8] slave_prev_port_state Previous port connectivity on slave. {} Event Information Packet Type: 24 EIP24 - Host Port Event A Host Port Event Occurred {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56>

scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> ulong[5] data Event specific data {} Event Information Packet Type: 26 EIP26 - ECC error counter events {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string

<byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {ecc_cnt (No description available)} <byte 76> ulong time_since_reset time since last reset <byte 80> ulong policy_mem_size policy memory size <byte 84> ulong cache_mem_size cache memory size <byte 88> ulong ecc_count ecc errors count <byte 92> ulong ecc_previous_count ecc errors previous count {} {} Event Information Packet Type: 27 EIP27 - Battery policy changed {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller

tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {node_name (World Wide Name of)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B

its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> ulong old_battery_state_this old battery state this controller <byte 88> ulong old_battery_state_other old battery state other controller <byte 92> ulong old_battery_cache_state old battery cache state <byte 96> ulong new_battery_state_this new battery state this controller <byte 100> ulong new_battery_state_other new battery state other controller <byte 104> ulong new_battery_cache_state new battery cache state {} Event Information Packet Type: 28 EIP28 - Fibre Channel Services Fibre Channel Port Link Transition A Fibre Channel port link has come up or gone down. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68>

union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {node_name (World Wide Name of HSV450 controller)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port <byte 92> utiny port_count Then number of ports on the device <byte 93> utiny level The level of the link transition: 0: Low - TSDK Layer 1: High - Stat e Layer <byte 94> utiny status The status of the link transition: 0: Link went down 1: Link came u p <byte 95> utiny port HSV450 controller internal Fibre Channel port number <byte 96> ulong[8] fm_status The FM status for each Fibre Channel port on this controller Note: This can change size depending on the controller port count {} Event Information Packet Type: 29 EIP29 A physical disk drive has experienced an ID block inconsistency. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re

conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> ushort idb_write_status keeps state of the ID block write <byte 78> ushort instance 4 parts of code will trap the ID mismatch <byte 80> {cached_node_name (the cached wwn)} <byte 80> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B

its 3:0) Type <byte 84> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 88> {last_poll_node_name (the wwn as of last poll)} <byte 88> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 92> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 96> tag cached_ps_tag the cached ps tag <byte 112> tag id_ps_tag the ps tag read from disk <byte 128> tag cached_vol_tag the cached vol tag <byte 144> tag id_vol_tag the vol tab read from disk <byte 160> ushort bay drive bay <byte 162> ushort enclosure the drive shelf {} Event Information Packet Type: 2a EIP2A - Information report when CVM quorum update fails on at least one drive. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45

0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> ulong io_mask quorum io mask <byte 80> ulong rss0_member_mask current state mask <byte 84> ulong success_rewrite rewritten RSS0 count <byte 88> ulong incarnation new incarnation {} TERMINATION EVENT BLOCK: {Termination Event Block} <byte 0> union u Last Termination Event Block Union <byte 0> {data (Termination Event Block Data)} <byte 0> {ltei (Last Termination Event Information)} <byte 0> {lteihd (Last Termination Event Information Header)} <byte 0> {flags (Last Termination Event flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced

tbits:1 rsvd Pad to fill byte tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort size Structure size {} <byte 4> {lter (Last Termination Event Report Block)} <byte 4> ulong seq Sequence number assigned to the termination event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV 450 controller that terminated operation <byte 56> scmitim termination_time Time termination event occurred <byte 64> {termination_event (Termination event information)} <byte 64> ulong termination_location Location of termination event report call <byte 68> union u Termination Code Union <byte 68> {code (Termination Code)} <byte 68> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 68> ulong value Termination Code Value endunion u Termination Code Union <byte 72> {params (Termination Parameters)} <byte 72> ulong[31] param Termination Parameters {} {} <byte 196> utiny[2] reserved Reserved <byte 198> {flags (Other Last Termination Event flags)} <byte 198>

tbits:1 lg_send_sts Last Gasp send status tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved tbits:3 rsvd Pad to fill byte {} <byte 199> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Eve nt array index <byte 200> ulonglong uptime Number of seconds HSV450 controller has run functional code {} <byte 208> {sa (Exception save area)} <byte 208> ulong[32] registers R0-R31 <byte 336> union int_level The level of interrupt machine, external or critical <byte 336> {standard (standard)} <byte 336> ulong srr0 SRR0 <byte 340> ulong srr1 SRR1 {} or int_level The level of interrupt machine, external or critical <byte 336> {machine (No description available)} <byte 336> ulong mcsrr0 MCSRR0 <byte 340> ulong mcsrr1 MCSRR1 {} or int_level The level of interrupt machine, external or critical <byte 336> {critical (No description available)} <byte 336> ulong csrr0 CSRR0 <byte 340> ulong csrr1 CSRR1 {} endunion int_level The level of interrupt machine, external or critical <byte 344> ulong cr CR <byte 348> ulong xer XER <byte 352> ulong esr ESR <byte 356> ulong ctr CTR <byte 360> ulong lr LR <byte 364> ulong exception Exception Code <byte 368> union optional Machine check or DSI exception values <byte 368> {mcp (Machine check values)} <byte 368>

ulong mc_count Exception Count <byte 372> ulong mcsr MCSR Register or MCSRR0 Register {} or optional Machine check or DSI exception values <byte 368> {dsi (DSI exception values)} <byte 368> ulong dsisr DSI Status Register <byte 372> ulong dear DEAR Register (440) or DAR Register (7448) {} endunion optional Machine check or DSI exception values <byte 376> ulong pid PID <byte 380> ulong usprg0 usprg0 {} <byte 384> char[8] current_process Current process name <byte 392> {stack (Stack information)} <byte 392> ulong stack_depth Total calls made <byte 396> {stack[0] (Stack entries)} <byte 396> ulong bc Back chain (old stack pointer) <byte 400> ulong slr Saved link register {} <byte 404> {stack[1] (Stack entries)} <byte 404> ulong bc Back chain (old stack pointer) <byte 408> ulong slr Saved link register {} <byte 412> {stack[2] (Stack entries)} <byte 412> ulong bc Back chain (old stack pointer) <byte 416> ulong slr Saved link register {} <byte 420> {stack[3] (Stack entries)} <byte 420> ulong bc Back chain (old stack pointer) <byte 424> ulong slr Saved link register {} <byte 428> {stack[4] (Stack entries)} <byte 428> ulong bc Back chain (old stack pointer) <byte 432> ulong slr Saved link register {} <byte 436>

{stack[5] (Stack entries)} <byte 436> ulong bc Back chain (old stack <byte 440> ulong slr Saved link register {} <byte 444> {stack[6] (Stack entries)} <byte 444> ulong bc Back chain (old stack <byte 448> ulong slr Saved link register {} <byte 452> {stack[7] (Stack entries)} <byte 452> ulong bc Back chain (old stack <byte 456> ulong slr Saved link register {} <byte 460> {stack[8] (Stack entries)} <byte 460> ulong bc Back chain (old stack <byte 464> ulong slr Saved link register {} <byte 468> {stack[9] (Stack entries)} <byte 468> ulong bc Back chain (old stack <byte 472> ulong slr Saved link register {} <byte 476> {stack[10] (Stack entries)} <byte 476> ulong bc Back chain (old stack <byte 480> ulong slr Saved link register {} <byte 484> {stack[11] (Stack entries)} <byte 484> ulong bc Back chain (old stack <byte 488> ulong slr Saved link register {} <byte 492> {stack[12] (Stack entries)} <byte 492> ulong bc Back chain (old stack <byte 496> ulong slr Saved link register {} <byte 500> {stack[13] (Stack entries)} <byte 500> ulong bc Back chain (old stack <byte 504>

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ulong slr Saved link register {} <byte 508> {stack[14] (Stack entries)} <byte 508> ulong bc Back chain (old stack <byte 512> ulong slr Saved link register {} <byte 516> {stack[15] (Stack entries)} <byte 516> ulong bc Back chain (old stack <byte 520> ulong slr Saved link register {} <byte 524> {stack[16] (Stack entries)} <byte 524> ulong bc Back chain (old stack <byte 528> ulong slr Saved link register {} <byte 532> {stack[17] (Stack entries)} <byte 532> ulong bc Back chain (old stack <byte 536> ulong slr Saved link register {} <byte 540> {stack[18] (Stack entries)} <byte 540> ulong bc Back chain (old stack <byte 544> ulong slr Saved link register {} <byte 548> {stack[19] (Stack entries)} <byte 548> ulong bc Back chain (old stack <byte 552> ulong slr Saved link register {} <byte 556> {stack[20] (Stack entries)} <byte 556> ulong bc Back chain (old stack <byte 560> ulong slr Saved link register {} <byte 564> {stack[21] (Stack entries)} <byte 564> ulong bc Back chain (old stack <byte 568> ulong slr Saved link register {} <byte 572> {stack[22] (Stack entries)}

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<byte 572> ulong bc Back chain (old stack <byte 576> ulong slr Saved link register {} <byte 580> {stack[23] (Stack entries)} <byte 580> ulong bc Back chain (old stack <byte 584> ulong slr Saved link register {} <byte 588> {stack[24] (Stack entries)} <byte 588> ulong bc Back chain (old stack <byte 592> ulong slr Saved link register {} <byte 596> {stack[25] (Stack entries)} <byte 596> ulong bc Back chain (old stack <byte 600> ulong slr Saved link register {} <byte 604> {stack[26] (Stack entries)} <byte 604> ulong bc Back chain (old stack <byte 608> ulong slr Saved link register {} <byte 612> {stack[27] (Stack entries)} <byte 612> ulong bc Back chain (old stack <byte 616> ulong slr Saved link register {} <byte 620> {stack[28] (Stack entries)} <byte 620> ulong bc Back chain (old stack <byte 624> ulong slr Saved link register {} <byte 628> {stack[29] (Stack entries)} <byte 628> ulong bc Back chain (old stack <byte 632> ulong slr Saved link register {} <byte 636> {stack[30] (Stack entries)} <byte 636> ulong bc Back chain (old stack <byte 640> ulong slr Saved link register

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{} <byte 644> {stack[31] (Stack entries)} <byte 644> ulong bc Back chain (old stack pointer) <byte 648> ulong slr Saved link register {} <byte 652> *ptr *bad_stack_ptr Bad stack address <byte 656> ulong system_stack_guard System stack guard intact flags (set to 1 if not intact ) <byte 660> ulong[16] stack_guard Process stack guard intact flags (set to 1 if not intact) {} <byte 724> {hardware (Hardware registers)} <byte 724> {flags (Hardware registers gathered flags)} <byte 724> lbits:1 uartdrd SC28L194 Quad UART d data registers gathered lbits:1 uartdrc SC28L194 Quad UART c data registers gathered lbits:1 uartdrb SC28L194 Quad UART b data registers gathered lbits:1 uartdra SC28L194 Quad UART a data registers gathered lbits:1 uartcrd SC28L194 Quad UART d control registers gathered lbits:1 uartcrc SC28L194 Quad UART c control registers gathered lbits:1 uartcrb SC28L194 Quad UART b control registers gathered lbits:1 uartcra SC28L194 Quad UART a control registers gathered lbits:1 sprite_csr Sprite Chip CSR registers gathered lbits:1 glue_csr Glue Chip CSR registers gathered lbits:1 toyclock DS1557 4MEG NV Y2KC Timekeeping RAM registers gathered lbits:1 decoder_csr Decoder lbits:1 atlantis_csr Atlantis (Crash Dump only) lbits:1 atlantis_mcs Atlantis machine check specific registers (Termination even t only) lbits:1 atlantis_a1 Atlantis Area 1 miscellaneous registers (Termination event o nly) lbits:1 aa2 Atlantis registers--Area 2 (Termination event only) lbits:1 aa3 Atlantis registers--Area 3 (Termination event only) lbits:15 rsvd Reserved {} <byte 728> {tach_flags (Tachyon registers gathered flags)} <byte 728> lbits:1 tachyon9_csr Tachyon 9 CSR registers gathered lbits:1 tachyon9_pcicfg Tachyon 9 PCI Configuration lbits:1 tachyon9_gbic Tachyon 9 GBIC Small Form Factor ID lbits:1 tachyon8_csr Tachyon 8 CSR registers gathered lbits:1 tachyon8_pcicfg Tachyon 8 PCI Configuration lbits:1 tachyon8_gbic Tachyon 8 GBIC Small Form Factor ID lbits:1 tachyon7_csr Tachyon 7 CSR registers gathered lbits:1 tachyon7_pcicfg Tachyon 7 PCI Configuration lbits:1 tachyon7_gbic Tachyon 7 GBIC Small Form Factor ID lbits:1 tachyon6_csr Tachyon 6 CSR registers gathered lbits:1 tachyon6_pcicfg Tachyon 6 PCI Configuration lbits:1 tachyon6_gbic Tachyon 6 GBIC Small Form Factor ID lbits:1 tachyon5_csr Tachyon 5 CSR registers gathered lbits:1 tachyon5_pcicfg Tachyon 5 PCI Configuration lbits:1 tachyon5_gbic Tachyon 5 GBIC Small Form Factor ID

lbits:1 tachyon4_csr Tachyon 4 CSR registers gathered lbits:1 tachyon4_pcicfg Tachyon 4 PCI Configuration lbits:1 tachyon4_gbic Tachyon 4 GBIC Small Form Factor ID lbits:1 tachyon3_csr Tachyon 3 CSR registers gathered lbits:1 tachyon3_pcicfg Tachyon 3 PCI Configuration lbits:1 tachyon3_gbic Tachyon 3 GBIC Small Form Factor ID lbits:1 tachyon2_csr Tachyon 2 CSR registers gathered lbits:1 tachyon2_pcicfg Tachyon 2 PCI Configuration lbits:1 tachyon2_gbic Tachyon 2 GBIC Small Form Factor ID lbits:1 tachyon1_csr Tachyon 1 CSR registers gathered lbits:1 tachyon1_pcicfg Tachyon 1 PCI Configuration lbits:1 tachyon1_gbic Tachyon 1 GBIC Small Form Factor ID lbits:1 tachyon0_csr Tachyon 0 CSR registers gathered lbits:1 tachyon0_pcicfg Tachyon 0 PCI Configuration lbits:1 tachyon0_gbic Tachyon 0 GBIC Small Form Factor ID lbits:2 rsvd Reserved {} <byte 732> {tach_flags2 (Tachyon registers gathered flags)} <byte 732> lbits:26 rsvd Reserved lbits:1 tachyon11_csr Tachyon 11 CSR registers gathered lbits:1 tachyon11_pcicfg Tachyon 11 PCI Configuration lbits:1 tachyon11_gbic Tachyon 11 GBIC Small Form Factor ID lbits:1 tachyon10_csr Tachyon 10 CSR registers gathered lbits:1 tachyon10_pcicfg Tachyon 10 PCI Configuration lbits:1 tachyon10_gbic Tachyon 10 GBIC Small Form Factor ID {} <byte 736> {tach_ncfg_flags (Tachyon non-configuration registers gathered flags)} <byte 736> lbits:1 tachyon9_ncfghi Tachyon 9 Non-configuration--high registers gathered lbits:1 tachyon9_ncfglo Tachyon 9 Non-configuration--low registers gathered lbits:1 tachyon8_ncfghi Tachyon 8 Non-configuration--high registers gathered lbits:1 tachyon8_ncfglo Tachyon 8 Non-configuration--low registers gathered lbits:1 tachyon7_ncfghi Tachyon 7 Non-configuration--high registers gathered lbits:1 tachyon7_ncfglo Tachyon 7 Non-configuration--low registers gathered lbits:1 tachyon6_ncfghi Tachyon 6 Non-configuration--high registers gathered lbits:1 tachyon6_ncfglo Tachyon 6 Non-configuration--low registers gathered lbits:1 tachyon5_ncfghi Tachyon 5 Non-configuration--high registers gathered lbits:1 tachyon5_ncfglo Tachyon 5 Non-configuration--low registers gathered lbits:1 tachyon4_ncfghi Tachyon 4 Non-configuration--high registers gathered lbits:1 tachyon4_ncfglo Tachyon 4 Non-configuration--low registers gathered lbits:1 tachyon3_ncfghi Tachyon 3 Non-configuration--high registers gathered lbits:1 tachyon3_ncfglo Tachyon 3 Non-configuration--low registers gathered lbits:1 tachyon2_ncfghi Tachyon 2 Non-configuration--high registers gathered lbits:1 tachyon2_ncfglo Tachyon 2 Non-configuration--low registers gathered lbits:1 tachyon1_ncfghi Tachyon 1 Non-configuration--high registers gathered lbits:1 tachyon1_ncfglo Tachyon 1 Non-configuration--low registers gathered lbits:1 tachyon0_ncfghi Tachyon 0 Non-configuration--high registers gathered lbits:1 tachyon0_ncfglo Tachyon 0 Non-configuration--low registers gathered lbits:1 tachyon10_ncfghi Tachyon 1 Non-configuration--high registers gathered lbits:1 tachyon10_ncfglo Tachyon 1 Non-configuration--low registers gathered lbits:1 tachyon11_ncfghi Tachyon 0 Non-configuration--high registers gathered lbits:1 tachyon11_ncfglo Tachyon 0 Non-configuration--low registers gathered lbits:8 rsvd Reserved {} <byte 740> {aa3 (Atlantis registers--Area3)} <byte 740>

ulong[518] reserved Reserved for future use {} <byte 2812> {aa2 (Atlantis registers--Area2)} <byte 2812> ulong[200] reserved Reserved for future use {} <byte 3612> {atlantis_a1 (Atlantis Area 1 miscellaneous registers)} <byte 3612> union cpu_configuration (Offset 0x0000) CPU Configuration <byte 3612> {field (By field)} <byte 3612> lbits:8 nomatchcnt RW CPU Address Miss Counter lbits:1 nomatchcnten RW CPU Address Miss Counter Enable lbits:1 nomatchcntext RW CPU address miss counter MSB lbits:1 reserved4 RES Reserved lbits:1 singlecpu RW 0 = Dual CPU. 1 = Single CPU lbits:1 endianess RW CPU Bus Byte Orientation. Must be 0 lbits:1 pipeline RW Pipeline Enable lbits:3 reserved3 RES Reserved lbits:1 stopretry RW Stop to retry transactions from PCI lbits:1 multigtdec RW Multi-GT Address Decode lbits:1 dpvalid RW CPU DP[0-7] Connection lbits:2 reserved2 RES Reserved lbits:1 perrprop RW Parity Error Propagation lbits:2 reserved1 RES Reserved lbits:1 aackdelay2 RW AACK# earliest assertion following TS# lbits:1 apvalid RW CPU AP[0-3] Connection lbits:1 remapwrdis RW Address Remap Registers Write Control lbits:4 reserved0 RES Reserved {} or cpu_configuration (Offset 0x0000) CPU Configuration <byte 3612> ulong value As longword endunion cpu_configuration (Offset 0x0000) CPU Configuration <byte 3616> union cs_0_base_address (Offset 0x0008) CS[0]# Base Address <byte 3616> {field (By field)} <byte 3616> lbits:20 base RW Base Address lbits:12 reserved0 RES Reserved {} or cs_0_base_address (Offset 0x0008) CS[0]# Base Address <byte 3616> ulong value As longword endunion cs_0_base_address (Offset 0x0008) CS[0]# Base Address <byte 3620> union cs_0_size (Offset 0x0010) CS[0]# Size <byte 3620> {field (By field)} <byte 3620> lbits:16 size RW Bank Size lbits:16 reserved0 RES Reserved {} or cs_0_size (Offset 0x0010) CS[0]# Size <byte 3620> ulong value As longword

endunion cs_0_size (Offset 0x0010) CS[0]# Size <byte 3624> union cs_2_base_address (Offset 0x0018) CS[2]# Base Address <byte 3624> {field (By field)} <byte 3624> lbits:20 base RW Base Address lbits:12 reserved0 RES Reserved {} or cs_2_base_address (Offset 0x0018) CS[2]# Base Address <byte 3624> ulong value As longword endunion cs_2_base_address (Offset 0x0018) CS[2]# Base Address <byte 3628> union cs_2_size (Offset 0x0020) CS[2]# Size <byte 3628> {field (By field)} <byte 3628> lbits:16 size RW Bank Size lbits:16 reserved0 RES Reserved {} or cs_2_size (Offset 0x0020) CS[2]# Size <byte 3628> ulong value As longword endunion cs_2_size (Offset 0x0020) CS[2]# Size <byte 3632> union cs_1_base_address (Offset 0x0208) CS[1]# Base Address <byte 3632> {field (By field)} <byte 3632> lbits:20 base RW Base Address lbits:12 reserved0 RES Reserved {} or cs_1_base_address (Offset 0x0208) CS[1]# Base Address <byte 3632> ulong value As longword endunion cs_1_base_address (Offset 0x0208) CS[1]# Base Address <byte 3636> union cs_1_size (Offset 0x0210) CS[1]# Size <byte 3636> {field (By field)} <byte 3636> lbits:16 size RW Bank Size lbits:16 reserved0 RES Reserved {} or cs_1_size (Offset 0x0210) CS[1]# Size <byte 3636> ulong value As longword endunion cs_1_size (Offset 0x0210) CS[1]# Size <byte 3640> union cs_3_base_address (Offset 0x0218) CS[3]# Base Address <byte 3640> {field (By field)} <byte 3640> lbits:20 base RW Base Address lbits:12 reserved0 RES Reserved {} or cs_3_base_address (Offset 0x0218) CS[3]# Base Address <byte 3640> ulong value As longword

endunion cs_3_base_address (Offset 0x0218) CS[3]# Base Address <byte 3644> union cs_3_size (Offset 0x0220) CS[3]# Size <byte 3644> {field (By field)} <byte 3644> lbits:16 size RW Bank Size lbits:16 reserved0 RES Reserved {} or cs_3_size (Offset 0x0220) CS[3]# Size <byte 3644> ulong value As longword endunion cs_3_size (Offset 0x0220) CS[3]# Size <byte 3648> union base_address_enable (Offset 0x0278) Base Address Enable <byte 3648> {field (By field)} <byte 3648> lbits:1 encs_0 RW CS[0] base address enable lbits:1 encs_1 RW CS[1] base address enable lbits:1 encs_2 RW CS[2] base address enable lbits:1 encs_3 RW CS[3] base address enable lbits:1 endevcs_0 RW DevCS[0] base address enable lbits:1 endevcs_1 RW DevCS[1] base address enable lbits:1 endevcs_2 RW DevCS[2] base address enable lbits:1 endevcs_3 RW DevCS[3] base address enable lbits:1 enbootcs RW BootCS base address enable lbits:1 enpci_0_io RW PCI_0 I/O base address enable lbits:1 enpci_0_mem0 RW PCI_0 Mem0 base address enable lbits:1 enpci_0_mem1 RW PCI_0 Mem1 base address enable lbits:1 enpci_0_mem2 RW PCI_0 Mem2 base address enable lbits:1 enpci_0_mem3 RW PCI_0 Mem3 base address enable lbits:1 enpci_1_io RW PCI_1 I/O base address enable lbits:1 enpci_1_mem0 RW PCI_1 Mem0 base address enable lbits:1 enpci_1_mem1 RW PCI_1 Mem1 base address enable lbits:1 enpci_1_mem2 RW PCI_1 Mem2 base address enable lbits:1 enpci_1_mem3 RW PCI_1 Mem3 base address enable lbits:1 enintegr_sram RW Integrated SRAM base address enable lbits:1 eninter_space RW Internal Space base address enable lbits:11 reserved0 RES Reserved {} or base_address_enable (Offset 0x0278) Base Address Enable <byte 3648> ulong value As longword endunion base_address_enable (Offset 0x0278) Base Address Enable <byte 3652> union idma_channel_0_dma_byte_count (Offset 0x0800) IDMA Channel 0 DMA Byte Coun t <byte 3652> {field (By field)} <byte 3652> lbits:24 bytecnt RW Number of bytes left for the DMA to transfer lbits:6 reserved0 RES Reserved lbits:1 bcleft RW Left Byte Count lbits:1 own RW Ownership Bit {} or idma_channel_0_dma_byte_count (Offset 0x0800) IDMA Channel 0 DMA Byte Count <byte 3652> ulong value As longword endunion idma_channel_0_dma_byte_count (Offset 0x0800) IDMA Channel 0 DMA Byte C

ount <byte 3656> union idma_channel_1_dma_byte_count (Offset 0x0804) IDMA Channel 1 DMA Byte Coun t <byte 3656> {field (By field)} <byte 3656> lbits:24 bytecnt RW Number of bytes left for the DMA to transfer lbits:6 reserved0 RES Reserved lbits:1 bcleft RW Left Byte Count lbits:1 own RW Ownership Bit {} or idma_channel_1_dma_byte_count (Offset 0x0804) IDMA Channel 1 DMA Byte Count <byte 3656> ulong value As longword endunion idma_channel_1_dma_byte_count (Offset 0x0804) IDMA Channel 1 DMA Byte C ount <byte 3660> union idma_channel_2_dma_byte_count (Offset 0x0808) IDMA Channel 2 DMA Byte Coun t <byte 3660> {field (By field)} <byte 3660> lbits:24 bytecnt RW Number of bytes left for the DMA to transfer lbits:6 reserved0 RES Reserved lbits:1 bcleft RW Left Byte Count lbits:1 own RW Ownership Bit {} or idma_channel_2_dma_byte_count (Offset 0x0808) IDMA Channel 2 DMA Byte Count <byte 3660> ulong value As longword endunion idma_channel_2_dma_byte_count (Offset 0x0808) IDMA Channel 2 DMA Byte C ount <byte 3664> union idma_channel_3_dma_byte_count (Offset 0x080C) IDMA Channel 3 DMA Byte Coun t <byte 3664> {field (By field)} <byte 3664> lbits:24 bytecnt RW Number of bytes left for the DMA to transfer lbits:6 reserved0 RES Reserved lbits:1 bcleft RW Left Byte Count lbits:1 own RW Ownership Bit {} or idma_channel_3_dma_byte_count (Offset 0x080C) IDMA Channel 3 DMA Byte Count <byte 3664> ulong value As longword endunion idma_channel_3_dma_byte_count (Offset 0x080C) IDMA Channel 3 DMA Byte C ount <byte 3668> union idma_channel_0_dma_source_address (Offset 0x0810) IDMA Channel 0 DMA Sourc e Address <byte 3668> {field (By field)} <byte 3668> lbits:32 srcadd RW Bits[31:0] of the DMA source address {} or idma_channel_0_dma_source_address (Offset 0x0810) IDMA Channel 0 DMA Source A ddress <byte 3668>

ulong value As longword endunion idma_channel_0_dma_source_address (Offset 0x0810) IDMA Channel 0 DMA So urce Address <byte 3672> union idma_channel_1_dma_source_address (Offset 0x0814) IDMA Channel 1 DMA Sourc e Address <byte 3672> {field (By field)} <byte 3672> lbits:32 srcadd RW Bits[31:0] of the DMA source address {} or idma_channel_1_dma_source_address (Offset 0x0814) IDMA Channel 1 DMA Source A ddress <byte 3672> ulong value As longword endunion idma_channel_1_dma_source_address (Offset 0x0814) IDMA Channel 1 DMA So urce Address <byte 3676> union idma_channel_2_dma_source_address (Offset 0x0818) IDMA Channel 2 DMA Sourc e Address <byte 3676> {field (By field)} <byte 3676> lbits:32 srcadd RW Bits[31:0] of the DMA source address {} or idma_channel_2_dma_source_address (Offset 0x0818) IDMA Channel 2 DMA Source A ddress <byte 3676> ulong value As longword endunion idma_channel_2_dma_source_address (Offset 0x0818) IDMA Channel 2 DMA So urce Address <byte 3680> union idma_channel_3_dma_source_address (Offset 0x081C) IDMA Channel 3 DMA Sourc e Address <byte 3680> {field (By field)} <byte 3680> lbits:32 srcadd RW Bits[31:0] of the DMA source address {} or idma_channel_3_dma_source_address (Offset 0x081C) IDMA Channel 3 DMA Source A ddress <byte 3680> ulong value As longword endunion idma_channel_3_dma_source_address (Offset 0x081C) IDMA Channel 3 DMA So urce Address <byte 3684> union idma_channel_0_dma_destination_address (Offset 0x0820) IDMA Channel 0 DMA Destination Address <byte 3684> {field (By field)} <byte 3684> lbits:32 destadd RW Bits[31:0] of the DMA destination address {} or idma_channel_0_dma_destination_address (Offset 0x0820) IDMA Channel 0 DMA Des tination Address <byte 3684> ulong value As longword endunion idma_channel_0_dma_destination_address (Offset 0x0820) IDMA Channel 0 D MA Destination Address <byte 3688>

union idma_channel_1_dma_destination_address (Offset 0x0824) IDMA Channel 1 DMA Destination Address <byte 3688> {field (By field)} <byte 3688> lbits:32 destadd RW Bits[31:0] of the DMA destination address {} or idma_channel_1_dma_destination_address (Offset 0x0824) IDMA Channel 1 DMA Des tination Address <byte 3688> ulong value As longword endunion idma_channel_1_dma_destination_address (Offset 0x0824) IDMA Channel 1 D MA Destination Address <byte 3692> union idma_channel_2_dma_destination_address (Offset 0x0828) IDMA Channel 2 DMA Destination Address <byte 3692> {field (By field)} <byte 3692> lbits:32 destadd RW Bits[31:0] of the DMA destination address {} or idma_channel_2_dma_destination_address (Offset 0x0828) IDMA Channel 2 DMA Des tination Address <byte 3692> ulong value As longword endunion idma_channel_2_dma_destination_address (Offset 0x0828) IDMA Channel 2 D MA Destination Address <byte 3696> union idma_channel_3_dma_destination_address (Offset 0x082C) IDMA Channel 3 DMA Destination Address <byte 3696> {field (By field)} <byte 3696> lbits:32 destadd RW Bits[31:0] of the DMA destination address {} or idma_channel_3_dma_destination_address (Offset 0x082C) IDMA Channel 3 DMA Des tination Address <byte 3696> ulong value As longword endunion idma_channel_3_dma_destination_address (Offset 0x082C) IDMA Channel 3 D MA Destination Address <byte 3700> union idma_channel_0_next_descriptor_pointer (Offset 0x0830) IDMA Channel 0 Next Descriptor Pointer <byte 3700> {field (By field)} <byte 3700> lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address {} or idma_channel_0_next_descriptor_pointer (Offset 0x0830) IDMA Channel 0 Next De scriptor Pointer <byte 3700> ulong value As longword endunion idma_channel_0_next_descriptor_pointer (Offset 0x0830) IDMA Channel 0 N ext Descriptor Pointer <byte 3704> union idma_channel_1_next_descriptor_pointer (Offset 0x0834) IDMA Channel 1 Next Descriptor Pointer <byte 3704> {field (By field)}

<byte 3704> lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address {} or idma_channel_1_next_descriptor_pointer (Offset 0x0834) IDMA Channel 1 Next De scriptor Pointer <byte 3704> ulong value As longword endunion idma_channel_1_next_descriptor_pointer (Offset 0x0834) IDMA Channel 1 N ext Descriptor Pointer <byte 3708> union idma_channel_2_next_descriptor_pointer (Offset 0x0838) IDMA Channel 2 Next Descriptor Pointer <byte 3708> {field (By field)} <byte 3708> lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address {} or idma_channel_2_next_descriptor_pointer (Offset 0x0838) IDMA Channel 2 Next De scriptor Pointer <byte 3708> ulong value As longword endunion idma_channel_2_next_descriptor_pointer (Offset 0x0838) IDMA Channel 2 N ext Descriptor Pointer <byte 3712> union idma_channel_3_next_descriptor_pointer (Offset 0x083C) IDMA Channel 3 Next Descriptor Pointer <byte 3712> {field (By field)} <byte 3712> lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address {} or idma_channel_3_next_descriptor_pointer (Offset 0x083C) IDMA Channel 3 Next De scriptor Pointer <byte 3712> ulong value As longword endunion idma_channel_3_next_descriptor_pointer (Offset 0x083C) IDMA Channel 3 N ext Descriptor Pointer <byte 3716> union idma_channel_0_control_low (Offset 0x0840) IDMA Channel 0 Control (Low) <byte 3716> {field (By field)} <byte 3716> lbits:3 dstburstlimit RW Destination burst limit in each DMA access lbits:1 srchold RW Source Hold lbits:1 dmaack_width RW DMA ack width lbits:1 desthold RW Destination Hold lbits:3 srcburstlimit RW Source burst limit in each DMA access lbits:1 chainmode RW Chained Mode lbits:1 intmode RW Interrupt Mode lbits:1 demandmode RW Demand Mode Enable lbits:1 chanen RW Channel Enable lbits:1 fetchnd RWC Fetch Next Descriptor lbits:1 chanact RO DMA Channel Active lbits:1 dmareqdir RW DMAReq Direction lbits:1 dmareqmode RW DMAReq# Mode lbits:1 cden RW Close Descriptor Enable lbits:1 eoten RW End Of Transfer Enable lbits:1 eotmode RW End of Transfer Affect lbits:1 abr RW Channel Abort lbits:2 saddrovr RW Override Source Address

lbits:2 daddrovr RW Override Destination Address lbits:2 naddrovr RW Override Next Descriptor Address lbits:1 dmaackmode RW DMA Acknowledge Mode lbits:1 timerreq RW Timer DMA Request Enable lbits:2 dmaackdir RW DMA Acknowledge Direction lbits:1 descmode RW Descriptor Mode {} or idma_channel_0_control_low (Offset 0x0840) IDMA Channel 0 Control (Low) <byte 3716> ulong value As longword endunion idma_channel_0_control_low (Offset 0x0840) IDMA Channel 0 Control (Low) <byte 3720> union idma_channel_1_control_low (Offset 0x0844) IDMA Channel 1 Control (Low) <byte 3720> {field (By field)} <byte 3720> lbits:3 dstburstlimit RW Destination burst limit in each DMA access lbits:1 srchold RW Source Hold lbits:1 dmaack_width RW DMA ack width lbits:1 desthold RW Destination Hold lbits:3 srcburstlimit RW Source burst limit in each DMA access lbits:1 chainmode RW Chained Mode lbits:1 intmode RW Interrupt Mode lbits:1 demandmode RW Demand Mode Enable lbits:1 chanen RW Channel Enable lbits:1 fetchnd RWC Fetch Next Descriptor lbits:1 chanact RO DMA Channel Active lbits:1 dmareqdir RW DMAReq Direction lbits:1 dmareqmode RW DMAReq# Mode lbits:1 cden RW Close Descriptor Enable lbits:1 eoten RW End Of Transfer Enable lbits:1 eotmode RW End of Transfer Affect lbits:1 abr RW Channel Abort lbits:2 saddrovr RW Override Source Address lbits:2 daddrovr RW Override Destination Address lbits:2 naddrovr RW Override Next Descriptor Address lbits:1 dmaackmode RW DMA Acknowledge Mode lbits:1 timerreq RW Timer DMA Request Enable lbits:2 dmaackdir RW DMA Acknowledge Direction lbits:1 descmode RW Descriptor Mode {} or idma_channel_1_control_low (Offset 0x0844) IDMA Channel 1 Control (Low) <byte 3720> ulong value As longword endunion idma_channel_1_control_low (Offset 0x0844) IDMA Channel 1 Control (Low) <byte 3724> union idma_channel_2_control_low (Offset 0x0848) IDMA Channel 2 Control (Low) <byte 3724> {field (By field)} <byte 3724> lbits:3 dstburstlimit RW Destination burst limit in each DMA access lbits:1 srchold RW Source Hold lbits:1 dmaack_width RW DMA ack width lbits:1 desthold RW Destination Hold lbits:3 srcburstlimit RW Source burst limit in each DMA access lbits:1 chainmode RW Chained Mode lbits:1 intmode RW Interrupt Mode lbits:1 demandmode RW Demand Mode Enable lbits:1 chanen RW Channel Enable lbits:1 fetchnd RWC Fetch Next Descriptor

lbits:1 chanact RO DMA Channel Active lbits:1 dmareqdir RW DMAReq Direction lbits:1 dmareqmode RW DMAReq# Mode lbits:1 cden RW Close Descriptor Enable lbits:1 eoten RW End Of Transfer Enable lbits:1 eotmode RW End of Transfer Affect lbits:1 abr RW Channel Abort lbits:2 saddrovr RW Override Source Address lbits:2 daddrovr RW Override Destination Address lbits:2 naddrovr RW Override Next Descriptor Address lbits:1 dmaackmode RW DMA Acknowledge Mode lbits:1 timerreq RW Timer DMA Request Enable lbits:2 dmaackdir RW DMA Acknowledge Direction lbits:1 descmode RW Descriptor Mode {} or idma_channel_2_control_low (Offset 0x0848) IDMA Channel 2 Control (Low) <byte 3724> ulong value As longword endunion idma_channel_2_control_low (Offset 0x0848) IDMA Channel 2 Control (Low) <byte 3728> union idma_channel_3_control_low (Offset 0x084C) IDMA Channel 3 Control (Low) <byte 3728> {field (By field)} <byte 3728> lbits:3 dstburstlimit RW Destination burst limit in each DMA access lbits:1 srchold RW Source Hold lbits:1 dmaack_width RW DMA ack width lbits:1 desthold RW Destination Hold lbits:3 srcburstlimit RW Source burst limit in each DMA access lbits:1 chainmode RW Chained Mode lbits:1 intmode RW Interrupt Mode lbits:1 demandmode RW Demand Mode Enable lbits:1 chanen RW Channel Enable lbits:1 fetchnd RWC Fetch Next Descriptor lbits:1 chanact RO DMA Channel Active lbits:1 dmareqdir RW DMAReq Direction lbits:1 dmareqmode RW DMAReq# Mode lbits:1 cden RW Close Descriptor Enable lbits:1 eoten RW End Of Transfer Enable lbits:1 eotmode RW End of Transfer Affect lbits:1 abr RW Channel Abort lbits:2 saddrovr RW Override Source Address lbits:2 daddrovr RW Override Destination Address lbits:2 naddrovr RW Override Next Descriptor Address lbits:1 dmaackmode RW DMA Acknowledge Mode lbits:1 timerreq RW Timer DMA Request Enable lbits:2 dmaackdir RW DMA Acknowledge Direction lbits:1 descmode RW Descriptor Mode {} or idma_channel_3_control_low (Offset 0x084C) IDMA Channel 3 Control (Low) <byte 3728> ulong value As longword endunion idma_channel_3_control_low (Offset 0x084C) IDMA Channel 3 Control (Low) <byte 3732> union idma_arbiter_control (Offset 0x0860) IDMA Arbiter Control <byte 3732> {field (By field)} <byte 3732> lbits:2 arb0 RW Slice 0 of 'pizza arbiter' lbits:2 arb1 RW Slice 1 of 'pizza arbiter'

lbits:2 arb2 RW Slice 2 of 'pizza arbiter' lbits:2 arb3 RW Slice 3 of 'pizza arbiter' lbits:2 arb4 RW Slice 4 of 'pizza arbiter' lbits:2 arb5 RW Slice 5 of 'pizza arbiter' lbits:2 arb6 RW Slice 6 of 'pizza arbiter' lbits:2 arb7 RW Slice 7 of 'pizza arbiter' lbits:2 arb8 RW Slice 8 of 'pizza arbiter' lbits:2 arb9 RW Slice 9 of 'pizza arbiter' lbits:2 arb10 RW Slice 10 of 'pizza arbiter' lbits:2 arb11 RW Slice 11 of 'pizza arbiter' lbits:2 arb12 RW Slice 12 of 'pizza arbiter' lbits:2 arb13 RW Slice 13 of 'pizza arbiter' lbits:2 arb14 RW Slice 14 of 'pizza arbiter' lbits:2 arb15 RW Slice 15 of 'pizza arbiter' {} or idma_arbiter_control (Offset 0x0860) IDMA Arbiter Control <byte 3732> ulong value As longword endunion idma_arbiter_control (Offset 0x0860) IDMA Arbiter Control <byte 3736> union idma_base_address_register_0 (Offset 0x0A00) IDMA Base Address Register 0 <byte 3736> {field (By field)} <byte 3736> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3736> union attr Target specific attributes <byte 3740> {dramti (DRAM Target Interface)} <byte 3740> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3736> {dbti (Device Bus Target Interface)} <byte 3736> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3736> {pci01ti (PCI0/1 Target Interface)} <byte 3736> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3736> utiny value As byte endunion attr Target specific attributes <byte 3737> lbits:16 base RW Base Address {} or idma_base_address_register_0 (Offset 0x0A00) IDMA Base Address Register 0

<byte 3736> ulong value As longword endunion idma_base_address_register_0 (Offset 0x0A00) IDMA Base Address Register 0 <byte 3740> union idma_size_register_0 (Offset 0x0A04) IDMA Size Register 0 <byte 3740> {field (By field)} <byte 3740> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_0 (Offset 0x0A04) IDMA Size Register 0 <byte 3740> ulong value As longword endunion idma_size_register_0 (Offset 0x0A04) IDMA Size Register 0 <byte 3744> union idma_base_address_register_1 (Offset 0x0A08) IDMA Base Address Register 1 <byte 3744> {field (By field)} <byte 3744> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3744> union attr Target specific attributes <byte 3748> {dramti (DRAM Target Interface)} <byte 3748> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3744> {dbti (Device Bus Target Interface)} <byte 3744> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3744> {pci01ti (PCI0/1 Target Interface)} <byte 3744> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3744> utiny value As byte endunion attr Target specific attributes <byte 3745> lbits:16 base RW Base Address {} or idma_base_address_register_1 (Offset 0x0A08) IDMA Base Address Register 1 <byte 3744> ulong value As longword endunion idma_base_address_register_1 (Offset 0x0A08) IDMA Base Address Register

1 <byte 3748> union idma_size_register_1 (Offset 0x0A0C) IDMA Size Register 1 <byte 3748> {field (By field)} <byte 3748> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_1 (Offset 0x0A0C) IDMA Size Register 1 <byte 3748> ulong value As longword endunion idma_size_register_1 (Offset 0x0A0C) IDMA Size Register 1 <byte 3752> union idma_base_address_register_2 (Offset 0x0A10) IDMA Base Address Register 2 <byte 3752> {field (By field)} <byte 3752> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3752> union attr Target specific attributes <byte 3756> {dramti (DRAM Target Interface)} <byte 3756> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3752> {dbti (Device Bus Target Interface)} <byte 3752> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3752> {pci01ti (PCI0/1 Target Interface)} <byte 3752> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3752> utiny value As byte endunion attr Target specific attributes <byte 3753> lbits:16 base RW Base Address {} or idma_base_address_register_2 (Offset 0x0A10) IDMA Base Address Register 2 <byte 3752> ulong value As longword endunion idma_base_address_register_2 (Offset 0x0A10) IDMA Base Address Register 2 <byte 3756> union idma_size_register_2 (Offset 0x0A14) IDMA Size Register 2

<byte 3756> {field (By field)} <byte 3756> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_2 (Offset 0x0A14) IDMA Size Register 2 <byte 3756> ulong value As longword endunion idma_size_register_2 (Offset 0x0A14) IDMA Size Register 2 <byte 3760> union idma_base_address_register_3 (Offset 0x0A18) IDMA Base Address Register 3 <byte 3760> {field (By field)} <byte 3760> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3760> union attr Target specific attributes <byte 3764> {dramti (DRAM Target Interface)} <byte 3764> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3760> {dbti (Device Bus Target Interface)} <byte 3760> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3760> {pci01ti (PCI0/1 Target Interface)} <byte 3760> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3760> utiny value As byte endunion attr Target specific attributes <byte 3761> lbits:16 base RW Base Address {} or idma_base_address_register_3 (Offset 0x0A18) IDMA Base Address Register 3 <byte 3760> ulong value As longword endunion idma_base_address_register_3 (Offset 0x0A18) IDMA Base Address Register 3 <byte 3764> union idma_size_register_3 (Offset 0x0A1C) IDMA Size Register 3 <byte 3764> {field (By field)} <byte 3764>

lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_3 (Offset 0x0A1C) IDMA Size Register 3 <byte 3764> ulong value As longword endunion idma_size_register_3 (Offset 0x0A1C) IDMA Size Register 3 <byte 3768> union idma_base_address_register_4 (Offset 0x0A20) IDMA Base Address Register 4 <byte 3768> {field (By field)} <byte 3768> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3768> union attr Target specific attributes <byte 3772> {dramti (DRAM Target Interface)} <byte 3772> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3768> {dbti (Device Bus Target Interface)} <byte 3768> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3768> {pci01ti (PCI0/1 Target Interface)} <byte 3768> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3768> utiny value As byte endunion attr Target specific attributes <byte 3769> lbits:16 base RW Base Address {} or idma_base_address_register_4 (Offset 0x0A20) IDMA Base Address Register 4 <byte 3768> ulong value As longword endunion idma_base_address_register_4 (Offset 0x0A20) IDMA Base Address Register 4 <byte 3772> union idma_size_register_4 (Offset 0x0A24) IDMA Size Register 4 <byte 3772> {field (By field)} <byte 3772> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {}

or idma_size_register_4 (Offset 0x0A24) IDMA Size Register 4 <byte 3772> ulong value As longword endunion idma_size_register_4 (Offset 0x0A24) IDMA Size Register 4 <byte 3776> union idma_base_address_register_5 (Offset 0x0A28) IDMA Base Address Register 5 <byte 3776> {field (By field)} <byte 3776> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3776> union attr Target specific attributes <byte 3780> {dramti (DRAM Target Interface)} <byte 3780> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3776> {dbti (Device Bus Target Interface)} <byte 3776> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3776> {pci01ti (PCI0/1 Target Interface)} <byte 3776> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3776> utiny value As byte endunion attr Target specific attributes <byte 3777> lbits:16 base RW Base Address {} or idma_base_address_register_5 (Offset 0x0A28) IDMA Base Address Register 5 <byte 3776> ulong value As longword endunion idma_base_address_register_5 (Offset 0x0A28) IDMA Base Address Register 5 <byte 3780> union idma_size_register_5 (Offset 0x0A2C) IDMA Size Register 5 <byte 3780> {field (By field)} <byte 3780> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_5 (Offset 0x0A2C) IDMA Size Register 5 <byte 3780> ulong value As longword

endunion idma_size_register_5 (Offset 0x0A2C) IDMA Size Register 5 <byte 3784> union idma_base_address_register_6 (Offset 0x0A30) IDMA Base Address Register 6 <byte 3784> {field (By field)} <byte 3784> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3784> union attr Target specific attributes <byte 3788> {dramti (DRAM Target Interface)} <byte 3788> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3784> {dbti (Device Bus Target Interface)} <byte 3784> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3784> {pci01ti (PCI0/1 Target Interface)} <byte 3784> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3784> utiny value As byte endunion attr Target specific attributes <byte 3785> lbits:16 base RW Base Address {} or idma_base_address_register_6 (Offset 0x0A30) IDMA Base Address Register 6 <byte 3784> ulong value As longword endunion idma_base_address_register_6 (Offset 0x0A30) IDMA Base Address Register 6 <byte 3788> union idma_size_register_6 (Offset 0x0A34) IDMA Size Register 6 <byte 3788> {field (By field)} <byte 3788> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_6 (Offset 0x0A34) IDMA Size Register 6 <byte 3788> ulong value As longword endunion idma_size_register_6 (Offset 0x0A34) IDMA Size Register 6 <byte 3792> union idma_base_address_register_7 (Offset 0x0A38) IDMA Base Address Register 7

<byte 3792> {field (By field)} <byte 3792> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3792> union attr Target specific attributes <byte 3796> {dramti (DRAM Target Interface)} <byte 3796> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3792> {dbti (Device Bus Target Interface)} <byte 3792> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3792> {pci01ti (PCI0/1 Target Interface)} <byte 3792> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3792> utiny value As byte endunion attr Target specific attributes <byte 3793> lbits:16 base RW Base Address {} or idma_base_address_register_7 (Offset 0x0A38) IDMA Base Address Register 7 <byte 3792> ulong value As longword endunion idma_base_address_register_7 (Offset 0x0A38) IDMA Base Address Register 7 <byte 3796> union idma_size_register_7 (Offset 0x0A3C) IDMA Size Register 7 <byte 3796> {field (By field)} <byte 3796> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_7 (Offset 0x0A3C) IDMA Size Register 7 <byte 3796> ulong value As longword endunion idma_size_register_7 (Offset 0x0A3C) IDMA Size Register 7 <byte 3800> union idma_base_address_enable (Offset 0x0A80) IDMA Base Address Enable <byte 3800> {field (By field)} <byte 3800>

lbits:1 en0 RW Address window 0 enable lbits:1 en1 RW Address window 1 enable lbits:1 en2 RW Address window 2 enable lbits:1 en3 RW Address window 3 enable lbits:1 en4 RW Address window 4 enable lbits:1 en5 RW Address window 5 enable lbits:1 en6 RW Address window 6 enable lbits:1 en7 RW Address window 7 enable lbits:24 reserved0 RO Reserved, read only {} or idma_base_address_enable (Offset 0x0A80) IDMA Base Address Enable <byte 3800> ulong value As longword endunion idma_base_address_enable (Offset 0x0A80) IDMA Base Address Enable <byte 3804> union sdram_configuration (Offset 0x1400) SDRAM Configuration <byte 3804> {field (By field)} <byte 3804> lbits:14 refresh Refresh rate of DIMM lbits:1 pinter Physical interleaving lbits:1 vinter Virtual interleaving lbits:1 reserved1 Reserved lbits:1 regdram Registered DRAM lbits:1 ecc Enable ECC lbits:1 reserved2 Reserved lbits:2 dqs # DQS pins lbits:4 reserved3 Reserved lbits:6 rdbuff Read Buffer assignment {} or sdram_configuration (Offset 0x1400) SDRAM Configuration <byte 3804> ulong value As longword endunion sdram_configuration (Offset 0x1400) SDRAM Configuration <byte 3808> union dunit_control_low (Offset 0x1404) Dunit Control (Low) <byte 3808> {field (By field)} <byte 3808> lbits:1 clksync RW Clock Domains Synchronization lbits:1 rdsyncsel RW Read Data Synchronization Select lbits:1 rdctrltdel RW Read Control Logic Delay lbits:1 rddatadel RW Read Data Delay lbits:2 ctrlpipe RW Number of pipeline stages in the Dunit control path lbits:1 ctrlpos RW Address/Control Output Timing lbits:1 rdpipe RW Number of pipeline stages in the read data path lbits:1 rdsyncen RW Read Data Path Synchronization lbits:1 rmwsyncen RW RMW Path Synchronization lbits:1 cpupriority RW CPU priority assignment lbits:1 pci_0priority RW PCI_0 priority assignment lbits:1 pci_1priority RW PCI_1 priority assignment lbits:1 mpscpriority RW MPSC priority assignment lbits:1 idmapriority RW IDMA priority assignment lbits:1 gbpriority RW Gb priority assignment lbits:4 lcnt RW Arbiter Low Priority Counter lbits:4 hcnt RW Arbiter High Priority Counter lbits:3 stburstdel RW Number of sample stages on StartBurstIn lbits:1 stburstneg RW StartBurstIn is first sampled on the falling edge of cl ock lbits:1 stburstsrc RW StartBurst source

lbits:1 rddataneg RW Read data is first sampled with falling edge of clock lbits:2 reserved0 RES Reserved {} or dunit_control_low (Offset 0x1404) Dunit Control (Low) <byte 3808> ulong value As longword endunion dunit_control_low (Offset 0x1404) Dunit Control (Low) <byte 3812> union atlantis_sdram_timing_l (Offset 0x1408) SDRAM Timing (Low) <byte 3812> {field (By field)} <byte 3812> lbits:4 Tdqss Write to DQS lbits:4 Trcd Activate to command lbits:4 Trp Precharge command period lbits:4 Twr Write command to precharge lbits:4 Twtr Write command to read command lbits:4 Tras Minimum row active time lbits:4 Trrd Activate bank A to activate bank B lbits:4 reserved Reserved {} or atlantis_sdram_timing_l (Offset 0x1408) SDRAM Timing (Low) <byte 3812> ulong value As longword endunion atlantis_sdram_timing_l (Offset 0x1408) SDRAM Timing (Low) <byte 3816> union atlantis_sdram_timing_h (Offset 0x140C) SDRAM Timing (High) <byte 3816> {field (By field)} <byte 3816> lbits:4 Trfc Refresh command period lbits:2 Trd2rd Minimum gap between DRAM read accesses lbits:2 Trd2wr Minimum gap between DRAM read and write accesses lbits:24 reserved Write command to precharge {} or atlantis_sdram_timing_h (Offset 0x140C) SDRAM Timing (High) <byte 3816> ulong value As longword endunion atlantis_sdram_timing_h (Offset 0x140C) SDRAM Timing (High) <byte 3820> union sdram_address_control (Offset 0x1410) SDRAM Address Control <byte 3820> {field (By field)} <byte 3820> lbits:4 addrsel RW SDRAM Address Select lbits:2 dcfg RW SDRAM Device Configuration lbits:26 reserved0 RES Reserved {} or sdram_address_control (Offset 0x1410) SDRAM Address Control <byte 3820> ulong value As longword endunion sdram_address_control (Offset 0x1410) SDRAM Address Control <byte 3824> union sdram_open_pages_control (Offset 0x1414) SDRAM Open Pages Control <byte 3824> {field (By field)} <byte 3824> lbits:1 ope0 RW Open Page Enable CS[0]# bank0 lbits:1 ope1 RW Open Page Enable CS[0]# bank1 lbits:1 ope2 RW Open Page Enable CS[0]# bank2

lbits:1 ope3 RW Open Page Enable CS[0]# bank3 lbits:1 ope4 RW Open Page Enable CS[1]# bank0 lbits:1 ope5 RW Open Page Enable CS[1]# bank1 lbits:1 ope6 RW Open Page Enable CS[1]# bank2 lbits:1 ope7 RW Open Page Enable CS[1]# bank3 lbits:1 ope8 RW Open Page Enable CS[2]# bank0 lbits:1 ope9 RW Open Page Enable CS[2]# bank1 lbits:1 ope10 RW Open Page Enable CS[2]# bank2 lbits:1 ope11 RW Open Page Enable CS[2]# bank3 lbits:1 ope12 RW Open Page Enable CS[3]# bank0 lbits:1 ope13 RW Open Page Enable CS[3]# bank1 lbits:1 ope14 RW Open Page Enable CS[3]# bank2 lbits:1 ope15 RW Open Page Enable CS[3]# bank3 lbits:16 reserved0 RES Reserved {} or sdram_open_pages_control (Offset 0x1414) SDRAM Open Pages Control <byte 3824> ulong value As longword endunion sdram_open_pages_control (Offset 0x1414) SDRAM Open Pages Control <byte 3828> union sdram_operation (Offset 0x1418) SDRAM Operation <byte 3828> {field (By field)} <byte 3828> lbits:3 cmd RW DRAM Mode Select lbits:29 reserved0 RES Reserved {} or sdram_operation (Offset 0x1418) SDRAM Operation <byte 3828> ulong value As longword endunion sdram_operation (Offset 0x1418) SDRAM Operation <byte 3832> union sdram_mode (Offset 0x141C) SDRAM Mode <byte 3832> {field (By field)} <byte 3832> lbits:3 bl RW Burst Length lbits:1 bt RW Burst Type/Init Val lbits:3 cl RW CAS Latency lbits:7 om RW Operation Mode lbits:18 reserved0 RES Reserved {} or sdram_mode (Offset 0x141C) SDRAM Mode <byte 3832> ulong value As longword endunion sdram_mode (Offset 0x141C) SDRAM Mode <byte 3836> union extsdram_mode (Offset 0x1420) Extended SDRAM Mode <byte 3836> {field (By field)} <byte 3836> lbits:1 dll RW DRAM DLL Enable lbits:1 ds RW DRAM Drive Strength lbits:1 qfc RW QFC Signal Enable lbits:11 om RW Operation Mode lbits:18 reserved0 RES Reserved {} or extsdram_mode (Offset 0x1420) Extended SDRAM Mode <byte 3836> ulong value As longword

endunion extsdram_mode (Offset 0x1420) Extended SDRAM Mode <byte 3840> union dunit_control_high (Offset 0x1424) Dunit Control (High) <byte 3840> {field (By field)} <byte 3840> lbits:4 wrbuff RW Reserved lbits:4 rdbuff RW Reserved lbits:4 txque RW Reserved lbits:4 wrtrig RW Reserved lbits:4 rdtrig RW Reserved lbits:4 rmwtrig RW Reserved lbits:1 snooppipe RW Snoops pipeline enable lbits:4 snoopdepth RW Reserved lbits:3 reserved0 RES Reserved {} or dunit_control_high (Offset 0x1424) Dunit Control (High) <byte 3840> ulong value As longword endunion dunit_control_high (Offset 0x1424) Dunit Control (High) <byte 3844> union sdram_interface_crossbar_control_low (Offset 0x1430) SDRAM Interface Cross bar Control (Low) <byte 3844> {field (By field)} <byte 3844> lbits:4 arb0 RW Slice 0 of the device controller 'pizza' arbiter lbits:4 arb1 RW Slice 1 of the device controller 'pizza' arbiter lbits:4 arb2 RW Slice 2 of the device controller 'pizza' arbiter lbits:4 arb3 RW Slice 3 of the device controller 'pizza' arbiter lbits:4 arb4 RW Slice 4 of the device controller 'pizza' arbiter lbits:4 arb5 RW Slice 5 of the device controller 'pizza' arbiter lbits:4 arb6 RW Slice 6 of the device controller 'pizza' arbiter lbits:4 arb7 RW Slice 7 of the device controller 'pizza' arbiter {} or sdram_interface_crossbar_control_low (Offset 0x1430) SDRAM Interface Crossbar Control (Low) <byte 3844> ulong value As longword endunion sdram_interface_crossbar_control_low (Offset 0x1430) SDRAM Interface Cr ossbar Control (Low) <byte 3848> union sdram_interface_crossbar_control_high (Offset 0x1434) SDRAM Interface Cros sbar Control (High) <byte 3848> {field (By field)} <byte 3848> lbits:4 arb8 RW Slice 8 of the device controller 'pizza' arbiter lbits:4 arb9 RW Slice 9 of the device controller 'pizza' arbiter lbits:4 arb10 RW Slice 10 of the device controller 'pizza' arbiter lbits:4 arb11 RW Slice 11 of the device controller 'pizza' arbiter lbits:4 arb12 RW Slice 12 of the device controller 'pizza' arbiter lbits:4 arb13 RW Slice 13 of the device controller 'pizza' arbiter lbits:4 arb14 RW Slice 14 of the device controller 'pizza' arbiter lbits:4 arb15 RW Slice 15 of the device controller 'pizza' arbiter {} or sdram_interface_crossbar_control_high (Offset 0x1434) SDRAM Interface Crossba r Control (High) <byte 3848> ulong value As longword

endunion sdram_interface_crossbar_control_high (Offset 0x1434) SDRAM Interface C rossbar Control (High) <byte 3852> union sdram_interface_crossbar_timeout (Offset 0x1438) SDRAM Interface Crossbar Timeout <byte 3852> {field (By field)} <byte 3852> lbits:8 timeout RW CrossBar Arbiter Timeout Preset Value lbits:8 reserved1 RES Reserved lbits:1 timeouten RW CrossBar Arbiter Timer Enable lbits:15 reserved0 RES Reserved {} or sdram_interface_crossbar_timeout (Offset 0x1438) SDRAM Interface Crossbar Tim eout <byte 3852> ulong value As longword endunion sdram_interface_crossbar_timeout (Offset 0x1438) SDRAM Interface Crossb ar Timeout <byte 3856> union dfcdl_configuration0 (Offset 0x1480) DFCDL Configuration0 <byte 3856> {field (By field)} <byte 3856> lbits:8 updwin RW The window size, after the refresh command, in which DFCDL update is allowed lbits:5 reserved1 RES Reserved lbits:1 forceupdsync RW Forces the delay line update as soon as DFCDL is sync hronized lbits:1 forceupdw RW Forces delay line update as soon as update window arrive s lbits:1 blockupd RW Disables delay line update (unless using ForceUpdSync or ForceUpdW bits) lbits:1 updnosync RW Enables dynamic update without reaching sync condition lbits:1 updnowin RW Enables dynamic update without reaching update window lbits:1 forceacc RW Forces the filter state machine to accept bad values lbits:9 maxdiff RW Maximum difference between consecutive updates Filtering i s performed on values multiplied by 4 lbits:4 reserved0 RES Reserved {} or dfcdl_configuration0 (Offset 0x1480) DFCDL Configuration0 <byte 3856> ulong value As longword endunion dfcdl_configuration0 (Offset 0x1480) DFCDL Configuration0 <byte 3860> union dfcdl_configuration1 (Offset 0x1484) DFCDL Configuration1 <byte 3860> {field (By field)} <byte 3860> lbits:6 delpval RW Delay counter preset value lbits:1 fourcell RW Delay unit selects lbits:1 isense RW Multiply by two the value found by the search machine lbits:6 phased RW Delay Counter Phase Delta lbits:1 singlephase RW Search machine only searches for first phase lbits:1 reserved1 RES Reserved lbits:1 phasemode RW Phase Mode Jump lbits:1 reserved0 RES Reserved lbits:2 avg RW Average Value Calculation for Filter Process lbits:2 goodhits RW For the sync machine to enter the previous sync state, th e number of times the good value must be received after the bad value

lbits:2 goodsync RW For the sync machine to enter sync state, the number of t imes the good value must be received after loss of sync lbits:1 forcesync RW Forces the sync machine to enter the sync state lbits:1 holdsync RW Forces the sync machine to maintain this state lbits:1 resync RW Forces the sync machine to enter a loss of sync state lbits:2 avgrd RW Average used for read address of the SRAM lbits:1 stopimid RW Forces the filter machine to enter stop state lbits:1 stopsync RW Forces it to enter stop state, if there is sync condition lbits:1 goinit RW Forces it to remain in this state {} or dfcdl_configuration1 (Offset 0x1484) DFCDL Configuration1 <byte 3860> ulong value As longword endunion dfcdl_configuration1 (Offset 0x1484) DFCDL Configuration1 <byte 3864> union sram_address (Offset 0x1490) SRAM Address <byte 3864> {field (By field)} <byte 3864> lbits:32 addr RW SRAM address {} or sram_address (Offset 0x1490) SRAM Address <byte 3864> ulong value As longword endunion sram_address (Offset 0x1490) SRAM Address <byte 3868> union sram_data0 (Offset 0x1494) SRAM Data0 <byte 3868> {field (By field)} <byte 3868> lbits:32 data RW SRAM Write Data to initialize the DFCDL SRAM {} or sram_data0 (Offset 0x1494) SRAM Data0 <byte 3868> ulong value As longword endunion sram_data0 (Offset 0x1494) SRAM Data0 <byte 3872> union dfcdl_probe (Offset 0x14A0) DFCDL Probe <byte 3872> {field (By field)} <byte 3872> lbits:4 bussel RW Select DFCDL bus to be probed lbits:1 proben RW Probe Enabled lbits:27 reserved0 RES Reserved {} or dfcdl_probe (Offset 0x14A0) DFCDL Probe <byte 3872> ulong value As longword endunion dfcdl_probe (Offset 0x14A0) DFCDL Probe <byte 3876> union sdram_address_control_pads_calibration (Offset 0x14C0) SDRAM Address/Contr ol Pads Calibration <byte 3876> {field (By field)} <byte 3876> lbits:5 drvn RW Pad Nchannel Driving Strength lbits:5 drvp RW Pad Pchannel Driving Strength lbits:6 reserved1 RES Reserved, read only lbits:1 tuneen RW Enables the dynamic tuning of pad driving strength lbits:5 lockn RO Final locked value of the Nchannel Driving Strength

lbits:5 lockp RO Final locked value of the Pchannel Driving Strength lbits:4 reserved0 RES Reserved, read only lbits:1 wren RW Write Enable CPU Pads Calibration register {} or sdram_address_control_pads_calibration (Offset 0x14C0) SDRAM Address/Control Pads Calibration <byte 3876> ulong value As longword endunion sdram_address_control_pads_calibration (Offset 0x14C0) SDRAM Address/Co ntrol Pads Calibration <byte 3880> union sdram_data_pads_calibration (Offset 0x14C4) SDRAM Data Pads Calibration <byte 3880> {field (By field)} <byte 3880> lbits:5 drvn RW Pad Nchannel Driving Strength lbits:5 drvp RW Pad Pchannel Driving Strength lbits:6 reserved1 RES Reserved, read only lbits:1 tuneen RW Enables the dynamic tuning of pad driving strength lbits:5 lockn RO Final locked value of the Nchannel Driving Strength lbits:5 lockp RO Final locked value of the Pchannel Driving Strength lbits:4 reserved0 RES Reserved, read only lbits:1 wren RW Write Enable CPU Pads Calibration register {} or sdram_data_pads_calibration (Offset 0x14C4) SDRAM Data Pads Calibration <byte 3880> ulong value As longword endunion sdram_data_pads_calibration (Offset 0x14C4) SDRAM Data Pads Calibration <byte 3884> union twsi_slave_address (Offset 0xC000) Two-Wire Serial Interface Slave Address <byte 3884> {field (By field)} <byte 3884> lbits:1 gce RW General Call Enable lbits:7 saddr RW Slave address lbits:24 reserved0 RES Reserved {} or twsi_slave_address (Offset 0xC000) Two-Wire Serial Interface Slave Address <byte 3884> ulong value As longword endunion twsi_slave_address (Offset 0xC000) Two-Wire Serial Interface Slave Addr ess <byte 3888> union twsi_data (Offset 0xC004) Two-Wire Serial Interface Data <byte 3888> {field (By field)} <byte 3888> lbits:8 data RW Data/Address byte to be transmitted by the TWSI master or sla ve, or data byte received lbits:24 reserved0 RES Reserved {} or twsi_data (Offset 0xC004) Two-Wire Serial Interface Data <byte 3888> ulong value As longword endunion twsi_data (Offset 0xC004) Two-Wire Serial Interface Data <byte 3892> union twsi_control (Offset 0xC008) Two-Wire Serial Interface Control <byte 3892> {field (By field)} <byte 3892>

lbits:2 reserved1 RES Reserved, read only lbits:1 ack RW Acknowledge lbits:1 iflg RW Interrupt Flag lbits:1 stop RW Stop lbits:1 start RW Start lbits:1 twsien RW TWSI enable lbits:1 inten RW Interrupt Enable lbits:24 reserved0 RES Reserved {} or twsi_control (Offset 0xC008) Two-Wire Serial Interface Control <byte 3892> ulong value As longword endunion twsi_control (Offset 0xC008) Two-Wire Serial Interface Control <byte 3896> union twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Bau d Rate <byte 3896> {status (Status value)} <byte 3896> lbits:8 stat RO TWSI Status lbits:24 reserved0 RES Reserved {} or twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Baud R ate <byte 3896> {br (Baud rate)} <byte 3896> lbits:3 n WO SCL frequency power of 2 lbits:4 m WO SCL frequency multiplier lbits:25 reserved0 RES Reserved {} or twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Baud R ate <byte 3896> ulong value As longword endunion twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/ Baud Rate <byte 3900> union twsi_extended_slave_address (Offset 0xC010) Two-Wire Serial Interface Exte nded Slave Address <byte 3900> {field (By field)} <byte 3900> lbits:8 saddr RW Bits[7:0] of the 10-bit slave address lbits:24 reserved0 RES Reserved {} or twsi_extended_slave_address (Offset 0xC010) Two-Wire Serial Interface Extende d Slave Address <byte 3900> ulong value As longword endunion twsi_extended_slave_address (Offset 0xC010) Two-Wire Serial Interface E xtended Slave Address <byte 3904> union twsi_soft_reset (Offset 0xC01C) Two-Wire Serial Interface Soft Reset <byte 3904> {field (By field)} <byte 3904> lbits:32 rst WO Write to this register resets the TWSI logic and sets all TWS I registers to their reset values {}

or twsi_soft_reset (Offset 0xC01C) Two-Wire Serial Interface Soft Reset <byte 3904> ulong value As longword endunion twsi_soft_reset (Offset 0xC01C) Two-Wire Serial Interface Soft Reset {} <byte 3908> {atlantis_mcs (Atlantis machine check specific registers)} <byte 3908> union main_interrupt_cause_low (Offset 0x0004) Main Interrupt Cause (Low) <byte 3908> {field (By field)} <byte 3908> lbits:1 reserved2 R Reserved lbits:1 deverr R/CLL Device Bus Error lbits:1 dmaerr R/CLL DMA Error lbits:1 cpuerr R/CLL CPU Error lbits:1 idma0 R/CLL IDMA Channel0 Completion lbits:1 idma1 R/CLL IDMA Channel1 Completion lbits:1 idma2 R/CLL IDMA Channel2 Completion lbits:1 idma3 R/CLL IDMA Channel3 Completion lbits:1 timer0 R/CLL Timer0 lbits:1 timer1 R/CLL Timer1 lbits:1 timer2 R/CLL Timer2 lbits:1 timer3 R/CLL Timer3 lbits:1 pci0 R/CLL PCI0 lbits:1 sramerr R/CLL SRAM Parity Error lbits:1 gbeerr R/CLL Gb Ethernet Error lbits:1 cerr R/CLL Serial Ports Error lbits:1 pci1 R/CLL PCI1 lbits:1 dramerr R/CLL DRAM ECC Error lbits:1 wdnmi R/CLL WatchDog Reached NMI Threshold lbits:1 wde R/CLL WatchDog Reached Terminal Cnt lbits:1 pci0in R/CLL PCI0 Inbound lbits:1 pci0out R/CLL PCI0 Outbound lbits:1 pci1in R/CLL PCI1 Inbound lbits:1 pci1out R/CLL PCI1 Outbound lbits:1 p1_gpp0_7 R/CLL CPU1 GPP[7:0] Interrupt lbits:1 p1_gpp8_15 R/CLL CPU1 GPP[15:8] Interrupt lbits:1 p1_gpp16_23 R/CLL CPU1 GPP[23:16] Interrupt lbits:1 p1_gpp24_31 R/CLL CPU1 GPP[24:31] Interrupt lbits:1 p1_cpu_db R/CLL CPU1 Doorbell lbits:3 reserved1 R Reserved {} or main_interrupt_cause_low (Offset 0x0004) Main Interrupt Cause (Low) <byte 3908> ulong value As longword endunion main_interrupt_cause_low (Offset 0x0004) Main Interrupt Cause (Low) <byte 3912> union main_interrupt_cause_high (Offset 0x000C) Main Interrupt Cause (High) <byte 3912> {field (By field)} <byte 3912> lbits:1 ge0 R/CLL Gb Ethernet0 lbits:1 ge1 R/CLL Gb Ethernet1 lbits:1 ge2 R/CLL Gb Ethernet2 lbits:1 reserved3 R Reserved lbits:1 sdma0 R/CLL MPSC0 SDMA lbits:1 twsi R/CLL TWSI (I2C) lbits:1 sdma1 R/CLL MPSC1 SDMA lbits:1 brg R/CLL BRG

lbits:1 mpsc0 R/CLL MPSC0 lbits:1 mpsc1 R/CLL MPSC1 lbits:1 g0rx R/CLL Gb Ethernet0 Rx lbits:1 g0tx R/CLL Gb Ethernet0 Tx lbits:1 g0misc R/CLL Gb Ethernet0 Misc lbits:1 g1rx R/CLL Gb Ethernet1 Rx lbits:1 g1tx R/CLL Gb Ethernet1 Tx lbits:1 g1misc R/CLL Gb Ethernet1 Misc lbits:1 g2rx R/CLL Gb Ethernet2 Rx lbits:1 g2tx R/CLL Gb Ethernet2 Tx lbits:1 g2misc R/CLL Gb Ethernet2 Misc lbits:5 reserved2 R Reserved lbits:1 p0_gpp0_7 R/CLL CPU0 GPP[7:0] Interrupt lbits:1 p0_gpp8_15 R/CLL CPU0 GPP[15:8] Interrupt lbits:1 p0_gpp16_23 R/CLL CPU0 GPP[23:16] Interrupt lbits:1 p0_gpp24_31 R/CLL CPU0 GPP[24:31] Interrupt lbits:1 p0_cpu_db R/CLL CPU0 Doorbell lbits:3 reserved1 R Reserved {} or main_interrupt_cause_high (Offset 0x000C) Main Interrupt Cause (High) <byte 3912> ulong value As longword endunion main_interrupt_cause_high (Offset 0x000C) Main Interrupt Cause (High) <byte 3916> union cpuint_0_mask_low (Offset 0x0014) CPUInt[0]# Mask (Low) <byte 3916> {field (By field)} <byte 3916> lbits:1 reserved2 R Reserved lbits:1 deverr R/CLL Device Bus Error lbits:1 dmaerr R/CLL DMA Error lbits:1 cpuerr R/CLL CPU Error lbits:1 idma0 R/CLL IDMA Channel0 Completion lbits:1 idma1 R/CLL IDMA Channel1 Completion lbits:1 idma2 R/CLL IDMA Channel2 Completion lbits:1 idma3 R/CLL IDMA Channel3 Completion lbits:1 timer0 R/CLL Timer0 lbits:1 timer1 R/CLL Timer1 lbits:1 timer2 R/CLL Timer2 lbits:1 timer3 R/CLL Timer3 lbits:1 pci0 R/CLL PCI0 lbits:1 sramerr R/CLL SRAM Parity Error lbits:1 gbeerr R/CLL Gb Ethernet Error lbits:1 cerr R/CLL Serial Ports Error lbits:1 pci1 R/CLL PCI1 lbits:1 dramerr R/CLL DRAM ECC Error lbits:1 wdnmi R/CLL WatchDog Reached NMI Threshold lbits:1 wde R/CLL WatchDog Reached Terminal Cnt lbits:1 pci0in R/CLL PCI0 Inbound lbits:1 pci0out R/CLL PCI0 Outbound lbits:1 pci1in R/CLL PCI1 Inbound lbits:1 pci1out R/CLL PCI1 Outbound lbits:1 p1_gpp0_7 R/CLL CPU1 GPP[7:0] Interrupt lbits:1 p1_gpp8_15 R/CLL CPU1 GPP[15:8] Interrupt lbits:1 p1_gpp16_23 R/CLL CPU1 GPP[23:16] Interrupt lbits:1 p1_gpp24_31 R/CLL CPU1 GPP[24:31] Interrupt lbits:1 p1_cpu_db R/CLL CPU1 Doorbell lbits:3 reserved1 R Reserved {} or cpuint_0_mask_low (Offset 0x0014) CPUInt[0]# Mask (Low)

<byte 3916> ulong value As longword endunion cpuint_0_mask_low (Offset 0x0014) CPUInt[0]# Mask (Low) <byte 3920> union cpuint_0_mask_high (Offset 0x001C) CPUInt[0]# Mask (High) <byte 3920> {field (By field)} <byte 3920> lbits:1 ge0 R/CLL Gb Ethernet0 lbits:1 ge1 R/CLL Gb Ethernet1 lbits:1 ge2 R/CLL Gb Ethernet2 lbits:1 reserved3 R Reserved lbits:1 sdma0 R/CLL MPSC0 SDMA lbits:1 twsi R/CLL TWSI (I2C) lbits:1 sdma1 R/CLL MPSC1 SDMA lbits:1 brg R/CLL BRG lbits:1 mpsc0 R/CLL MPSC0 lbits:1 mpsc1 R/CLL MPSC1 lbits:1 g0rx R/CLL Gb Ethernet0 Rx lbits:1 g0tx R/CLL Gb Ethernet0 Tx lbits:1 g0misc R/CLL Gb Ethernet0 Misc lbits:1 g1rx R/CLL Gb Ethernet1 Rx lbits:1 g1tx R/CLL Gb Ethernet1 Tx lbits:1 g1misc R/CLL Gb Ethernet1 Misc lbits:1 g2rx R/CLL Gb Ethernet2 Rx lbits:1 g2tx R/CLL Gb Ethernet2 Tx lbits:1 g2misc R/CLL Gb Ethernet2 Misc lbits:5 reserved2 R Reserved lbits:1 p0_gpp0_7 R/CLL CPU0 GPP[7:0] Interrupt lbits:1 p0_gpp8_15 R/CLL CPU0 GPP[15:8] Interrupt lbits:1 p0_gpp16_23 R/CLL CPU0 GPP[23:16] Interrupt lbits:1 p0_gpp24_31 R/CLL CPU0 GPP[24:31] Interrupt lbits:1 p0_cpu_db R/CLL CPU0 Doorbell lbits:3 reserved1 R Reserved {} or cpuint_0_mask_high (Offset 0x001C) CPUInt[0]# Mask (High) <byte 3920> ulong value As longword endunion cpuint_0_mask_high (Offset 0x001C) CPUInt[0]# Mask (High) <byte 3924> union cpu_error_address_low (Offset 0x0070) CPU Error Address (Low) <byte 3924> {field (By field)} <byte 3924> lbits:32 erraddr RO Latched address bits [31:0] of a CPU transaction: illegal address (failed address decoding), access protection violation, bad data parity , bad address parity {} or cpu_error_address_low (Offset 0x0070) CPU Error Address (Low) <byte 3924> ulong value As longword endunion cpu_error_address_low (Offset 0x0070) CPU Error Address (Low) <byte 3928> union cpu_error_address_high (Offset 0x0078) CPU Error Address (High) <byte 3928> {field (By field)} <byte 3928> lbits:4 erraddr_h R Error Address bits [35:32] lbits:5 errpar R Address Parity bits lbits:1 hit R 1=HIT# asserted (cached)

lbits:22 reserved R Reserved {} or cpu_error_address_high (Offset 0x0078) CPU Error Address (High) <byte 3928> ulong value As longword endunion cpu_error_address_high (Offset 0x0078) CPU Error Address (High) <byte 3932> union cpu_error_data_low (Offset 0x0128) CPU Error Data (Low) <byte 3932> {field (By field)} <byte 3932> lbits:32 perrdata RO Latched data bits in case of bad data parity sampled on write transactions or on master read transactions on the 60x bus {} or cpu_error_data_low (Offset 0x0128) CPU Error Data (Low) <byte 3932> ulong value As longword endunion cpu_error_data_low (Offset 0x0128) CPU Error Data (Low) <byte 3936> union cpu_error_data_high (Offset 0x0130) CPU Error Data (High) <byte 3936> {field (By field)} <byte 3936> lbits:32 perrdata RO Latched data bits in case of bad data parity sampled on write transactions or on master read transactions on the 60x bus {} or cpu_error_data_high (Offset 0x0130) CPU Error Data (High) <byte 3936> ulong value As longword endunion cpu_error_data_high (Offset 0x0130) CPU Error Data (High) <byte 3940> union cpu_error_parity (Offset 0x0138) CPU Error Parity <byte 3940> {field (By field)} <byte 3940> lbits:8 perrpar RO Latched data parity bus in case of bad data parity sampled on write transactions or on master read transactions on the 60x bus lbits:2 gronk ?? Atlantis spec. error, Table 273--these bits are not defined! !! lbits:22 reserved0 RES Reserved {} or cpu_error_parity (Offset 0x0138) CPU Error Parity <byte 3940> ulong value As longword endunion cpu_error_parity (Offset 0x0138) CPU Error Parity <byte 3944> union cpu_error_cause (Offset 0x0140) CPU Error Cause <byte 3944> {field (By field)} <byte 3944> lbits:1 addrout R/W0C CPU Address Out of Range in Addr, Data, Parity Err Regs lbits:1 addrperr R/W0C Bad Address Parity Detected lbits:1 tterr R/W0C Transfer Type/Init Val Violation lbits:1 accerr R/W0C Access to a Protected Region lbits:1 wrerr R/W0C Write to a Wrt Protectd Region lbits:1 cacheerr R/W0C Cache Rd, Caching Protected lbits:1 wrdataperr R/W0C Bad Write Data Parity Detected lbits:1 rddataperr R/W0C Bad Read Data Parity Detected lbits:19 reserved R Reserved lbits:5 sel R Type of above error captured

{} or cpu_error_cause (Offset 0x0140) CPU Error Cause <byte 3944> ulong value As longword endunion cpu_error_cause (Offset 0x0140) CPU Error Cause <byte 3948> union cpu0_error_mask (Offset 0x0148) CPU0 Error Mask <byte 3948> {field (By field)} <byte 3948> lbits:1 addrout R/W0C CPU Address Out of Range in Addr, Data, Parity Err Regs lbits:1 addrperr R/W0C Bad Address Parity Detected lbits:1 tterr R/W0C Transfer Type/Init Val Violation lbits:1 accerr R/W0C Access to a Protected Region lbits:1 wrerr R/W0C Write to a Wrt Protectd Region lbits:1 cacheerr R/W0C Cache Rd, Caching Protected lbits:1 wrdataperr R/W0C Bad Write Data Parity Detected lbits:1 rddataperr R/W0C Bad Read Data Parity Detected lbits:19 reserved R Reserved lbits:5 sel R Type of above error captured {} or cpu0_error_mask (Offset 0x0148) CPU0 Error Mask <byte 3948> ulong value As longword endunion cpu0_error_mask (Offset 0x0148) CPU0 Error Mask <byte 3952> union sram_configuration (Offset 0x0380) SRAM Configuration <byte 3952> {field (By field)} <byte 3952> lbits:2 ccen R/W Cache Coherency Enable lbits:2 reserved2 R Reserved lbits:1 paren R/W Parity Enable (gen. & check) lbits:1 perrpropen R/W Parity Error Propagate Enable lbits:1 forceparen R/W Force Parity Enable (debug) lbits:1 park R/W Arbiter Park on cross bar lbits:8 forcepar R/W Forced Parity Byte Value lbits:3 rtc R Reserved by Marvell (0x6) lbits:2 wtc R Reserved by Marvell (0x2) lbits:11 reserved1 R Reserved {} or sram_configuration (Offset 0x0380) SRAM Configuration <byte 3952> ulong value As longword endunion sram_configuration (Offset 0x0380) SRAM Configuration <byte 3956> union sram_error_cause (Offset 0x0388) SRAM Error Cause <byte 3956> {field (By field)} <byte 3956> lbits:1 perr0_7 R/W0C Parity Error Byte [7:0] lbits:1 perr8_15 R/W0C Parity Error Byte [15:8] lbits:1 perr16_23 R/W0C Parity Error Byte [23:16] lbits:1 perr24_31 R/W0C Parity Error Byte [31:24] lbits:1 perr32_39 R/W0C Parity Error Byte [39:32] lbits:1 perr40_47 R/W0C Parity Error Byte [47:40] lbits:1 perr48_55 R/W0C Parity Error Byte [55:48] lbits:1 perr56_63 R/W0C Parity Error Byte [63:56] lbits:24 reserved R Reserved {}

or sram_error_cause (Offset 0x0388) SRAM Error Cause <byte 3956> ulong value As longword endunion sram_error_cause (Offset 0x0388) SRAM Error Cause <byte 3960> union sram_error_address (Offset 0x0390) SRAM Error Address <byte 3960> {field (By field)} <byte 3960> lbits:32 addr RW Error Address bits[31:0] {} or sram_error_address (Offset 0x0390) SRAM Error Address <byte 3960> ulong value As longword endunion sram_error_address (Offset 0x0390) SRAM Error Address <byte 3964> union sram_error_data_low (Offset 0x0398) SRAM Error Data (Low) <byte 3964> {field (By field)} <byte 3964> lbits:32 data RW Error data {} or sram_error_data_low (Offset 0x0398) SRAM Error Data (Low) <byte 3964> ulong value As longword endunion sram_error_data_low (Offset 0x0398) SRAM Error Data (Low) <byte 3968> union sram_error_data_high (Offset 0x03A0) SRAM Error Data (High) <byte 3968> {field (By field)} <byte 3968> lbits:32 data RW Error data {} or sram_error_data_high (Offset 0x03A0) SRAM Error Data (High) <byte 3968> ulong value As longword endunion sram_error_data_high (Offset 0x03A0) SRAM Error Data (High) <byte 3972> union sram_error_parity (Offset 0x03A8) SRAM Error Parity <byte 3972> {field (By field)} <byte 3972> lbits:8 par RW Error parity lbits:24 reserved0 RES Reserved {} or sram_error_parity (Offset 0x03A8) SRAM Error Parity <byte 3972> ulong value As longword endunion sram_error_parity (Offset 0x03A8) SRAM Error Parity <byte 3976> union sram_error_address_high (Offset 0x03F8) SRAM Error Address (High) <byte 3976> {field (By field)} <byte 3976> lbits:4 addr RW Error Address bits[35:32] Latched upon SRAM parity error dete ction lbits:28 reserved0 RES Reserved {} or sram_error_address_high (Offset 0x03F8) SRAM Error Address (High) <byte 3976>

ulong value As longword endunion sram_error_address_high (Offset 0x03F8) SRAM Error Address (High) <byte 3980> union device_interrupt_cause (Offset 0x04D0) Device Interrupt Cause <byte 3980> {field (By field)} <byte 3980> lbits:1 dbursterr R/W0C Forced ECC Byte Value in Addr, Data, Parity Err Regs lbits:1 drdyerr R/W0C Write 'forceecc' Enable (debug) lbits:1 perr0 R/W0C Parity Error 0 lbits:1 perr1 R/W0C Parity Error 1 lbits:1 perr2 R/W0C Parity Error 2 lbits:1 perr3 R/W0C Parity Error 3 lbits:21 reserved R Reserved lbits:5 sel R Type of above error captured {} or device_interrupt_cause (Offset 0x04D0) Device Interrupt Cause <byte 3980> ulong value As longword endunion device_interrupt_cause (Offset 0x04D0) Device Interrupt Cause <byte 3984> union device_interrupt_mask (Offset 0x04D4) Device Interrupt Mask <byte 3984> {field (By field)} <byte 3984> lbits:1 dbursterr R/W0C Forced ECC Byte Value in Addr, Data, Parity Err Regs lbits:1 drdyerr R/W0C Write 'forceecc' Enable (debug) lbits:1 perr0 R/W0C Parity Error 0 lbits:1 perr1 R/W0C Parity Error 1 lbits:1 perr2 R/W0C Parity Error 2 lbits:1 perr3 R/W0C Parity Error 3 lbits:21 reserved R Reserved lbits:5 sel R Type of above error captured {} or device_interrupt_mask (Offset 0x04D4) Device Interrupt Mask <byte 3984> ulong value As longword endunion device_interrupt_mask (Offset 0x04D4) Device Interrupt Mask <byte 3988> union device_error_address (Offset 0x04D8) Device Error Address <byte 3988> {field (By field)} <byte 3988> lbits:32 addr RW Latched Address Upon Device Error Condition {} or device_error_address (Offset 0x04D8) Device Error Address <byte 3988> ulong value As longword endunion device_error_address (Offset 0x04D8) Device Error Address <byte 3992> union device_error_data (Offset 0x04DC) Device Error Data <byte 3992> {field (By field)} <byte 3992> lbits:32 data RW Latched data upon parity error detection {} or device_error_data (Offset 0x04DC) Device Error Data <byte 3992> ulong value As longword endunion device_error_data (Offset 0x04DC) Device Error Data

<byte 3996> union device_error_parity (Offset 0x04E0) Device Error Parity <byte 3996> {field (By field)} <byte 3996> lbits:4 par RW Latched parity upon parity error detection lbits:28 reserved0 RES Reserved, read only {} or device_error_parity (Offset 0x04E0) Device Error Parity <byte 3996> ulong value As longword endunion device_error_parity (Offset 0x04E0) Device Error Parity <byte 4000> union idma_interrupt_cause (Offset 0x08C0) IDMA Interrupt Cause <byte 4000> {field (By field)} <byte 4000> lbits:1 dmacmplt0 R/W0C Channel 0 DMA Complete lbits:1 addrmiss0 R/W0C Channel 0 Address Miss, Failed Decode lbits:1 accprot0 R/W0C Channel 0 Access Protect Violation lbits:1 wrprot0 R/W0C Channel 0 Write Protect Violation lbits:1 own0 R/W0C Channel 0 Descriptor Ownership Violation lbits:3 reserved0 R Reserved lbits:1 dmacmplt1 R/W0C Channel 1 DMA Complete lbits:1 addrmiss1 R/W0C Channel 1 Address Miss, Failed Decode lbits:1 accprot1 R/W0C Channel 1 Access Protect Violation lbits:1 wrprot1 R/W0C Channel 1 Write Protect Violation lbits:1 own1 R/W0C Channel 1 Descriptor Ownership Violation lbits:3 reserved1 R Reserved lbits:1 dmacmplt2 R/W0C Channel 2 DMA Complete lbits:1 addrmiss2 R/W0C Channel 2 Address Miss, Failed Decode lbits:1 accprot2 R/W0C Channel 2 Access Protect Violation lbits:1 wrprot2 R/W0C Channel 2 Write Protect Violation lbits:1 own2 R/W0C Channel 2 Descriptor Ownership Violation lbits:3 reserved2 R Reserved lbits:1 dmacmplt3 R/W0C Channel 3 DMA Complete lbits:1 addrmiss3 R/W0C Channel 3 Address Miss, Failed Decode lbits:1 accprot3 R/W0C Channel 3 Access Protect Violation lbits:1 wrprot3 R/W0C Channel 3 Write Protect Violation lbits:1 own3 R/W0C Channel 3 Descriptor Ownership Violation lbits:3 reserved3 R Reserved {} or idma_interrupt_cause (Offset 0x08C0) IDMA Interrupt Cause <byte 4000> ulong value As longword endunion idma_interrupt_cause (Offset 0x08C0) IDMA Interrupt Cause <byte 4004> union idma_interrupt_mask (Offset 0x08C4) IDMA Interrupt Mask <byte 4004> {field (By field)} <byte 4004> lbits:1 dmacmplt0 R/W0C Channel 0 DMA Complete lbits:1 addrmiss0 R/W0C Channel 0 Address Miss, Failed Decode lbits:1 accprot0 R/W0C Channel 0 Access Protect Violation lbits:1 wrprot0 R/W0C Channel 0 Write Protect Violation lbits:1 own0 R/W0C Channel 0 Descriptor Ownership Violation lbits:3 reserved0 R Reserved lbits:1 dmacmplt1 R/W0C Channel 1 DMA Complete lbits:1 addrmiss1 R/W0C Channel 1 Address Miss, Failed Decode lbits:1 accprot1 R/W0C Channel 1 Access Protect Violation

lbits:1 wrprot1 R/W0C Channel 1 Write Protect Violation lbits:1 own1 R/W0C Channel 1 Descriptor Ownership Violation lbits:3 reserved1 R Reserved lbits:1 dmacmplt2 R/W0C Channel 2 DMA Complete lbits:1 addrmiss2 R/W0C Channel 2 Address Miss, Failed Decode lbits:1 accprot2 R/W0C Channel 2 Access Protect Violation lbits:1 wrprot2 R/W0C Channel 2 Write Protect Violation lbits:1 own2 R/W0C Channel 2 Descriptor Ownership Violation lbits:3 reserved2 R Reserved lbits:1 dmacmplt3 R/W0C Channel 3 DMA Complete lbits:1 addrmiss3 R/W0C Channel 3 Address Miss, Failed Decode lbits:1 accprot3 R/W0C Channel 3 Access Protect Violation lbits:1 wrprot3 R/W0C Channel 3 Write Protect Violation lbits:1 own3 R/W0C Channel 3 Descriptor Ownership Violation lbits:3 reserved3 R Reserved {} or idma_interrupt_mask (Offset 0x08C4) IDMA Interrupt Mask <byte 4004> ulong value As longword endunion idma_interrupt_mask (Offset 0x08C4) IDMA Interrupt Mask <byte 4008> union idma_error_address (Offset 0x08C8) IDMA Error Address <byte 4008> {field (By field)} <byte 4008> lbits:32 erraddr RW Bits[31:0] of Error Address {} or idma_error_address (Offset 0x08C8) IDMA Error Address <byte 4008> ulong value As longword endunion idma_error_address (Offset 0x08C8) IDMA Error Address <byte 4012> union sdram_error_data_high (Offset 0x1440) SDRAM Error Data (High) <byte 4012> {field (By field)} <byte 4012> lbits:32 eccdata RW Sampled 32 high bits of the last data with ECC error {} or sdram_error_data_high (Offset 0x1440) SDRAM Error Data (High) <byte 4012> ulong value As longword endunion sdram_error_data_high (Offset 0x1440) SDRAM Error Data (High) <byte 4016> union sdram_error_data_low (Offset 0x1444) SDRAM Error Data (Low) <byte 4016> {field (By field)} <byte 4016> lbits:32 eccdata RW Sampled 32 low bits of the last data with ECC error {} or sdram_error_data_low (Offset 0x1444) SDRAM Error Data (Low) <byte 4016> ulong value As longword endunion sdram_error_data_low (Offset 0x1444) SDRAM Error Data (Low) <byte 4020> union sdram_received_ecc (Offset 0x1448) SDRAM Received ECC <byte 4020> {field (By field)} <byte 4020> lbits:8 eccreg RW ECC code being read from SDRAM lbits:24 reserved0 RES Reserved

{} or sdram_received_ecc (Offset 0x1448) SDRAM Received ECC <byte 4020> ulong value As longword endunion sdram_received_ecc (Offset 0x1448) SDRAM Received ECC <byte 4024> union sdram_calculated_ecc (Offset 0x144C) SDRAM Calculated ECC <byte 4024> {field (By field)} <byte 4024> lbits:8 ecccalc RW ECC code calculated by Dunit lbits:24 reserved0 RES Reserved {} or sdram_calculated_ecc (Offset 0x144C) SDRAM Calculated ECC <byte 4024> ulong value As longword endunion sdram_calculated_ecc (Offset 0x144C) SDRAM Calculated ECC <byte 4028> union sdram_error_address (Offset 0x1450) SDRAM Error Address <byte 4028> {field (By field /* NOTE: WOC just clears the dramerr)} <byte 4028> lbits:1 errtype R/W0C Err Type (0=CDEs>limit, 1=UDE) lbits:2 bank R/W0C DIMM Bank (0-3) lbits:29 eccaddr R/W0C Address of Error [31:3] (NOTE: Atlantis spec. error, Tabl e 303--indicates this field is 30 bits [31:2]; changed to 29 bits [31:3]) {} or sdram_error_address (Offset 0x1450) SDRAM Error Address <byte 4028> ulong value As longword /* bit in the lower cause reg. endunion sdram_error_address (Offset 0x1450) SDRAM Error Address <byte 4032> union sdram_ecc_control (Offset 0x1454) SDRAM ECC Control <byte 4032> {field (By field)} <byte 4032> lbits:8 forceecc R/W Forced ECC Byte Value lbits:1 forceeccen R/W Write 'forceecc' Enable (debug) lbits:1 perrpropen R/W Propagate PERR to ECC mem. Err lbits:6 reserved2 R Reserved lbits:8 threcc R/W Threshold for reporting CDEs lbits:8 reserved1 R Reserved {} or sdram_ecc_control (Offset 0x1454) SDRAM ECC Control <byte 4032> ulong value As longword endunion sdram_ecc_control (Offset 0x1454) SDRAM ECC Control <byte 4036> union sdram_ecc_counter (Offset 0x1458) SDRAM ECC Counter <byte 4036> {field (By field)} <byte 4036> lbits:32 count R Number of single bit ECC errors detected {} or sdram_ecc_counter (Offset 0x1458) SDRAM ECC Counter <byte 4036> ulong value As longword endunion sdram_ecc_counter (Offset 0x1458) SDRAM ECC Counter {} <byte 4040>

{decoder (Decoder)} <byte 4040> {rsvd (03 Reserved)} <byte 4040> utiny value {} <byte 4041> union gpo_c 02 GPO C: Enet Card Reset.. <byte 4041> {field (By field)} <byte 4041> tbits:7 rsvd R Reserved tbits:1 enet_card_rst R/W Ethernet Card Reset {} or gpo_c 02 GPO C: Enet Card Reset.. <byte 4041> utiny value As utiny endunion gpo_c 02 GPO C: Enet Card Reset.. <byte 4042> union gpi 01 GPI B: Module Type.. <byte 4042> {field (By field)} <byte 4042> tbits:4 mod_type R Module Type tbits:3 rsvd R Reserved tbits:1 enet_gpi R/W Ethernet Card GPI {} or gpi 01 GPI B: Module Type.. <byte 4042> utiny value As utiny endunion gpi 01 GPI B: Module Type.. <byte 4043> union mod_rev 00 GPI A: Module Revision <byte 4043> {field (By field)} <byte 4043> tbits:3 rev R Revision tbits:5 eco_level R ECO Level {} or mod_rev 00 GPI A: Module Revision <byte 4043> utiny value As utiny endunion mod_rev 00 GPI A: Module Revision <byte 4044> {rsvd1[1] (06-FC Reserved)} <byte 4044> utiny value {} <byte 4045> {rsvd1[0] (06-FC Reserved)} <byte 4045> utiny value {} <byte 4046> union gpo_bstat1 05 GPO E: Boot Status LEDs.. <byte 4046> {field (By field)} <byte 4046> tbits:1 led8 R/W Boot Status LED 8 tbits:1 led9 R/W Boot Status LED 9

tbits:6 rsvd R Reserved {} or gpo_bstat1 05 GPO E: Boot Status LEDs.. <byte 4046> utiny value As utiny endunion gpo_bstat1 05 GPO E: Boot Status LEDs.. <byte 4047> union bstat0 04 GPO D: Boot Status LEDs <byte 4047> {field (By field)} <byte 4047> tbits:1 led0 R/W Boot Status LED 8 tbits:1 led1 R/W Boot Status LED 9 tbits:1 led2 R/W Boot Status LED 9 tbits:1 led3 R/W Boot Status LED 9 tbits:1 led4 R/W Boot Status LED 9 tbits:1 led5 R/W Boot Status LED 9 tbits:1 led6 R/W Boot Status LED 9 tbits:1 led7 R/W Boot Status LED 9 {} or bstat0 04 GPO D: Boot Status LEDs <byte 4047> utiny value As utiny endunion bstat0 04 GPO D: Boot Status LEDs <byte 4048> {rsvd1[5] (06-FC Reserved)} <byte 4048> utiny value {} <byte 4049> {rsvd1[4] (06-FC Reserved)} <byte 4049> utiny value {} <byte 4050> {rsvd1[3] (06-FC Reserved)} <byte 4050> utiny value {} <byte 4051> {rsvd1[2] (06-FC Reserved)} <byte 4051> utiny value {} <byte 4052> {rsvd1[9] (06-FC Reserved)} <byte 4052> utiny value {} <byte 4053> {rsvd1[8] (06-FC Reserved)} <byte 4053> utiny value {} <byte 4054> {rsvd1[7] (06-FC Reserved)} <byte 4054> utiny value {} <byte 4055>

{rsvd1[6] (06-FC Reserved)} <byte 4055> utiny value {} <byte 4056> {rsvd1[13] (06-FC Reserved)} <byte 4056> utiny value {} <byte 4057> {rsvd1[12] (06-FC Reserved)} <byte 4057> utiny value {} <byte 4058> {rsvd1[11] (06-FC Reserved)} <byte 4058> utiny value {} <byte 4059> {rsvd1[10] (06-FC Reserved)} <byte 4059> utiny value {} <byte 4060> {rsvd1[17] (06-FC Reserved)} <byte 4060> utiny value {} <byte 4061> {rsvd1[16] (06-FC Reserved)} <byte 4061> utiny value {} <byte 4062> {rsvd1[15] (06-FC Reserved)} <byte 4062> utiny value {} <byte 4063> {rsvd1[14] (06-FC Reserved)} <byte 4063> utiny value {} <byte 4064> {rsvd1[21] (06-FC Reserved)} <byte 4064> utiny value {} <byte 4065> {rsvd1[20] (06-FC Reserved)} <byte 4065> utiny value {} <byte 4066> {rsvd1[19] (06-FC Reserved)} <byte 4066> utiny value {} <byte 4067>

{rsvd1[18] (06-FC <byte 4067> utiny value {} <byte 4068> {rsvd1[25] (06-FC <byte 4068> utiny value {} <byte 4069> {rsvd1[24] (06-FC <byte 4069> utiny value {} <byte 4070> {rsvd1[23] (06-FC <byte 4070> utiny value {} <byte 4071> {rsvd1[22] (06-FC <byte 4071> utiny value {} <byte 4072> {rsvd1[29] (06-FC <byte 4072> utiny value {} <byte 4073> {rsvd1[28] (06-FC <byte 4073> utiny value {} <byte 4074> {rsvd1[27] (06-FC <byte 4074> utiny value {} <byte 4075> {rsvd1[26] (06-FC <byte 4075> utiny value {} <byte 4076> {rsvd1[33] (06-FC <byte 4076> utiny value {} <byte 4077> {rsvd1[32] (06-FC <byte 4077> utiny value {} <byte 4078> {rsvd1[31] (06-FC <byte 4078> utiny value {} <byte 4079>

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

{rsvd1[30] (06-FC <byte 4079> utiny value {} <byte 4080> {rsvd1[37] (06-FC <byte 4080> utiny value {} <byte 4081> {rsvd1[36] (06-FC <byte 4081> utiny value {} <byte 4082> {rsvd1[35] (06-FC <byte 4082> utiny value {} <byte 4083> {rsvd1[34] (06-FC <byte 4083> utiny value {} <byte 4084> {rsvd1[41] (06-FC <byte 4084> utiny value {} <byte 4085> {rsvd1[40] (06-FC <byte 4085> utiny value {} <byte 4086> {rsvd1[39] (06-FC <byte 4086> utiny value {} <byte 4087> {rsvd1[38] (06-FC <byte 4087> utiny value {} <byte 4088> {rsvd1[45] (06-FC <byte 4088> utiny value {} <byte 4089> {rsvd1[44] (06-FC <byte 4089> utiny value {} <byte 4090> {rsvd1[43] (06-FC <byte 4090> utiny value {} <byte 4091>

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

{rsvd1[42] (06-FC <byte 4091> utiny value {} <byte 4092> {rsvd1[49] (06-FC <byte 4092> utiny value {} <byte 4093> {rsvd1[48] (06-FC <byte 4093> utiny value {} <byte 4094> {rsvd1[47] (06-FC <byte 4094> utiny value {} <byte 4095> {rsvd1[46] (06-FC <byte 4095> utiny value {} <byte 4096> {rsvd1[53] (06-FC <byte 4096> utiny value {} <byte 4097> {rsvd1[52] (06-FC <byte 4097> utiny value {} <byte 4098> {rsvd1[51] (06-FC <byte 4098> utiny value {} <byte 4099> {rsvd1[50] (06-FC <byte 4099> utiny value {} <byte 4100> {rsvd1[57] (06-FC <byte 4100> utiny value {} <byte 4101> {rsvd1[56] (06-FC <byte 4101> utiny value {} <byte 4102> {rsvd1[55] (06-FC <byte 4102> utiny value {} <byte 4103>

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

{rsvd1[54] (06-FC <byte 4103> utiny value {} <byte 4104> {rsvd1[61] (06-FC <byte 4104> utiny value {} <byte 4105> {rsvd1[60] (06-FC <byte 4105> utiny value {} <byte 4106> {rsvd1[59] (06-FC <byte 4106> utiny value {} <byte 4107> {rsvd1[58] (06-FC <byte 4107> utiny value {} <byte 4108> {rsvd1[65] (06-FC <byte 4108> utiny value {} <byte 4109> {rsvd1[64] (06-FC <byte 4109> utiny value {} <byte 4110> {rsvd1[63] (06-FC <byte 4110> utiny value {} <byte 4111> {rsvd1[62] (06-FC <byte 4111> utiny value {} <byte 4112> {rsvd1[69] (06-FC <byte 4112> utiny value {} <byte 4113> {rsvd1[68] (06-FC <byte 4113> utiny value {} <byte 4114> {rsvd1[67] (06-FC <byte 4114> utiny value {} <byte 4115>

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

{rsvd1[66] (06-FC <byte 4115> utiny value {} <byte 4116> {rsvd1[73] (06-FC <byte 4116> utiny value {} <byte 4117> {rsvd1[72] (06-FC <byte 4117> utiny value {} <byte 4118> {rsvd1[71] (06-FC <byte 4118> utiny value {} <byte 4119> {rsvd1[70] (06-FC <byte 4119> utiny value {} <byte 4120> {rsvd1[77] (06-FC <byte 4120> utiny value {} <byte 4121> {rsvd1[76] (06-FC <byte 4121> utiny value {} <byte 4122> {rsvd1[75] (06-FC <byte 4122> utiny value {} <byte 4123> {rsvd1[74] (06-FC <byte 4123> utiny value {} <byte 4124> {rsvd1[81] (06-FC <byte 4124> utiny value {} <byte 4125> {rsvd1[80] (06-FC <byte 4125> utiny value {} <byte 4126> {rsvd1[79] (06-FC <byte 4126> utiny value {} <byte 4127>

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

{rsvd1[78] (06-FC <byte 4127> utiny value {} <byte 4128> {rsvd1[85] (06-FC <byte 4128> utiny value {} <byte 4129> {rsvd1[84] (06-FC <byte 4129> utiny value {} <byte 4130> {rsvd1[83] (06-FC <byte 4130> utiny value {} <byte 4131> {rsvd1[82] (06-FC <byte 4131> utiny value {} <byte 4132> {rsvd1[89] (06-FC <byte 4132> utiny value {} <byte 4133> {rsvd1[88] (06-FC <byte 4133> utiny value {} <byte 4134> {rsvd1[87] (06-FC <byte 4134> utiny value {} <byte 4135> {rsvd1[86] (06-FC <byte 4135> utiny value {} <byte 4136> {rsvd1[93] (06-FC <byte 4136> utiny value {} <byte 4137> {rsvd1[92] (06-FC <byte 4137> utiny value {} <byte 4138> {rsvd1[91] (06-FC <byte 4138> utiny value {} <byte 4139>

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

{rsvd1[90] (06-FC Reserved)} <byte 4139> utiny value {} <byte 4140> {rsvd1[97] (06-FC Reserved)} <byte 4140> utiny value {} <byte 4141> {rsvd1[96] (06-FC Reserved)} <byte 4141> utiny value {} <byte 4142> {rsvd1[95] (06-FC Reserved)} <byte 4142> utiny value {} <byte 4143> {rsvd1[94] (06-FC Reserved)} <byte 4143> utiny value {} <byte 4144> {rsvd1[101] (06-FC Reserved)} <byte 4144> utiny value {} <byte 4145> {rsvd1[100] (06-FC Reserved)} <byte 4145> utiny value {} <byte 4146> {rsvd1[99] (06-FC Reserved)} <byte 4146> utiny value {} <byte 4147> {rsvd1[98] (06-FC Reserved)} <byte 4147> utiny value {} <byte 4148> {rsvd1[105] (06-FC Reserved)} <byte 4148> utiny value {} <byte 4149> {rsvd1[104] (06-FC Reserved)} <byte 4149> utiny value {} <byte 4150> {rsvd1[103] (06-FC Reserved)} <byte 4150> utiny value {} <byte 4151>

{rsvd1[102] <byte 4151> utiny value {} <byte 4152> {rsvd1[109] <byte 4152> utiny value {} <byte 4153> {rsvd1[108] <byte 4153> utiny value {} <byte 4154> {rsvd1[107] <byte 4154> utiny value {} <byte 4155> {rsvd1[106] <byte 4155> utiny value {} <byte 4156> {rsvd1[113] <byte 4156> utiny value {} <byte 4157> {rsvd1[112] <byte 4157> utiny value {} <byte 4158> {rsvd1[111] <byte 4158> utiny value {} <byte 4159> {rsvd1[110] <byte 4159> utiny value {} <byte 4160> {rsvd1[117] <byte 4160> utiny value {} <byte 4161> {rsvd1[116] <byte 4161> utiny value {} <byte 4162> {rsvd1[115] <byte 4162> utiny value {} <byte 4163>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[114] <byte 4163> utiny value {} <byte 4164> {rsvd1[121] <byte 4164> utiny value {} <byte 4165> {rsvd1[120] <byte 4165> utiny value {} <byte 4166> {rsvd1[119] <byte 4166> utiny value {} <byte 4167> {rsvd1[118] <byte 4167> utiny value {} <byte 4168> {rsvd1[125] <byte 4168> utiny value {} <byte 4169> {rsvd1[124] <byte 4169> utiny value {} <byte 4170> {rsvd1[123] <byte 4170> utiny value {} <byte 4171> {rsvd1[122] <byte 4171> utiny value {} <byte 4172> {rsvd1[129] <byte 4172> utiny value {} <byte 4173> {rsvd1[128] <byte 4173> utiny value {} <byte 4174> {rsvd1[127] <byte 4174> utiny value {} <byte 4175>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[126] <byte 4175> utiny value {} <byte 4176> {rsvd1[133] <byte 4176> utiny value {} <byte 4177> {rsvd1[132] <byte 4177> utiny value {} <byte 4178> {rsvd1[131] <byte 4178> utiny value {} <byte 4179> {rsvd1[130] <byte 4179> utiny value {} <byte 4180> {rsvd1[137] <byte 4180> utiny value {} <byte 4181> {rsvd1[136] <byte 4181> utiny value {} <byte 4182> {rsvd1[135] <byte 4182> utiny value {} <byte 4183> {rsvd1[134] <byte 4183> utiny value {} <byte 4184> {rsvd1[141] <byte 4184> utiny value {} <byte 4185> {rsvd1[140] <byte 4185> utiny value {} <byte 4186> {rsvd1[139] <byte 4186> utiny value {} <byte 4187>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[138] <byte 4187> utiny value {} <byte 4188> {rsvd1[145] <byte 4188> utiny value {} <byte 4189> {rsvd1[144] <byte 4189> utiny value {} <byte 4190> {rsvd1[143] <byte 4190> utiny value {} <byte 4191> {rsvd1[142] <byte 4191> utiny value {} <byte 4192> {rsvd1[149] <byte 4192> utiny value {} <byte 4193> {rsvd1[148] <byte 4193> utiny value {} <byte 4194> {rsvd1[147] <byte 4194> utiny value {} <byte 4195> {rsvd1[146] <byte 4195> utiny value {} <byte 4196> {rsvd1[153] <byte 4196> utiny value {} <byte 4197> {rsvd1[152] <byte 4197> utiny value {} <byte 4198> {rsvd1[151] <byte 4198> utiny value {} <byte 4199>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[150] <byte 4199> utiny value {} <byte 4200> {rsvd1[157] <byte 4200> utiny value {} <byte 4201> {rsvd1[156] <byte 4201> utiny value {} <byte 4202> {rsvd1[155] <byte 4202> utiny value {} <byte 4203> {rsvd1[154] <byte 4203> utiny value {} <byte 4204> {rsvd1[161] <byte 4204> utiny value {} <byte 4205> {rsvd1[160] <byte 4205> utiny value {} <byte 4206> {rsvd1[159] <byte 4206> utiny value {} <byte 4207> {rsvd1[158] <byte 4207> utiny value {} <byte 4208> {rsvd1[165] <byte 4208> utiny value {} <byte 4209> {rsvd1[164] <byte 4209> utiny value {} <byte 4210> {rsvd1[163] <byte 4210> utiny value {} <byte 4211>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[162] <byte 4211> utiny value {} <byte 4212> {rsvd1[169] <byte 4212> utiny value {} <byte 4213> {rsvd1[168] <byte 4213> utiny value {} <byte 4214> {rsvd1[167] <byte 4214> utiny value {} <byte 4215> {rsvd1[166] <byte 4215> utiny value {} <byte 4216> {rsvd1[173] <byte 4216> utiny value {} <byte 4217> {rsvd1[172] <byte 4217> utiny value {} <byte 4218> {rsvd1[171] <byte 4218> utiny value {} <byte 4219> {rsvd1[170] <byte 4219> utiny value {} <byte 4220> {rsvd1[177] <byte 4220> utiny value {} <byte 4221> {rsvd1[176] <byte 4221> utiny value {} <byte 4222> {rsvd1[175] <byte 4222> utiny value {} <byte 4223>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[174] <byte 4223> utiny value {} <byte 4224> {rsvd1[181] <byte 4224> utiny value {} <byte 4225> {rsvd1[180] <byte 4225> utiny value {} <byte 4226> {rsvd1[179] <byte 4226> utiny value {} <byte 4227> {rsvd1[178] <byte 4227> utiny value {} <byte 4228> {rsvd1[185] <byte 4228> utiny value {} <byte 4229> {rsvd1[184] <byte 4229> utiny value {} <byte 4230> {rsvd1[183] <byte 4230> utiny value {} <byte 4231> {rsvd1[182] <byte 4231> utiny value {} <byte 4232> {rsvd1[189] <byte 4232> utiny value {} <byte 4233> {rsvd1[188] <byte 4233> utiny value {} <byte 4234> {rsvd1[187] <byte 4234> utiny value {} <byte 4235>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[186] <byte 4235> utiny value {} <byte 4236> {rsvd1[193] <byte 4236> utiny value {} <byte 4237> {rsvd1[192] <byte 4237> utiny value {} <byte 4238> {rsvd1[191] <byte 4238> utiny value {} <byte 4239> {rsvd1[190] <byte 4239> utiny value {} <byte 4240> {rsvd1[197] <byte 4240> utiny value {} <byte 4241> {rsvd1[196] <byte 4241> utiny value {} <byte 4242> {rsvd1[195] <byte 4242> utiny value {} <byte 4243> {rsvd1[194] <byte 4243> utiny value {} <byte 4244> {rsvd1[201] <byte 4244> utiny value {} <byte 4245> {rsvd1[200] <byte 4245> utiny value {} <byte 4246> {rsvd1[199] <byte 4246> utiny value {} <byte 4247>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[198] <byte 4247> utiny value {} <byte 4248> {rsvd1[205] <byte 4248> utiny value {} <byte 4249> {rsvd1[204] <byte 4249> utiny value {} <byte 4250> {rsvd1[203] <byte 4250> utiny value {} <byte 4251> {rsvd1[202] <byte 4251> utiny value {} <byte 4252> {rsvd1[209] <byte 4252> utiny value {} <byte 4253> {rsvd1[208] <byte 4253> utiny value {} <byte 4254> {rsvd1[207] <byte 4254> utiny value {} <byte 4255> {rsvd1[206] <byte 4255> utiny value {} <byte 4256> {rsvd1[213] <byte 4256> utiny value {} <byte 4257> {rsvd1[212] <byte 4257> utiny value {} <byte 4258> {rsvd1[211] <byte 4258> utiny value {} <byte 4259>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[210] <byte 4259> utiny value {} <byte 4260> {rsvd1[217] <byte 4260> utiny value {} <byte 4261> {rsvd1[216] <byte 4261> utiny value {} <byte 4262> {rsvd1[215] <byte 4262> utiny value {} <byte 4263> {rsvd1[214] <byte 4263> utiny value {} <byte 4264> {rsvd1[221] <byte 4264> utiny value {} <byte 4265> {rsvd1[220] <byte 4265> utiny value {} <byte 4266> {rsvd1[219] <byte 4266> utiny value {} <byte 4267> {rsvd1[218] <byte 4267> utiny value {} <byte 4268> {rsvd1[225] <byte 4268> utiny value {} <byte 4269> {rsvd1[224] <byte 4269> utiny value {} <byte 4270> {rsvd1[223] <byte 4270> utiny value {} <byte 4271>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[222] <byte 4271> utiny value {} <byte 4272> {rsvd1[229] <byte 4272> utiny value {} <byte 4273> {rsvd1[228] <byte 4273> utiny value {} <byte 4274> {rsvd1[227] <byte 4274> utiny value {} <byte 4275> {rsvd1[226] <byte 4275> utiny value {} <byte 4276> {rsvd1[233] <byte 4276> utiny value {} <byte 4277> {rsvd1[232] <byte 4277> utiny value {} <byte 4278> {rsvd1[231] <byte 4278> utiny value {} <byte 4279> {rsvd1[230] <byte 4279> utiny value {} <byte 4280> {rsvd1[237] <byte 4280> utiny value {} <byte 4281> {rsvd1[236] <byte 4281> utiny value {} <byte 4282> {rsvd1[235] <byte 4282> utiny value {} <byte 4283>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[234] (06-FC Reserved)} <byte 4283> utiny value {} <byte 4284> {rsvd1[241] (06-FC Reserved)} <byte 4284> utiny value {} <byte 4285> {rsvd1[240] (06-FC Reserved)} <byte 4285> utiny value {} <byte 4286> {rsvd1[239] (06-FC Reserved)} <byte 4286> utiny value {} <byte 4287> {rsvd1[238] (06-FC Reserved)} <byte 4287> utiny value {} <byte 4288> {rsvd1[245] (06-FC Reserved)} <byte 4288> utiny value {} <byte 4289> {rsvd1[244] (06-FC Reserved)} <byte 4289> utiny value {} <byte 4290> {rsvd1[243] (06-FC Reserved)} <byte 4290> utiny value {} <byte 4291> {rsvd1[242] (06-FC Reserved)} <byte 4291> utiny value {} <byte 4292> {decoder_major_rev (FF Decoder Major Revision)} <byte 4292> utiny value {} <byte 4293> {decoder_minor_rev (FE Decoder Minor Revision)} <byte 4293> utiny value {} <byte 4294> {scratch (FD Scratch Register)} <byte 4294> utiny value {} <byte 4295>

{rsvd1[246] (06-FC Reserved)} <byte 4295> utiny value {} {} <byte 4296> {toyclock (DS1557 4MEG NV Y2KC Timekeeping RAM)} <byte 4296> union alarm_minutes Alarm Minutes Union <byte 4296> utiny value Alarm Minutes as byte or alarm_minutes Alarm Minutes Union <byte 4296> {bits (Alarm Minutes by field)} <byte 4296> tbits:4 minutes tbits:3 ten_minutes tbits:1 am2 {} endunion alarm_minutes Alarm Minutes Union <byte 4297> union alarm_seconds Alarm Seconds Union <byte 4297> utiny value Alarm Seconds as byte or alarm_seconds Alarm Seconds Union <byte 4297> {bits (Alarm Seconds by field)} <byte 4297> tbits:4 seconds tbits:3 ten_seconds tbits:1 am1 {} endunion alarm_seconds Alarm Seconds Union <byte 4298> utiny unused <byte 4299> union flag Alarm Enable/Status and Battery Status Flags Union <byte 4299> utiny value Alarm Enable/Status and Battery Status Flags as byte or flag Alarm Enable/Status and Battery Status Flags Union <byte 4299> {bits (Alarm Enable/Status and Battery Status Flags by field)} <byte 4299> tbits:4 unused2 tbits:1 bat_low tbits:1 unused1 tbits:1 alarm tbits:1 alarm_enable {} endunion flag Alarm Enable/Status and Battery Status Flags Union <byte 4300> union watchdog Watchdog Timer Control Flags Union <byte 4300> utiny value Watchdog Timer Control Flags as byte or watchdog Watchdog Timer Control Flags Union <byte 4300> {bits (Watchdog Timer Control Flags by field)} <byte 4300> tbits:7 multiplier tbits:1 steering_bit

{} endunion watchdog Watchdog Timer Control Flags Union <byte 4301> union interrupts Alarm Interrupt Enables Union <byte 4301> utiny value Alarm Interrupt Enables as byte or interrupts Alarm Interrupt Enables Union <byte 4301> {bits (Alarm Interrupt Enables by field)} <byte 4301> tbits:5 unused2 tbits:1 alarm_enable_in_bat tbits:1 unused1 tbits:1 alarm_enable {} endunion interrupts Alarm Interrupt Enables Union <byte 4302> union alarm_date Alarm Date Union <byte 4302> utiny value Alarm Date as byte or alarm_date Alarm Date Union <byte 4302> {bits (Alarm Date by field)} <byte 4302> tbits:4 date tbits:2 ten_date tbits:1 unused tbits:1 am4 {} endunion alarm_date Alarm Date Union <byte 4303> union alarm_hours Alarm Hours Union <byte 4303> utiny value Alarm Hours as byte or alarm_hours Alarm Hours Union <byte 4303> {alarm_hours (Alarm Hours by field)} <byte 4303> tbits:4 hours tbits:2 ten_hours tbits:1 unused tbits:1 am3 {} endunion alarm_hours Alarm Hours Union <byte 4304> union hour Hour Union <byte 4304> utiny value Hour as byte or hour Hour Union <byte 4304> {bits (Hour by field)} <byte 4304> tbits:6 hour tbits:2 unused {} endunion hour Hour Union <byte 4305> union minutes Minutes Union <byte 4305> utiny value Minutes as byte

or minutes Minutes Union <byte 4305> {bits (Minutes by field)} <byte 4305> tbits:7 minutes tbits:1 unused {} endunion minutes Minutes Union <byte 4306> union seconds Seconds/Oscillator Control Union <byte 4306> utiny value Seconds/Oscillator Control as byte or seconds Seconds/Oscillator Control Union <byte 4306> {bits (Seconds/Oscillator Control by field)} <byte 4306> tbits:7 seconds tbits:1 osc {} endunion seconds Seconds/Oscillator Control Union <byte 4307> union control TOY Control Flags/Century Union <byte 4307> utiny value TOY Control Flags/Century as byte or control TOY Control Flags/Century Union <byte 4307> {bits (TOY Control Flags/Century by field)} <byte 4307> tbits:6 century tbits:1 read_bit tbits:1 write_bit {} endunion control TOY Control Flags/Century Union <byte 4308> utiny year Year as byte <byte 4309> union month Month Union <byte 4309> utiny value Month as byte or month Month Union <byte 4309> {bits (Month by field)} <byte 4309> tbits:5 month tbits:3 unused {} endunion month Month Union <byte 4310> union date Date Union <byte 4310> utiny value Date as byte or date Date Union <byte 4310> {bits (Date by field)} <byte 4310> tbits:6 date tbits:2 unused {} endunion date Date Union <byte 4311>

union day Day Union <byte 4311> utiny value Day/Frequency Test as byte or day Day Union <byte 4311> {bits (Day/Frequency Test by field)} <byte 4311> tbits:3 day tbits:3 unused2 tbits:1 freq_test tbits:1 unused1 {} endunion day Day Union {} <byte 4312> {glue (Glue register save area)} <byte 4312> union csr Glue CSR Registers <byte 4312> ulong[256] csra Glue CSR Registers As Longwords or csr Glue CSR Registers <byte 4312> {csrfield (Glue CSR Registers By Field)} <byte 4312> {rsvd[0] (03-0F Reserved)} <byte 4312> utiny value {} <byte 4313> {self_reset (02 Self Reset (0xD1))} <byte 4313> utiny value {} <byte 4314> union reset_in 01 Reset Inputs <byte 4314> {field (By field)} <byte 4314> tbits:1 button_self R/W Button or Self Reset (Reset = 0) tbits:1 crc_reset R/W Sprite CRC Reset (Reset = 0) tbits:1 rsvd1 R Reserved tbits:1 pwr_up R/W Power Up Reset (Reset = 0) tbits:1 swd R/W SW Watchdog Reset (Reset = 0) tbits:3 rsvd R Reserved {} or reset_in 01 Reset Inputs <byte 4314> utiny value As utiny endunion reset_in 01 Reset Inputs <byte 4315> union reset_dis 00 Reset Disables <byte 4315> {field (By field)} <byte 4315> tbits:1 button_self R/W Button or Self Reset (Reset = 0) tbits:1 crc_reset R/W Sprite CRC Reset (Reset = 0) tbits:1 rsvd1 R Reserved tbits:1 pwr_up R/W Power Up Reset (Reset = 0) tbits:1 swd R/W SW Watchdog Reset (Reset = 0) tbits:3 rsvd R Reserved

{} or reset_dis 00 Reset Disables <byte 4315> utiny value As utiny endunion reset_dis 00 Reset Disables <byte 4316> {rsvd[4] (03-0F Reserved)} <byte 4316> utiny value {} <byte 4317> {rsvd[3] (03-0F Reserved)} <byte 4317> utiny value {} <byte 4318> {rsvd[2] (03-0F Reserved)} <byte 4318> utiny value {} <byte 4319> {rsvd[1] (03-0F Reserved)} <byte 4319> utiny value {} <byte 4320> {rsvd[8] (03-0F Reserved)} <byte 4320> utiny value {} <byte 4321> {rsvd[7] (03-0F Reserved)} <byte 4321> utiny value {} <byte 4322> {rsvd[6] (03-0F Reserved)} <byte 4322> utiny value {} <byte 4323> {rsvd[5] (03-0F Reserved)} <byte 4323> utiny value {} <byte 4324> {rsvd[12] (03-0F Reserved)} <byte 4324> utiny value {} <byte 4325> {rsvd[11] (03-0F Reserved)} <byte 4325> utiny value {} <byte 4326> {rsvd[10] (03-0F Reserved)} <byte 4326> utiny value {}

<byte 4327> {rsvd[9] (03-0F Reserved)} <byte 4327> utiny value {} <byte 4328> {rsvd1[0] (13-21 Reserved)} <byte 4328> utiny value {} <byte 4329> union req 12 Request <byte 4329> {field (By field)} <byte 4329> tbits:1 devA R/W PCIX0, Device A Req/Gnt Signal tbits:1 devB R/W PCIX0, Device B Req/Gnt Signal tbits:1 sprite0 R/W PCIX0, Sprite Req/Gnt Signal tbits:1 devE R/W PCIX0, Device E Req/Gnt Signal tbits:1 devC R/W PCIX1, Device C Req/Gnt Signal tbits:1 devD R/W PCIX1, Device D Req/Gnt Signal tbits:1 sprite1 R/W PCIX1, Sprite Req/Gnt Signal tbits:1 rsvd R Reserved {} or req 12 Request <byte 4329> utiny value As utiny endunion req 12 Request <byte 4330> union gnt 11 Grant <byte 4330> {field (By field)} <byte 4330> tbits:1 devA R/W PCIX0, Device A Req/Gnt Signal tbits:1 devB R/W PCIX0, Device B Req/Gnt Signal tbits:1 sprite0 R/W PCIX0, Sprite Req/Gnt Signal tbits:1 devE R/W PCIX0, Device E Req/Gnt Signal tbits:1 devC R/W PCIX1, Device C Req/Gnt Signal tbits:1 devD R/W PCIX1, Device D Req/Gnt Signal tbits:1 sprite1 R/W PCIX1, Sprite Req/Gnt Signal tbits:1 rsvd R Reserved {} or gnt 11 Grant <byte 4330> utiny value As utiny endunion gnt 11 Grant <byte 4331> union arb 10 Arbitration Control & Status <byte 4331> {field (By field)} <byte 4331> tbits:2 ctrl0 R/W PCIX0 Arb Control tbits:2 state0 R PCIX0 Arb State tbits:2 ctrl1 R/W PCIX1 Arb Control tbits:2 state1 R PCIX1 Arb State {} or arb 10 Arbitration Control & Status <byte 4331> utiny value As utiny endunion arb 10 Arbitration Control & Status

<byte 4332> {rsvd1[4] (13-21 Reserved)} <byte 4332> utiny value {} <byte 4333> {rsvd1[3] (13-21 Reserved)} <byte 4333> utiny value {} <byte 4334> {rsvd1[2] (13-21 Reserved)} <byte 4334> utiny value {} <byte 4335> {rsvd1[1] (13-21 Reserved)} <byte 4335> utiny value {} <byte 4336> {rsvd1[8] (13-21 Reserved)} <byte 4336> utiny value {} <byte 4337> {rsvd1[7] (13-21 Reserved)} <byte 4337> utiny value {} <byte 4338> {rsvd1[6] (13-21 Reserved)} <byte 4338> utiny value {} <byte 4339> {rsvd1[5] (13-21 Reserved)} <byte 4339> utiny value {} <byte 4340> {rsvd1[12] (13-21 Reserved)} <byte 4340> utiny value {} <byte 4341> {rsvd1[11] (13-21 Reserved)} <byte 4341> utiny value {} <byte 4342> {rsvd1[10] (13-21 Reserved)} <byte 4342> utiny value {} <byte 4343> {rsvd1[9] (13-21 Reserved)} <byte 4343> utiny value {}

<byte 4344> {swd_tp (23 SW Watchdog Timer Trip Pt.)} <byte 4344> utiny value {} <byte 4345> {swd_ct (22 SW Watchdog Current Time)} <byte 4345> utiny value {} <byte 4346> {rsvd1[14] (13-21 Reserved)} <byte 4346> utiny value {} <byte 4347> {rsvd1[13] (13-21 Reserved)} <byte 4347> utiny value {} <byte 4348> {rsvd2[0] (27-3F Reserved)} <byte 4348> utiny value {} <byte 4349> union timer_ctrl 26 Timer Control <byte 4349> {field (By field)} <byte 4349> tbits:1 mbd_ok R/W Driven Lo when Watchdog Expires tbits:1 rsvd1 R Reserved tbits:1 ena_swd R/W SW Watchdog Timer Enable tbits:1 ena_ppc R/W PPC Bus Snoop Timer Enable tbits:3 rsvd R Reserved tbits:1 swd_rst R/W1R SW Watchdog Reset/Restart {} or timer_ctrl 26 Timer Control <byte 4349> utiny value As utiny endunion timer_ctrl 26 Timer Control <byte 4350> {ppc_sv (25 PPC ' ' Timer Start Value)} <byte 4350> utiny value {} <byte 4351> {ppc_ct (24 PPC Bus Snoop Current Value)} <byte 4351> utiny value {} <byte 4352> {rsvd2[4] (27-3F Reserved)} <byte 4352> utiny value {} <byte 4353> {rsvd2[3] (27-3F Reserved)} <byte 4353> utiny value

{} <byte 4354> {rsvd2[2] (27-3F Reserved)} <byte 4354> utiny value {} <byte 4355> {rsvd2[1] (27-3F Reserved)} <byte 4355> utiny value {} <byte 4356> {rsvd2[8] (27-3F Reserved)} <byte 4356> utiny value {} <byte 4357> {rsvd2[7] (27-3F Reserved)} <byte 4357> utiny value {} <byte 4358> {rsvd2[6] (27-3F Reserved)} <byte 4358> utiny value {} <byte 4359> {rsvd2[5] (27-3F Reserved)} <byte 4359> utiny value {} <byte 4360> {rsvd2[12] (27-3F Reserved)} <byte 4360> utiny value {} <byte 4361> {rsvd2[11] (27-3F Reserved)} <byte 4361> utiny value {} <byte 4362> {rsvd2[10] (27-3F Reserved)} <byte 4362> utiny value {} <byte 4363> {rsvd2[9] (27-3F Reserved)} <byte 4363> utiny value {} <byte 4364> {rsvd2[16] (27-3F Reserved)} <byte 4364> utiny value {} <byte 4365> {rsvd2[15] (27-3F Reserved)} <byte 4365> utiny value

{} <byte 4366> {rsvd2[14] (27-3F Reserved)} <byte 4366> utiny value {} <byte 4367> {rsvd2[13] (27-3F Reserved)} <byte 4367> utiny value {} <byte 4368> {rsvd2[20] (27-3F Reserved)} <byte 4368> utiny value {} <byte 4369> {rsvd2[19] (27-3F Reserved)} <byte 4369> utiny value {} <byte 4370> {rsvd2[18] (27-3F Reserved)} <byte 4370> utiny value {} <byte 4371> {rsvd2[17] (27-3F Reserved)} <byte 4371> utiny value {} <byte 4372> {rsvd2[24] (27-3F Reserved)} <byte 4372> utiny value {} <byte 4373> {rsvd2[23] (27-3F Reserved)} <byte 4373> utiny value {} <byte 4374> {rsvd2[22] (27-3F Reserved)} <byte 4374> utiny value {} <byte 4375> {rsvd2[21] (27-3F Reserved)} <byte 4375> utiny value {} <byte 4376> {supply_a_off (43 Supply A Turn Off <byte 4376> utiny value {} <byte 4377> {rsvd3 (42 Reserved)} <byte 4377> utiny value

(0xA5))}

{} <byte 4378> {kill_other (41 Kill Other Controller (0x37))} <byte 4378> utiny value {} <byte 4379> union dis_ctrl 40 Disable Control <byte 4379> {field (By field)} <byte 4379> tbits:1 ena_kill_other R/W Kill Other Controller - Enable tbits:1 rsvd1 R Reserved tbits:1 ena_ps_a_off R/W Power Supply A Off - Enable tbits:1 ena_ps_b_off R/W Power Supply B Off - Enable tbits:1 amb_ps_a_led R/W Amber Power Supply A Failure LED {E1} tbits:1 amb_ps_b_led R/W Amber Power Supply B Failure LED {E2} tbits:2 rsvd R Reserved {} or dis_ctrl 40 Disable Control <byte 4379> utiny value As utiny endunion dis_ctrl 40 Disable Control <byte 4380> union iic_bus_ctrl 47 Atlantis IIC Bus Control <byte 4380> {field (By field Bus: A B C D)} <byte 4380> tbits:3 iic_sel R/W IIC Bus Select {AA9, AB9, W9, Y9} tbits:5 rsvd R Reserved {} or iic_bus_ctrl 47 Atlantis IIC Bus Control <byte 4380> utiny value As utiny endunion iic_bus_ctrl 47 Atlantis IIC Bus Control <byte 4381> {rsvdz[1] (45-46 Reserved)} <byte 4381> utiny value {} <byte 4382> {rsvdz[0] (45-46 Reserved)} <byte 4382> utiny value {} <byte 4383> {supply_b_off (44 Supply B Turn Off (0xB5))} <byte 4383> utiny value {} <byte 4384> {rsvd4[3] (48-4F Reserved)} <byte 4384> utiny value {} <byte 4385> {rsvd4[2] (48-4F Reserved)} <byte 4385> utiny value {}

<byte 4386> {rsvd4[1] (48-4F Reserved)} <byte 4386> utiny value {} <byte 4387> {rsvd4[0] (48-4F Reserved)} <byte 4387> utiny value {} <byte 4388> {rsvd4[7] (48-4F Reserved)} <byte 4388> utiny value {} <byte 4389> {rsvd4[6] (48-4F Reserved)} <byte 4389> utiny value {} <byte 4390> {rsvd4[5] (48-4F Reserved)} <byte 4390> utiny value {} <byte 4391> {rsvd4[4] (48-4F Reserved)} <byte 4391> utiny value {} <byte 4392> {rsvd5[0] (51-5F Reserved)} <byte 4392> utiny value {} <byte 4393> union ena_smi_5 52 SMI Enables 47:40 <byte 4393> {field (By field)} <byte 4393> tbits:1 atlantis_bus_req Atlantis Bus Request tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4} tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9} tbits:1 rsvd Reserved tbits:1 dx2f_f1_dir_rst DX2F F1 DIR RST (Int=1) {E10} tbits:1 dx2f_f0_dir_rst DX2F F0 DIR RST (Int=1) {E11} tbits:1 dx2f_intb DX2F INTB (Int=0) {F10} tbits:1 dx2f_inta DX2F INTA (Int=0) {F11} {} or ena_smi_5 52 SMI Enables 47:40 <byte 4393> utiny value As utiny endunion ena_smi_5 52 SMI Enables 47:40 <byte 4394> union int_smi_5 51 SMI Interrupt 47:40 (Int=1) <byte 4394> {field (By field)} <byte 4394> tbits:1 atlantis_bus_req Atlantis Bus Request tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4}

tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9} tbits:1 rsvd Reserved tbits:1 dx2f_f1_dir_rst DX2F F1 DIR RST (Int=1) {E10} tbits:1 dx2f_f0_dir_rst DX2F F0 DIR RST (Int=1) {E11} tbits:1 dx2f_intb DX2F INTB (Int=0) {F10} tbits:1 dx2f_inta DX2F INTA (Int=0) {F11} {} or int_smi_5 51 SMI Interrupt 47:40 (Int=1) <byte 4394> utiny value As utiny endunion int_smi_5 51 SMI Interrupt 47:40 (Int=1) <byte 4395> union int_out 50 Interrupt Out <byte 4395> {field (By field)} <byte 4395> tbits:1 other_l R/W Int. to Other Ctrllr (Int=0) {V12} tbits:1 rsvd1 R Reserved {U12} tbits:1 smi_l R/W System Management Int. (Int=0) {B6} tbits:1 mcp_l R/W Machine Check Interrupt (Int=0) {A6} tbits:4 rsvd R Reserved {} or int_out 50 Interrupt Out <byte 4395> utiny value As utiny endunion int_out 50 Interrupt Out <byte 4396> {rsvd5[4] (51-5F Reserved)} <byte 4396> utiny value {} <byte 4397> {rsvd5[3] (51-5F Reserved)} <byte 4397> utiny value {} <byte 4398> {rsvd5[2] (51-5F Reserved)} <byte 4398> utiny value {} <byte 4399> {rsvd5[1] (51-5F Reserved)} <byte 4399> utiny value {} <byte 4400> {rsvd5[8] (51-5F Reserved)} <byte 4400> utiny value {} <byte 4401> {rsvd5[7] (51-5F Reserved)} <byte 4401> utiny value {} <byte 4402> {rsvd5[6] (51-5F Reserved)} <byte 4402> utiny value

{} <byte 4403> {rsvd5[5] (51-5F Reserved)} <byte 4403> utiny value {} <byte 4404> {rsvd5[12] (51-5F Reserved)} <byte 4404> utiny value {} <byte 4405> {rsvd5[11] (51-5F Reserved)} <byte 4405> utiny value {} <byte 4406> {rsvd5[10] (51-5F Reserved)} <byte 4406> utiny value {} <byte 4407> {rsvd5[9] (51-5F Reserved)} <byte 4407> utiny value {} <byte 4408> union int_smi_3 63 SMI Interrupt 31:24 (Int=1) <byte 4408> {field (By field)} <byte 4408> tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or int_smi_3 63 SMI Interrupt 31:24 (Int=1) <byte 4408> utiny value As utiny endunion int_smi_3 63 SMI Interrupt 31:24 (Int=1) <byte 4409> union int_smi_2 62 SMI Interrupt 23:16 (Int=1) <byte 4409> {field (By field)} <byte 4409> tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20} tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or int_smi_2 62 SMI Interrupt 23:16 (Int=1) <byte 4409>

utiny value As utiny endunion int_smi_2 62 SMI Interrupt 23:16 (Int=1) <byte 4410> union int_smi_1 61 SMI Interrupt 15:08 (Int=1) <byte 4410> {field (By field)} <byte 4410> tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20} tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or int_smi_1 61 SMI Interrupt 15:08 (Int=1) <byte 4410> utiny value As utiny endunion int_smi_1 61 SMI Interrupt 15:08 (Int=1) <byte 4411> union int_smi_0 60 SMI Interrupt 07:00 (Int=1) <byte 4411> {field (By field)} <byte 4411> tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {} or int_smi_0 60 SMI Interrupt 07:00 (Int=1) <byte 4411> utiny value As utiny endunion int_smi_0 60 SMI Interrupt 07:00 (Int=1) <byte 4412> union ena_smi_2 67 SMI Enables 23:16 <byte 4412> {field (By field)} <byte 4412> tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20} tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or ena_smi_2 67 SMI Enables 23:16 <byte 4412> utiny value As utiny endunion ena_smi_2 67 SMI Enables 23:16 <byte 4413> union ena_smi_1 66 SMI Enables 15:08 <byte 4413> {field (By field)}

{N22} {N21} {N20} {N19} {N18} {P18} {P22} {P21}

<byte 4413> tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20} tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or ena_smi_1 66 SMI Enables 15:08 <byte 4413> utiny value As utiny endunion ena_smi_1 66 SMI Enables 15:08 <byte 4414> union ena_smi_0 65 SMI Enables 07:00 <byte 4414> {field (By field)} <byte 4414> tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22} tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21} tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20} tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19} tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18} tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18} tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22} tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21} {} or ena_smi_0 65 SMI Enables 07:00 <byte 4414> utiny value As utiny endunion ena_smi_0 65 SMI Enables 07:00 <byte 4415> union int_smi_4 64 SMI Interrupt 39:32 (Int=1) <byte 4415> {field (By field)} <byte 4415> tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or int_smi_4 64 SMI Interrupt 39:32 (Int=1) <byte 4415> utiny value As utiny endunion int_smi_4 64 SMI Interrupt 39:32 (Int=1) <byte 4416> union int_mcp_1 6B MCP Interrupt 15:08 (Int=1) <byte 4416> {field (By field)} <byte 4416> tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20}

tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or int_mcp_1 6B MCP Interrupt 15:08 (Int=1) <byte 4416> utiny value As utiny endunion int_mcp_1 6B MCP Interrupt 15:08 (Int=1) <byte 4417> union int_mcp_0 6A MCP Interrupt 07:00 (Int=1) <byte 4417> {field (By field)} <byte 4417> tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22} tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21} tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20} tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19} tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18} tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18} tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22} tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21} {} or int_mcp_0 6A MCP Interrupt 07:00 (Int=1) <byte 4417> utiny value As utiny endunion int_mcp_0 6A MCP Interrupt 07:00 (Int=1) <byte 4418> union ena_smi_4 69 SMI Enables 39:32 <byte 4418> {field (By field)} <byte 4418> tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or ena_smi_4 69 SMI Enables 39:32 <byte 4418> utiny value As utiny endunion ena_smi_4 69 SMI Enables 39:32 <byte 4419> union ena_smi_3 68 SMI Enables 31:24 <byte 4419> {field (By field)} <byte 4419> tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or ena_smi_3 68 SMI Enables 31:24 <byte 4419>

utiny value As utiny endunion ena_smi_3 68 SMI Enables 31:24 <byte 4420> union ena_mcp_0 6F MCP Enables 07:00 <byte 4420> {field (By field)} <byte 4420> tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22} tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21} tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20} tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19} tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18} tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18} tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22} tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21} {} or ena_mcp_0 6F MCP Enables 07:00 <byte 4420> utiny value As utiny endunion ena_mcp_0 6F MCP Enables 07:00 <byte 4421> union int_mcp_4 6E MCP Interrupt 39:32 (Int=1) <byte 4421> {field (By field)} <byte 4421> tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or int_mcp_4 6E MCP Interrupt 39:32 (Int=1) <byte 4421> utiny value As utiny endunion int_mcp_4 6E MCP Interrupt 39:32 (Int=1) <byte 4422> union int_mcp_3 6D MCP Interrupt 31:24 (Int=1) <byte 4422> {field (By field)} <byte 4422> tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or int_mcp_3 6D MCP Interrupt 31:24 (Int=1) <byte 4422> utiny value As utiny endunion int_mcp_3 6D MCP Interrupt 31:24 (Int=1) <byte 4423> union int_mcp_2 6C MCP Interrupt 23:16 (Int=1) <byte 4423> {field (By field)}

<byte 4423> tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20} tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or int_mcp_2 6C MCP Interrupt 23:16 (Int=1) <byte 4423> utiny value As utiny endunion int_mcp_2 6C MCP Interrupt 23:16 (Int=1) <byte 4424> union ena_mcp_4 73 MCP Enables 39:32 <byte 4424> {field (By field)} <byte 4424> tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or ena_mcp_4 73 MCP Enables 39:32 <byte 4424> utiny value As utiny endunion ena_mcp_4 73 MCP Enables 39:32 <byte 4425> union ena_mcp_3 72 MCP Enables 31:24 <byte 4425> {field (By field)} <byte 4425> tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or ena_mcp_3 72 MCP Enables 31:24 <byte 4425> utiny value As utiny endunion ena_mcp_3 72 MCP Enables 31:24 <byte 4426> union ena_mcp_2 71 MCP Enables 23:16 <byte 4426> {field (By field)} <byte 4426> tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20}

tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or ena_mcp_2 71 MCP Enables 23:16 <byte 4426> utiny value As utiny endunion ena_mcp_2 71 MCP Enables 23:16 <byte 4427> union ena_mcp_1 70 MCP Enables 15:08 <byte 4427> {field (By field)} <byte 4427> tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20} tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or ena_mcp_1 70 MCP Enables 15:08 <byte 4427> utiny value As utiny endunion ena_mcp_1 70 MCP Enables 15:08 <byte 4428> union int_in_3 77 Interrupt Inputs 31:24 <byte 4428> {field (By field)} <byte 4428> tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or int_in_3 77 Interrupt Inputs 31:24 <byte 4428> utiny value As utiny endunion int_in_3 77 Interrupt Inputs 31:24 <byte 4429> union int_in_2 76 Interrupt Inputs 23:16 <byte 4429> {field (By field)} <byte 4429> tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20} tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or int_in_2 76 Interrupt Inputs 23:16 <byte 4429>

utiny value As utiny endunion int_in_2 76 Interrupt Inputs 23:16 <byte 4430> union int_in_1 75 Interrupt Inputs 15:08 <byte 4430> {field (By field)} <byte 4430> tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20} tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or int_in_1 75 Interrupt Inputs 15:08 <byte 4430> utiny value As utiny endunion int_in_1 75 Interrupt Inputs 15:08 <byte 4431> union int_in_0 74 Interrupt Inputs 07:00 <byte 4431> {field (By field)} <byte 4431> tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22} tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21} tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20} tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19} tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18} tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18} tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22} tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21} {} or int_in_0 74 Interrupt Inputs 07:00 <byte 4431> utiny value As utiny endunion int_in_0 74 Interrupt Inputs 07:00 <byte 4432> union int_mcp_5 7B MCP Interrupt 47:40 <byte 4432> {field (By field)} <byte 4432> tbits:1 atlantis_bus_req Atlantis Bus Request tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4} tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9} tbits:1 rsvd Reserved tbits:1 dx2f_f1_dir_rst DX2F F1 DIR RST (Int=1) {E10} tbits:1 dx2f_f0_dir_rst DX2F F0 DIR RST (Int=1) {E11} tbits:1 dx2f_intb DX2F INTB (Int=0) {F10} tbits:1 dx2f_inta DX2F INTA (Int=0) {F11} {} or int_mcp_5 7B MCP Interrupt 47:40 <byte 4432> utiny value As utiny endunion int_mcp_5 7B MCP Interrupt 47:40 <byte 4433> union int_in_5 7A Interrupt Inputs 47:40 <byte 4433> {field (By field)}

<byte 4433> tbits:1 atlantis_bus_req Atlantis Bus Request tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4} tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9} tbits:1 rsvd Reserved tbits:1 dx2f_f1_dir_rst DX2F F1 DIR RST (Int=1) {E10} tbits:1 dx2f_f0_dir_rst DX2F F0 DIR RST (Int=1) {E11} tbits:1 dx2f_intb DX2F INTB (Int=0) {F10} tbits:1 dx2f_inta DX2F INTA (Int=0) {F11} {} or int_in_5 7A Interrupt Inputs 47:40 <byte 4433> utiny value As utiny endunion int_in_5 7A Interrupt Inputs 47:40 <byte 4434> union int_smi_pulsed 79 SMI Latched Pulse Interrupts <byte 4434> {field (By field)} <byte 4434> tbits:2 rsvd2 Reserved tbits:1 sdc_int SDC Latched Int. (Int=1) tbits:1 rsvd1 Reserved tbits:1 lcd_int LCD Latched Int. (Int=1) tbits:3 rsvd Reserved {} or int_smi_pulsed 79 SMI Latched Pulse Interrupts <byte 4434> utiny value As utiny endunion int_smi_pulsed 79 SMI Latched Pulse Interrupts <byte 4435> union int_in_4 78 Interrupt Inputs 39:32 <byte 4435> {field (By field)} <byte 4435> tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or int_in_4 78 Interrupt Inputs 39:32 <byte 4435> utiny value As utiny endunion int_in_4 78 Interrupt Inputs 39:32 <byte 4436> {rsvda[2] (7D-7F Reserved)} <byte 4436> utiny value {} <byte 4437> {rsvda[1] (7D-7F Reserved)} <byte 4437> utiny value {} <byte 4438> {rsvda[0] (7D-7F Reserved)} <byte 4438>

utiny value {} <byte 4439> union ena_mcp_5 7C MCP Enables 47:40 <byte 4439> {field (By field)} <byte 4439> tbits:1 atlantis_bus_req Atlantis Bus Request tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4} tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9} tbits:1 rsvd Reserved tbits:1 dx2f_f1_dir_rst DX2F F1 DIR RST (Int=1) {E10} tbits:1 dx2f_f0_dir_rst DX2F F0 DIR RST (Int=1) {E11} tbits:1 dx2f_intb DX2F INTB (Int=0) {F10} tbits:1 dx2f_inta DX2F INTA (Int=0) {F11} {} or ena_mcp_5 7C MCP Enables 47:40 <byte 4439> utiny value As utiny endunion ena_mcp_5 7C MCP Enables 47:40 <byte 4440> {int_sci_3 (83 State Change Interrupt 31:24)} <byte 4440> utiny value {} <byte 4441> union int_sci_2 82 State Change Interrupt 23:16 <byte 4441> {field (By field)} <byte 4441> tbits:1 sfp3_l SFP 3 Present Lo {R1} tbits:1 sfp2_l SFP 2 Present Lo {R2} tbits:1 sfp1_l SFP 1 Present Lo {R3} tbits:1 sfp0_l SFP 0 Present Lo {R4} tbits:1 agent_pres_l Agent Present Lo {T1} tbits:1 ups1_pres_l UPS 1 Present Lo {T2} tbits:1 ps_a_dcok_l Power Supply A DC OK Lo {U3} tbits:1 ps_b_dcok_l Power Supply B DC OK Lo {U4} {} or int_sci_2 82 State Change Interrupt 23:16 <byte 4441> utiny value As utiny endunion int_sci_2 82 State Change Interrupt 23:16 <byte 4442> union int_sci_1 81 State Change Interrupt 15:08 <byte 4442> {field (By field)} <byte 4442> tbits:1 sfp9_l SFP 9 Present Lo {N5} tbits:1 sfp8_l SFP 8 Present Lo {N6} tbits:1 sprite_hw_rdy_l Sprite HW ready Lo {P1} tbits:1 lcd_l LCD Present Lo {P2} tbits:1 sfp7_l SFP 7 Present Lo {P3} tbits:1 sfp6_l SFP 6 Present Lo {P4} tbits:1 sfp5_l SFP 5 Present Lo {P5} tbits:1 sfp4_l SFP 4 Present Lo {P6} {} or int_sci_1 81 State Change Interrupt 15:08 <byte 4442> utiny value As utiny

endunion int_sci_1 81 State Change Interrupt 15:08 <byte 4443> union int_sci_0 80 State Change Interrupt 07:00 <byte 4443> {field (By field)} <byte 4443> tbits:1 ps_b_pres_l Power Supply B Present (Int=1) {M3} tbits:1 ps_a_pres_l Power Supply A Present (Int=1) {M4} tbits:1 sfp11_l SFP 11 Present Lo {M5} tbits:1 sfp10_l SFP 10 Present Lo {M6} tbits:1 bhm_pres_l Bulkhead Modules (Int=1) {N1} Present tbits:1 mpi_pres_l Mid Plane Interconnect (Int=1) {N2} Present tbits:1 clf_pres_l Flash Card Present Lo {N3} tbits:1 other_ok_l Other Controller OK Lo (Int=1) {N4} {} or int_sci_0 80 State Change Interrupt 07:00 <byte 4443> utiny value As utiny endunion int_sci_0 80 State Change Interrupt 07:00 <byte 4444> union ena_sci_1 87 State Change Int Enable 15:08 <byte 4444> {field (By field)} <byte 4444> tbits:1 sfp9_l SFP 9 Present Lo {N5} tbits:1 sfp8_l SFP 8 Present Lo {N6} tbits:1 sprite_hw_rdy_l Sprite HW ready Lo {P1} tbits:1 lcd_l LCD Present Lo {P2} tbits:1 sfp7_l SFP 7 Present Lo {P3} tbits:1 sfp6_l SFP 6 Present Lo {P4} tbits:1 sfp5_l SFP 5 Present Lo {P5} tbits:1 sfp4_l SFP 4 Present Lo {P6} {} or ena_sci_1 87 State Change Int Enable 15:08 <byte 4444> utiny value As utiny endunion ena_sci_1 87 State Change Int Enable 15:08 <byte 4445> union ena_sci_0 86 State Change Int Enable 07:00 <byte 4445> {field (By field)} <byte 4445> tbits:1 ps_b_pres_l Power Supply B Present (Int=1) {M3} tbits:1 ps_a_pres_l Power Supply A Present (Int=1) {M4} tbits:1 sfp11_l SFP 11 Present Lo {M5} tbits:1 sfp10_l SFP 10 Present Lo {M6} tbits:1 bhm_pres_l Bulkhead Modules (Int=1) {N1} Present tbits:1 mpi_pres_l Mid Plane Interconnect (Int=1) {N2} Present tbits:1 clf_pres_l Flash Card Present Lo {N3} tbits:1 other_ok_l Other Controller OK Lo (Int=1) {N4} {} or ena_sci_0 86 State Change Int Enable 07:00 <byte 4445> utiny value As utiny endunion ena_sci_0 86 State Change Int Enable 07:00 <byte 4446> {rsvdb (85 Reserved)} <byte 4446> utiny value {}

Lo Lo

Lo Lo

<byte 4447> union int_sci_4 84 State Change Interrupt 39:32 <byte 4447> {field (By field)} <byte 4447> tbits:1 batt_det Battery Detect tbits:1 blower_det Blower Detect tbits:1 meltdown_temp_minus_4C_det Meltdown Temp minus 4 degrees C detect tbits:1 meltdown_temp_det Meltdown Temperature detect tbits:4 rsvd Reserved {} or int_sci_4 84 State Change Interrupt 39:32 <byte 4447> utiny value As utiny endunion int_sci_4 84 State Change Interrupt 39:32 <byte 4448> {rsvdc (8B Reserved)} <byte 4448> utiny value {} <byte 4449> union ena_sci_4 8A State Change Int Enable 39:32 <byte 4449> {field (By field)} <byte 4449> tbits:1 batt_det Battery Detect tbits:1 blower_det Blower Detect tbits:1 meltdown_temp_minus_4C_det Meltdown Temp minus 4 degrees C detect tbits:1 meltdown_temp_det Meltdown Temperature detect tbits:4 rsvd Reserved {} or ena_sci_4 8A State Change Int Enable 39:32 <byte 4449> utiny value As utiny endunion ena_sci_4 8A State Change Int Enable 39:32 <byte 4450> {ena_sci_3 (89 State Change Int Enable 31:24)} <byte 4450> utiny value {} <byte 4451> union ena_sci_2 88 State Change Int Enable 23:16 <byte 4451> {field (By field)} <byte 4451> tbits:1 sfp3_l SFP 3 Present Lo {R1} tbits:1 sfp2_l SFP 2 Present Lo {R2} tbits:1 sfp1_l SFP 1 Present Lo {R3} tbits:1 sfp0_l SFP 0 Present Lo {R4} tbits:1 agent_pres_l Agent Present Lo {T1} tbits:1 ups1_pres_l UPS 1 Present Lo {T2} tbits:1 ps_a_dcok_l Power Supply A DC OK Lo {U3} tbits:1 ps_b_dcok_l Power Supply B DC OK Lo {U4} {} or ena_sci_2 88 State Change Int Enable 23:16 <byte 4451> utiny value As utiny endunion ena_sci_2 88 State Change Int Enable 23:16 <byte 4452> {sc_in_3 (8F State Change Inputs 31:24)}

<byte 4452> utiny value {} <byte 4453> union sc_in_2 8E State Change Inputs 23:16 <byte 4453> {field (By field)} <byte 4453> tbits:1 sfp3_l SFP 3 Present Lo {R1} tbits:1 sfp2_l SFP 2 Present Lo {R2} tbits:1 sfp1_l SFP 1 Present Lo {R3} tbits:1 sfp0_l SFP 0 Present Lo {R4} tbits:1 agent_pres_l Agent Present Lo {T1} tbits:1 ups1_pres_l UPS 1 Present Lo {T2} tbits:1 ps_a_dcok_l Power Supply A DC OK Lo {U3} tbits:1 ps_b_dcok_l Power Supply B DC OK Lo {U4} {} or sc_in_2 8E State Change Inputs 23:16 <byte 4453> utiny value As utiny endunion sc_in_2 8E State Change Inputs 23:16 <byte 4454> union sc_in_1 8D State Change Inputs 15:08 <byte 4454> {field (By field)} <byte 4454> tbits:1 sfp9_l SFP 9 Present Lo {N5} tbits:1 sfp8_l SFP 8 Present Lo {N6} tbits:1 sprite_hw_rdy_l Sprite HW ready Lo {P1} tbits:1 lcd_l LCD Present Lo {P2} tbits:1 sfp7_l SFP 7 Present Lo {P3} tbits:1 sfp6_l SFP 6 Present Lo {P4} tbits:1 sfp5_l SFP 5 Present Lo {P5} tbits:1 sfp4_l SFP 4 Present Lo {P6} {} or sc_in_1 8D State Change Inputs 15:08 <byte 4454> utiny value As utiny endunion sc_in_1 8D State Change Inputs 15:08 <byte 4455> union sc_in_0 8C State Change Inputs 07:00 <byte 4455> {field (By field)} <byte 4455> tbits:1 ps_b_pres_l Power Supply B Present (Int=1) {M3} tbits:1 ps_a_pres_l Power Supply A Present (Int=1) {M4} tbits:1 sfp11_l SFP 11 Present Lo {M5} tbits:1 sfp10_l SFP 10 Present Lo {M6} tbits:1 bhm_pres_l Bulkhead Modules (Int=1) {N1} Present Lo tbits:1 mpi_pres_l Mid Plane Interconnect (Int=1) {N2} Present Lo tbits:1 clf_pres_l Flash Card Present Lo {N3} tbits:1 other_ok_l Other Controller OK Lo (Int=1) {N4} {} or sc_in_0 8C State Change Inputs 07:00 <byte 4455> utiny value As utiny endunion sc_in_0 8C State Change Inputs 07:00 <byte 4456> {rsvdd[0] (93-9F Reserved)} <byte 4456>

utiny value {} <byte 4457> {batt_good_tp (92 Battery Good Trip Point)} <byte 4457> utiny value {} <byte 4458> {batt_lo_tp (91 Battery Low Trip Point)} <byte 4458> utiny value {} <byte 4459> {melt_down (90 Meltdown Temp.)} <byte 4459> utiny value {} <byte 4460> {rsvdd[4] (93-9F Reserved)} <byte 4460> utiny value {} <byte 4461> {rsvdd[3] (93-9F Reserved)} <byte 4461> utiny value {} <byte 4462> {rsvdd[2] (93-9F Reserved)} <byte 4462> utiny value {} <byte 4463> {rsvdd[1] (93-9F Reserved)} <byte 4463> utiny value {} <byte 4464> {rsvdd[8] (93-9F Reserved)} <byte 4464> utiny value {} <byte 4465> {rsvdd[7] (93-9F Reserved)} <byte 4465> utiny value {} <byte 4466> {rsvdd[6] (93-9F Reserved)} <byte 4466> utiny value {} <byte 4467> {rsvdd[5] (93-9F Reserved)} <byte 4467> utiny value {} <byte 4468> {rsvdd[12] (93-9F Reserved)} <byte 4468>

utiny value {} <byte 4469> {rsvdd[11] (93-9F Reserved)} <byte 4469> utiny value {} <byte 4470> {rsvdd[10] (93-9F Reserved)} <byte 4470> utiny value {} <byte 4471> {rsvdd[9] (93-9F Reserved)} <byte 4471> utiny value {} <byte 4472> union reset_dev_0 A3 GPO D: Reset Devices Ctrl 0 <byte 4472> {field (By field)} <byte 4472> tbits:1 dx2_a_l DX2 A Reset Lo {M21} tbits:1 dx2_b_l DX2 B Reset Lo {M20} tbits:1 dx2_c_l DX2 C Reset Lo {M19} tbits:1 dx2_d_l DX2 D Reset Lo {M18} tbits:1 sprite_l SPRITE Reset Lo {D1} tbits:1 uart_l UART Reset Lo {W17} tbits:1 enet1_l Ethernet 1 Reset Lo {Y17} tbits:1 enet2_l Ethernet 2 Reset Lo {AA18} {} or reset_dev_0 A3 GPO D: Reset Devices Ctrl 0 <byte 4472> utiny value As utiny endunion reset_dev_0 A3 GPO D: Reset Devices Ctrl 0 <byte 4473> union reprog_misc A2 GPO C: Reprog. & Misc. Ctrl <byte 4473> {field (By field)} <byte 4473> tbits:1 prog_sdc SDC reprogram mode (prog=1) {Y13} tbits:1 prog_can CAN reprogram mode (prog=1) {W13} tbits:1 prog_lcd LCD reprogram mode (prog=1) {V13} tbits:1 rpgm_clk Shared PIC reprogram clock {U13} tbits:1 rpgm_data Shared PIC reprogram data {W18} tbits:1 dx2_e_l DX2 E Reset L {V7} tbits:1 sdc_wdt SDC watchdog enable {Y5} tbits:1 dx2_f_l DX2 F Reset L {Y12} {} or reprog_misc A2 GPO C: Reprog. & Misc. Ctrl <byte 4473> utiny value As utiny endunion reprog_misc A2 GPO C: Reprog. & Misc. Ctrl <byte 4474> union sfp_laser A1 GPO B: SFP Laser Disable Ctrl <byte 4474> {field (By field)} <byte 4474> tbits:1 disable_0 SFP Laser 0 Disable (dis=1) {E18} tbits:1 disable_1 SFP Laser 1 Disable (dis=1) {F18}

tbits:1 disable_2 SFP Laser 2 Disable (dis=1) {G22} tbits:1 disable_3 SFP Laser 3 Disable (dis=1) {G21} tbits:1 disable_4 SFP Laser 4 Disable (dis=1) {H22} tbits:1 disable_5 SFP Laser 5 Disable (dis=1) {H21} tbits:1 disable_6 SFP Laser 6 Disable (dis=1) {H20} tbits:1 disable_7 SFP Laser 7 Disable (dis=1) {H19} {} or sfp_laser A1 GPO B: SFP Laser Disable Ctrl <byte 4474> utiny value As utiny endunion sfp_laser A1 GPO B: SFP Laser Disable Ctrl <byte 4475> union pcix01 A0 GPO A: PCIX 0 & 1 Bus Signals <byte 4475> {field (By field)} <byte 4475> tbits:1 bus0_stop_l Bus 0 STOP Lo {C22} tbits:1 bus0_trdy_l Bus 0 TRDY Lo {C21} tbits:1 bus0_devsel_l Bus 0 DEVSEL0 Lo {D22} tbits:1 bus0_req64_l Bus 0 REQ64 Lo {D21} tbits:2 rsvd1 Reserved tbits:1 pcix1_cfg_en PCIX1 Configuration Enable {E20} tbits:1 rsvd Reserved {} or pcix01 A0 GPO A: PCIX 0 & 1 Bus Signals <byte 4475> utiny value As utiny endunion pcix01 A0 GPO A: PCIX 0 & 1 Bus Signals <byte 4476> union gbic_act A7 GPI I: GBIC active <byte 4476> {field (By field)} <byte 4476> tbits:1 dx2a_f0 DX2A F0 ACTIVE {W1} tbits:1 dx2b_f0 DX2B F0 ACTIVE {W2} tbits:1 dx2c_f0 DX2C F0 ACTIVE {V3} tbits:1 dx2d_f0 DX2D F0 ACTIVE {V4} tbits:1 dx2e_f0 DX2E F0 ACTIVE {H2} tbits:1 temp0_ovr_thresh Temp Sensor 0 Over Threshold {AB19} tbits:1 temp1_ovr_thresh Temp Sensor 1 Over Threshold {AA17} tbits:1 temp2_ovr_thresh Temp Sensor 2 Over Threshold {Y18} {} or gbic_act A7 GPI I: GBIC active <byte 4476> utiny value As utiny endunion gbic_act A7 GPI I: GBIC active <byte 4477> union gbic_led A6 GPO G: GBIC LED Control <byte 4477> {field (By field)} <byte 4477> tbits:1 amb0_l R/W Amber 0 LED FLASH OFF Lo {E16} tbits:1 amb1_l R/W Amber 1 LED FLASH OFF Lo {E17} tbits:1 amb2_l R/W Amber 2 LED FLASH OFF Lo {A17} tbits:1 amb3_l R/W Amber 3 LED FLASH OFF Lo {B17} tbits:1 amb4_l R/W Amber 4 LED FLASH OFF Lo {C17} tbits:1 amb5_l R/W Amber 5 LED FLASH OFF Lo {D17} tbits:1 amb6_l R/W Amber 6 LED FLASH OFF Lo {A18} tbits:1 amb7_l R/W Amber 7 LED FLASH OFF Lo {B18} {}

or gbic_led A6 GPO G: GBIC LED Control <byte 4477> utiny value As utiny endunion gbic_led A6 GPO G: GBIC LED Control <byte 4478> union gp_in A5 GPI F: Kills, msref_req, etc. <byte 4478> {field (By field)} <byte 4478> tbits:1 dx2f_f0 DX2F F0 ACTIVE {AB17} tbits:1 rsvd Reserved {AA13} tbits:1 enet_card_gpi_1 Ethernet Card GPI_1 {V5} tbits:1 spr_debug2 Sprite Debug Bit2 {B4} tbits:1 msref_req_l MSREF_REQ Sense Line (0=SelfRef) {Y2} tbits:1 lcd_ready LCD Ready {L22} tbits:1 spr_debug3 Sprite Debug Bit3 {A4} tbits:1 rpgm_data_in Shared PIC reprogram data in {AA4} {} or gp_in A5 GPI F: Kills, msref_req, etc. <byte 4478> utiny value As utiny endunion gp_in A5 GPI F: Kills, msref_req, etc. <byte 4479> union reset_dev_1 A4 GPO E: Reset Devices Ctrl 1 <byte 4479> {field (By field)} <byte 4479> tbits:1 bezel_hb_led Bezel heart beat LED (Default=Off=1){AB5} tbits:1 sdc_l SDC Reset Lo {AA5} tbits:1 can_l CAN Reset Lo {Y6} tbits:1 lcd_l LCD Reset Lo {W6} tbits:1 toy_l TOY Reset Lo {V6} tbits:1 bezel_flt_led Bezel fault LED (Default=On=0) {W5} tbits:1 dpm_rdy PPC not accessing DPM {X} tbits:1 sdc_int_l glue to sdc interrupt (Int=0) {AB18} {} or reset_dev_1 A4 GPO E: Reset Devices Ctrl 1 <byte 4479> utiny value As utiny endunion reset_dev_1 A4 GPO E: Reset Devices Ctrl 1 <byte 4480> {rsvde[2] (A9-AE Reserved)} <byte 4480> utiny value {} <byte 4481> {rsvde[1] (A9-AE Reserved)} <byte 4481> utiny value {} <byte 4482> {rsvde[0] (A9-AE Reserved)} <byte 4482> utiny value {} <byte 4483> union gbic_led8 A8 GPO H: GBIC LED Control <byte 4483> {field (By field)} <byte 4483>

tbits:1 amb8_l R/W Amber 8 LED FLASH OFF Lo {Y2} tbits:1 amb9_l R/W Amber 9 LED FLASH OFF Lo {Y1} tbits:1 disable_8 SFP Laser 8 Disable (dis=1) {U5} tbits:1 disable_9 SFP Laser 9 Disable (dis=1) {V5} tbits:4 unused unused {} or gbic_led8 A8 GPO H: GBIC LED Control <byte 4483> utiny value As utiny endunion gbic_led8 A8 GPO H: GBIC LED Control <byte 4484> union cache_ctrl AF Cache DIMM Control <byte 4484> {field (By field)} <byte 4484> tbits:1 msref_req_l R/W MSREF_REQ (0=Self-Refresh) {AB8} tbits:1 dimm0_rst_l R/W DIMM 0 Reset Lo {D10} tbits:1 dimm1_rst_l R/W DIMM 1 Reset Lo {C10} tbits:1 dimm2_rst_l R/W DIMM 2 Reset Lo {B10} tbits:1 dimm3_rst_l R/W DIMM 3 Reset Lo {A10} tbits:1 bbu_dcok_clear R/W BBU DIMM DC OK LATCH CLEAR {AA8} tbits:1 batt_on_l R/W Battery Turn ON Lo (to preset) {Y8} tbits:1 batt_off_l R/W Battery Turn OFF Lo (to clear) {W8} {} or cache_ctrl AF Cache DIMM Control <byte 4484> utiny value As utiny endunion cache_ctrl AF Cache DIMM Control <byte 4485> {rsvde[5] (A9-AE Reserved)} <byte 4485> utiny value {} <byte 4486> {rsvde[4] (A9-AE Reserved)} <byte 4486> utiny value {} <byte 4487> {rsvde[3] (A9-AE Reserved)} <byte 4487> utiny value {} <byte 4488> {ppc_data[2] (B1-B4 PPC command data)} <byte 4488> utiny value {} <byte 4489> {ppc_data[1] (B1-B4 PPC command data)} <byte 4489> utiny value {} <byte 4490> {ppc_data[0] (B1-B4 PPC command data)} <byte 4490> utiny value {} <byte 4491> {ppc_cmd (B0 PPC command to SDC)}

<byte 4491> utiny value {} <byte 4492> {sdc_toy[1] (B6-BC sdc toy data)} <byte 4492> utiny value {} <byte 4493> {sdc_toy[0] (B6-BC sdc toy data)} <byte 4493> utiny value {} <byte 4494> {rsvb5 (B5 Reserved)} <byte 4494> utiny value {} <byte 4495> {ppc_data[3] (B1-B4 PPC command data)} <byte 4495> utiny value {} <byte 4496> {sdc_toy[5] (B6-BC sdc toy data)} <byte 4496> utiny value {} <byte 4497> {sdc_toy[4] (B6-BC sdc toy data)} <byte 4497> utiny value {} <byte 4498> {sdc_toy[3] (B6-BC sdc toy data)} <byte 4498> utiny value {} <byte 4499> {sdc_toy[2] (B6-BC sdc toy data)} <byte 4499> utiny value {} <byte 4500> union blower_led BF Blower LED Override Control <byte 4500> {field (By field)} <byte 4500> tbits:1 grn_blwr_a R/W Green Blower A LED tbits:1 amb_blwr_a R/W Amber Blower A LED tbits:1 grn_blwr_b R/W Green Blower B LED tbits:1 amb_blwr_b R/W Amber Blower B LED tbits:4 rsvd R Reserved {} or blower_led BF Blower LED Override Control <byte 4500> utiny value As utiny endunion blower_led BF Blower LED Override Control <byte 4501> union batt_led BE Battery LED Override Control

<byte 4501> {field (By field)} <byte 4501> tbits:1 grn_brk0 R/W Green Brick 0 LED tbits:1 amb_brk0 R/W Amber Brick 0 LED tbits:1 grn_brk1 R/W Green Brick 1 LED tbits:1 amb_brk1 R/W Amber Brick 1 LED tbits:1 grn_brk2 R/W Green Brick 2 LED tbits:1 amb_brk2 R/W Amber Brick 2 LED tbits:1 grn_brk3 R/W Green Brick 3 LED tbits:1 amb_brk3 R/W Amber Brick 3 LED {} or batt_led BE Battery LED Override Control <byte 4501> utiny value As utiny endunion batt_led BE Battery LED Override Control <byte 4502> {rsvbd (BD Reserved)} <byte 4502> utiny value {} <byte 4503> {sdc_toy[6] (B6-BC sdc toy data)} <byte 4503> utiny value {} <byte 4504> {batt_mod_rev[3] (C0-C3 Battery Mod. Rev.)} <byte 4504> utiny value {} <byte 4505> {batt_mod_rev[2] (C0-C3 Battery Mod. Rev.)} <byte 4505> utiny value {} <byte 4506> {batt_mod_rev[1] (C0-C3 Battery Mod. Rev.)} <byte 4506> utiny value {} <byte 4507> {batt_mod_rev[0] (C0-C3 Battery Mod. Rev.)} <byte 4507> utiny value {} <byte 4508> {avg_temp (C7 Average Temperature)} <byte 4508> utiny value {} <byte 4509> {temp_sensor[2] (C4-C6 Temp. Sensors 1, 2, & 3)} <byte 4509> utiny value {} <byte 4510> {temp_sensor[1] (C4-C6 Temp. Sensors 1, 2, & 3)} <byte 4510> utiny value

{} <byte 4511> {temp_sensor[0] (C4-C6 Temp. Sensors 1, 2, & 3)} <byte 4511> utiny value {} <byte 4512> {backup_time[1] (CA-CB backup time in x Watt-Sec)} <byte 4512> utiny value {} <byte 4513> {backup_time[0] (CA-CB backup time in x Watt-Sec)} <byte 4513> utiny value {} <byte 4514> {blower_rpm[1] (C8-C9 RPMs, Blowers 0 & 1)} <byte 4514> utiny value {} <byte 4515> {blower_rpm[0] (C8-C9 RPMs, Blowers 0 & 1)} <byte 4515> utiny value {} <byte 4516> {rsvcf (CF Spare Read Registers)} <byte 4516> utiny value {} <byte 4517> {volts_12v (CE 12V Level)} <byte 4517> utiny value {} <byte 4518> {sdc_major_rev (CD SDC Major Revision)} <byte 4518> utiny value {} <byte 4519> {sdc_minor_rev (CC SDC Minor Revision)} <byte 4519> utiny value {} <byte 4520> {brick_status[1] (D2-D5 brick interrupt status)} <byte 4520> utiny value {} <byte 4521> {brick_status[0] (D2-D5 brick interrupt status)} <byte 4521> utiny value {} <byte 4522> union sdc_int_cause1 D1 SDC interrupt cause1 <byte 4522> {field (By field)}

<byte 4522> tbits:1 rsvd R/WA0 Reserved tbits:1 cmd_processed R/WA0 PPC command has been processed tbits:2 rsvd1 R/WA0 Reserved tbits:1 hut_changed R/WA0 Hold up time changed tbits:2 rsvd2 R/WA0 Reserved tbits:1 time_req R/WA0 SDC time request {} or sdc_int_cause1 D1 SDC interrupt cause1 <byte 4522> utiny value As utiny endunion sdc_int_cause1 D1 SDC interrupt cause1 <byte 4523> union sdc_int_cause0 D0 SDC interrupt cause0 <byte 4523> {field (By field)} <byte 4523> tbits:1 brick0 R/WA0 Brick 0 tbits:1 brick1 R/WA0 Brick 1 tbits:1 brick2 R/WA0 Brick 2 tbits:1 brick3 R/WA0 Brick 3 tbits:1 blower0 R/WA0 Blower 0 tbits:1 blower1 R/WA0 Blower 1 tbits:1 temperature R/WA0 Temperature tbits:1 rsvd R/WA0 Reserved {} or sdc_int_cause0 D0 SDC interrupt cause0 <byte 4523> utiny value As utiny endunion sdc_int_cause0 D0 SDC interrupt cause0 <byte 4524> {blower_status[1] (D6-D7 blower interrupt status)} <byte 4524> utiny value {} <byte 4525> {blower_status[0] (D6-D7 blower interrupt status)} <byte 4525> utiny value {} <byte 4526> {brick_status[3] (D2-D5 brick interrupt status)} <byte 4526> utiny value {} <byte 4527> {brick_status[2] (D2-D5 brick interrupt status)} <byte 4527> utiny value {} <byte 4528> {sdc_cmd_status (DB Battery Hold Up Time)} <byte 4528> utiny value {} <byte 4529> union fru_detect DA fru detect bits <byte 4529> {field (By field)} <byte 4529>

tbits:1 brick0_present R tbits:1 brick1_present R tbits:1 brick2_present R tbits:1 brick3_present R tbits:1 blower0_present R tbits:1 blower1_present R tbits:2 rsvd R {} or fru_detect DA fru detect bits <byte 4529> utiny value As utiny endunion fru_detect DA fru detect bits <byte 4530> {sdc_status (D9 SDC codeload and brick test results)} <byte 4530> utiny value {} <byte 4531> {tmp_status (D8 temperature interrupt status)} <byte 4531> utiny value {} <byte 4532> {sdc_cmd_data[3] (DC-DF Reserved)} <byte 4532> utiny value {} <byte 4533> {sdc_cmd_data[2] (DC-DF Reserved)} <byte 4533> utiny value {} <byte 4534> {sdc_cmd_data[1] (DC-DF Reserved)} <byte 4534> utiny value {} <byte 4535> {sdc_cmd_data[0] (DC-DF Reserved)} <byte 4535> utiny value {} <byte 4536> {scratch[3] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4536> utiny value {} <byte 4537> {scratch[2] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4537> utiny value {} <byte 4538> {scratch[1] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4538> utiny value {}

<byte 4539> {scratch[0] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4539> utiny value {} <byte 4540> {scratch[7] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4540> utiny value {} <byte 4541> {scratch[6] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4541> utiny value {} <byte 4542> {scratch[5] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4542> utiny value {} <byte 4543> {scratch[4] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4543> utiny value {} <byte 4544> {scratch[11] (E0-EF R/W Scratch Registers: Hardware team maintains right to re serve higher bytes if future Glue features need the space.)} <byte 4544> utiny value {} <byte 4545> {scratch[10] (E0-EF R/W Scratch Registers: Hardware team maintains right to re serve higher bytes if future Glue features need the space.)} <byte 4545> utiny value {} <byte 4546> {scratch[9] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4546> utiny value {} <byte 4547> {scratch[8] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4547> utiny value {} <byte 4548> {scratch[15] (E0-EF R/W Scratch Registers: Hardware team maintains right to re serve higher bytes if future Glue features need the space.)} <byte 4548> utiny value {}

<byte 4549> {scratch[14] (E0-EF R/W Scratch serve higher bytes if future Glue <byte 4549> utiny value {} <byte 4550> {scratch[13] (E0-EF R/W Scratch serve higher bytes if future Glue <byte 4550> utiny value {} <byte 4551> {scratch[12] (E0-EF R/W Scratch serve higher bytes if future Glue <byte 4551> utiny value {} <byte 4552> {rsvd12[3] (F0-FD Reserved)} <byte 4552> utiny value {} <byte 4553> {rsvd12[2] (F0-FD Reserved)} <byte 4553> utiny value {} <byte 4554> {rsvd12[1] (F0-FD Reserved)} <byte 4554> utiny value {} <byte 4555> {rsvd12[0] (F0-FD Reserved)} <byte 4555> utiny value {} <byte 4556> {rsvd12[7] (F0-FD Reserved)} <byte 4556> utiny value {} <byte 4557> {rsvd12[6] (F0-FD Reserved)} <byte 4557> utiny value {} <byte 4558> {rsvd12[5] (F0-FD Reserved)} <byte 4558> utiny value {} <byte 4559> {rsvd12[4] (F0-FD Reserved)} <byte 4559> utiny value {} <byte 4560> {rsvd12[11] (F0-FD Reserved)}

Registers: Hardware team maintains right to re features need the space.)}

Registers: Hardware team maintains right to re features need the space.)}

Registers: Hardware team maintains right to re features need the space.)}

<byte 4560> utiny value {} <byte 4561> {rsvd12[10] (F0-FD Reserved)} <byte 4561> utiny value {} <byte 4562> {rsvd12[9] (F0-FD Reserved)} <byte 4562> utiny value {} <byte 4563> {rsvd12[8] (F0-FD Reserved)} <byte 4563> utiny value {} <byte 4564> {glue_major_rev (FF Glue Major Revision)} <byte 4564> utiny value {} <byte 4565> {glue_minor_rev (FE Glue Minor Revision)} <byte 4565> utiny value {} <byte 4566> {rsvd12[13] (F0-FD Reserved)} <byte 4566> utiny value {} <byte 4567> {rsvd12[12] (F0-FD Reserved)} <byte 4567> utiny value {} {} <byte 4568> do_not_display[768] union_pad Union Element Padding (DO NOT DISPLAY!) endunion csr Glue CSR Registers {} <byte 5336> {sprite (Sprite register save area)} <byte 5336> union csr Sprite CSR Registers <byte 5336> ulong[256] csra Sprite CSR Registers As Longwords or csr Sprite CSR Registers <byte 5336> {csrfield (Sprite CSR Registers By Field)} <byte 5336> union pc_cba 000 ppc chip base address <byte 5336> {field (By field)} <byte 5336> lbits:4 rev R Revision of Sprite lbits:4 rsvd R Reserved lbits:1 dimm_swap_cs R/W Swap DIMM Chip Select Signals

lbits:23 reg_base_addr R/W Register Base Address {} or pc_cba 000 ppc chip base address <byte 5336> ulong value As longword endunion pc_cba 000 ppc chip base address <byte 5340> union pc_m0_a 004 ppc to DDR memory window 0 description <byte 5340> {field (By field)} <byte 5340> lbits:12 ddr_addr R/W DDR base address, bits 35:xx lbits:2 rsvd R Reserved lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit lbits:8 size R/W Window size, 16MB -> 2GB lbits:8 base_addr R/W Sets bits 31:24 of base address {} or pc_m0_a 004 ppc to DDR memory window 0 description <byte 5340> ulong value As longword endunion pc_m0_a 004 ppc to DDR memory window 0 description <byte 5344> union pc_m1_a 008 ppc to DDR memory window 1 description <byte 5344> {field (By field)} <byte 5344> lbits:12 ddr_addr R/W DDR base address, bits 35:xx lbits:2 rsvd R Reserved lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit lbits:8 size R/W Window size, 16MB -> 2GB lbits:8 base_addr R/W Sets bits 31:24 of base address {} or pc_m1_a 008 ppc to DDR memory window 1 description <byte 5344> ulong value As longword endunion pc_m1_a 008 ppc to DDR memory window 1 description <byte 5348> union pc_m2_a 00c ppc to DDR memory window 2 description <byte 5348> {field (By field)} <byte 5348> lbits:12 ddr_addr R/W DDR base address, bits 35:xx lbits:2 rsvd R Reserved lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit lbits:8 size R/W Window size, 16MB -> 2GB lbits:8 base_addr R/W Sets bits 31:24 of base address {} or pc_m2_a 00c ppc to DDR memory window 2 description <byte 5348> ulong value As longword endunion pc_m2_a 00c ppc to DDR memory window 2 description <byte 5352> union pc_m3_a 010 ppc to DDR memory window 3 description <byte 5352> {field (By field)} <byte 5352> lbits:12 ddr_addr R/W DDR base address, bits 35:xx lbits:2 rsvd R Reserved lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit lbits:8 size R/W Window size, 16MB -> 2GB

Value Preserved

Value Preserved

Value Preserved

Value Preserved

lbits:8 base_addr R/W Sets bits 31:24 of base address {} or pc_m3_a 010 ppc to DDR memory window 3 description <byte 5352> ulong value As longword endunion pc_m3_a 010 ppc to DDR memory window 3 description <byte 5356> union pc_p0_a 014 ppc to PCIX0 memory space window description <byte 5356> {field (By field)} <byte 5356> lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved lbits:2 rsvd1 R Reserved lbits:12 size R/W Window size, 1MB -> 2GB lbits:4 rsvd R Reserved lbits:12 base_addr R/W Sets bits 31:20 of base address {} or pc_p0_a 014 ppc to PCIX0 memory space window description <byte 5356> ulong value As longword endunion pc_p0_a 014 ppc to PCIX0 memory space window description <byte 5360> {pc_p0_ua (018 ppc to PCIX0 upper address)} <byte 5360> ulong value {} <byte 5364> union pc_p1_a 01c ppc to PCIX1 memory space window description <byte 5364> {field (By field)} <byte 5364> lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved lbits:2 rsvd1 R Reserved lbits:12 size R/W Window size, 1MB -> 2GB lbits:4 rsvd R Reserved lbits:12 base_addr R/W Sets bits 31:20 of base address {} or pc_p1_a 01c ppc to PCIX1 memory space window description <byte 5364> ulong value As longword endunion pc_p1_a 01c ppc to PCIX1 memory space window description <byte 5368> {pc_p1_ua (020 ppc to PCIX1 upper address)} <byte 5368> ulong value {} <byte 5372> union pc_io_a 024 ppc lower IO address description <byte 5372> {field (By field)} <byte 5372> lbits:1 pcix_bus R/W 0 = PCIX0, 1 = PCIX1 lbits:1 rsvd R Reserved lbits:30 base_addr R/W Sets bits 31:02 of base address {} or pc_io_a 024 ppc lower IO address description <byte 5372> ulong value As longword endunion pc_io_a 024 ppc lower IO address description <byte 5376>

union pc_dls 028 mirror data has left sprite counter <byte 5376> {field (By field)} <byte 5376> lbits:16 count R/WTI Count of writes to this reg. lbits:16 rsvd R Reserved {} or pc_dls 028 mirror data has left sprite counter <byte 5376> ulong value As longword endunion pc_dls 028 mirror data has left sprite counter <byte 5380> union pc_cfg_add 02c ppc configuration address phase description <byte 5380> {field (By field)} <byte 5380> lbits:1 pcix_bus R/W 0 = PCIX0, 1 = PCIX1 lbits:1 rsvd1 R Reserved lbits:6 Register R/W Register Number lbits:3 Function R/W Function Number lbits:5 device R/W Device Number lbits:8 bus R/W Bus Number lbits:8 rsvd R Reserved {} or pc_cfg_add 02c ppc configuration address phase description <byte 5380> ulong value As longword endunion pc_cfg_add 02c ppc configuration address phase description <byte 5384> union pc_wtt 030 ppc watchdog transfer timeout <byte 5384> {field (By field)} <byte 5384> lbits:19 wd_lo R Lower Bits of Count Value lbits:8 wd_hi R/W Programmable Extra Count Value lbits:4 rsvd R Reserved lbits:1 wd_ena R/W Watchdog Enable {} or pc_wtt 030 ppc watchdog transfer timeout <byte 5384> ulong value As longword endunion pc_wtt 030 ppc watchdog transfer timeout <byte 5388> union pc_tt 034 ppc transfer timeout <byte 5388> {field (By field)} <byte 5388> lbits:16 ttcounter R/W Transfer Timeout Counter lbits:16 rsvd R Reserved {} or pc_tt 034 ppc transfer timeout <byte 5388> ulong value As longword endunion pc_tt 034 ppc transfer timeout <byte 5392> union pc_csr 038 ppc control and status <byte 5392> {field (By field)} <byte 5392> lbits:1 esum_ddr_me R/CLL DDR Memory Error Summary

lbits:1 esum_mir_me R/CLL Mirror Memory Error Summary lbits:1 esum_xor_dma R/CLL XOR-DMA Error Summary lbits:1 esum_que R/CLL Queue Error Summary lbits:1 esum_pcix1 R/CLL PCIX1 Error Summary lbits:1 esum_pcix0 R/CLL PCIX0 Error Summary lbits:1 err_pcixae R/W1C PCIX Access Error lbits:1 err_qrdpe R/W1C Queue Read Data Parity Error lbits:1 err_ppcttoe R/W1C PowerPC Transfer TimeOut Error lbits:1 err_ppcae R/W1C PowerPC Alignment Error lbits:1 err_ppcwdpe R/W1C PowerPC Write Data Parity Err lbits:1 err_ppcape R/W1C PowerPC Address Parity Error lbits:1 err_ppclee R/W1C PowerPC Last Entry Error lbits:1 err_ppc2pcixtoe R/W1C PowerPC-PCIX Transfer Timeout lbits:1 ena_pcixae R/W Enable PCIX Access Error lbits:1 ena_qrdpe R/W Enable Queue Rd Data Parity Er lbits:1 ena_ppcttoe R/W Enable PPC Transfer T.O. Error lbits:1 ena_ppcae R/W Enable PPC Alignment Error lbits:1 ena_ppcwdpe R/W Enable PPC Wrt Data Parity Err lbits:1 ena_ppcape R/W Enable PPC Address Parity Err lbits:1 ena_ppclee R/W Enable PPC Last Entry Error lbits:1 ena_ppc2pcixtoe R/W Enable PPC-PCIX Transfer T.O. lbits:1 ena_p_int1 R/W Ena PPC errs on INT1_L to Glue lbits:1 ena_p_int0 R/W Ena PPC errs on INT0_L to Glue lbits:1 sel_pcixae R/W Select P_INT(0/1)_L for pcixae lbits:1 sel_qrddpe R/W Select P_INT(0/1)_L for qrddpe lbits:1 sel_ppcttoe R/W Select P_INT(0/1)_L for ppcttoe lbits:1 sel_ppcae R/W Select P_INT(0/1)_L for ppcae lbits:1 sel_ppcwdpe R/W Select P_INT(0/1)_L for ppcwdpe lbits:1 sel_ppcape R/W Select P_INT(0/1)_L for ppcape lbits:1 sel_ppclee R/W Select P_INT(0/1)_L for ppclee lbits:1 sel_ppc2pcixtoe R/W Sel P_INT(0/1)_L 4 ppc2pcixtoe {} or pc_csr 038 ppc control and status <byte 5392> ulong value As longword endunion pc_csr 038 ppc control and status <byte 5396> union pc_err 03c ppc error status <byte 5396> {field (By field)} <byte 5396> lbits:1 hlt_mirror R/W Halt Mirror Block lbits:1 hlt_pcix1 R/W Halt PCIX 1 Block lbits:1 hlt_pcix0 R/W Halt PCIX 0 Block lbits:1 hlt_queue R/W Halt Queue Block lbits:1 hlt_ddrm R/W Halt DDR Memory Block lbits:1 hlt_dma R/W Halt DMA Block lbits:1 ena_tea R/W Enable Transfer Err Ack (TEA) lbits:1 rsvd1 R Reserved lbits:1 chk_even_ap R/W Set to Check Even Addr Parity lbits:1 chk_even_wrp R/W Set to Check Even WR Parity lbits:1 chk_even_rdp R/W Set to Check Even RD Parity lbits:1 gen_even_wrp R/W Set to Generate Even WR Parity lbits:1 gen_even_rdp R/W Set to Generate Even RD Parity lbits:1 ppc_mode R/W PowerPC Mode (1=7450 / 0=other) lbits:1 clr_hltd_mirror R/W Clear Mirror Halted Condition lbits:1 clr_hltd_pcix1 R/W Clear PCIX 1 Halted Condition lbits:1 clr_hltd_pcix0 R/W Clear PCIX 0 Halted Condition lbits:1 clr_hltd_ddq R/W Clear dma,ddrm,queue Halt Cond. lbits:8 rsvd R Reserved

lbits:1 hltd_mirror R Mirror Halted lbits:1 hltd_pcix1 R PCIX 1 Halted lbits:1 hltd_pcix0 R PCIX 0 Halted lbits:1 hltd_queue R Queue Halted lbits:1 hltd_ddrm R DDR Memory Halted lbits:1 hltd_dma R DMA Halted {} or pc_err 03c ppc error status <byte 5396> ulong value As longword endunion pc_err 03c ppc error status <byte 5400> {pc_io_data (040 ppc IO data (not configured; do not read))} <byte 5400> ulong value {} <byte 5404> {pc_cfg_data (044 ppc configuration data)} <byte 5404> ulong value {} <byte 5408> {pc_addr (048 ppc error address)} <byte 5408> ulong value {} <byte 5412> {pc_rev (04c sprite3 hardware build revision)} <byte 5412> ulong value {} <byte 5416> union pc_gen 050 sprite3 gpio control <byte 5416> {field (By field)} <byte 5416> lbits:1 gbic_amb0_l R/W GBIC Amber LED0 (flashing=1) lbits:1 gbic_amb1_l R/W GBIC Amber LED1 (flashing=1) lbits:1 gbic_amb2_l R/W GBIC Amber LED2 (flashing=1) lbits:1 gbic_amb3_l R/W GBIC Amber LED3 (flashing=1) lbits:1 gbic_amb4_l R/W GBIC Amber LED4 (flashing=1) lbits:1 gbic_amb5_l R/W GBIC Amber LED5 (flashing=1) lbits:1 gbic_amb6_l R/W GBIC Amber LED6 (flashing=1) lbits:1 gbic_amb7_l R/W GBIC Amber LED7 (flashing=1) lbits:1 gbic_amb8_l R/W GBIC Amber LED8 (flashing=1) lbits:1 gbic_amb9_l R/W GBIC Amber LED9 (flashing=1) lbits:1 sfp_dis_0 R/W SFP Laser 0 Disable (dis=1) lbits:1 sfp_dis_1 R/W SFP Laser 1 Disable (dis=1) lbits:1 sfp_dis_2 R/W SFP Laser 2 Disable (dis=1) lbits:1 sfp_dis_3 R/W SFP Laser 3 Disable (dis=1) lbits:1 sfp_dis_4 R/W SFP Laser 4 Disable (dis=1) lbits:1 sfp_dis_5 R/W SFP Laser 5 Disable (dis=1) lbits:1 sfp_dis_6 R/W SFP Laser 6 Disable (dis=1) lbits:1 sfp_dis_7 R/W SFP Laser 7 Disable (dis=1) lbits:1 sfp_dis_8 R/W SFP Laser 8 Disable (dis=1) lbits:1 sfp_dis_9 R/W SFP Laser 9 Disable (dis=1) lbits:1 sfp_dis_10 R/W SFP Laser 10 Disable (dis=1) lbits:1 sfp_dis_11 R/W SFP Laser 11 Disable (dis=1) lbits:1 gbic_amb10_l R/W GBIC Amber LED10 (flashing=1) lbits:1 gbic_amb11_l R/W GBIC Amber LED11 (flashing=1)

lbits:2 rsvd1 R/W Reserved 3.3V LVTTL lbits:6 rsvd R/W Reserved 2.5V CMOS {} or pc_gen 050 sprite3 gpio control <byte 5416> ulong value As longword endunion pc_gen 050 sprite3 gpio control <byte 5420> union pc_pll 054 sprite3 pll config <byte 5420> {field (By field)} <byte 5420> lbits:2 pll_phase_m_cnt R/W PLL phase shift for m counter lbits:2 pll_phase_c0 R/W PLL phase shift for clock C0 lbits:2 pll_phase_c1 R/W PLL phase shift for clock C1 lbits:2 pll_phase_c2 R/W PLL phase shift for clock C2 lbits:2 pll_phase_c3 R/W PLL phase shift for clock C3 lbits:2 pll_phase_c4 R/W PLL phase shift for clock C4 lbits:2 pll_phase_c5 R/W PLL phase shift for clock C5 lbits:1 rsvd1 R/W Reserved lbits:1 e_scan_done_ck R/W Enable scan done check lbits:7 pll_delay_parms R/W PLL delay parameters lbits:8 rsvd R/W Reserved lbits:1 pll_recon_w_e R/W PLL reconfig write enable {} or pc_pll 054 sprite3 pll config <byte 5420> ulong value As longword endunion pc_pll 054 sprite3 pll config <byte 5424> {ep_data (058 sprite3+ and sprite4 EEPROM reload data register)} <byte 5424> ulong value R/W EEPROM DATA {} <byte 5428> union ep_ctl 05c sprite3+ and sprite4 EEPROM reload control register <byte 5428> {field (By field)} <byte 5428> lbits:1 start_write R/W 1 = EEPROM Being written 0 = EEPROM was written lbits:1 start_read R/W 1 = EEPROM Being read 0 = EEPROM was read lbits:1 bulk_erase R/W 1 = EEPROM Being erased 0 = EEPROM was erased lbits:1 silicon_id_read R/W 1 = EEPROM ID Being read 0 = EEPROM ID read lbits:1 write_data_ready R 1 = EPA_DATA ready to be written 0 = EPA_DATA no new value lbits:1 read_data_ready R 1 = EPA_DATA ready to be read 0 = EPA_DATA now new v alue lbits:1 silicon_id_ready R Silicon ID placed in the lower bits of the EPA_DATA register lbits:1 reserved R Reserved lbits:24 eeprom_addr R Default value is 0 {} or ep_ctl 05c sprite3+ and sprite4 EEPROM reload control register <byte 5428> ulong value As longword endunion ep_ctl 05c sprite3+ and sprite4 EEPROM reload control register <byte 5432> union p0_mem_0 060 pcix0 to DDR window 0 description <byte 5432> {field (By field)}

<byte 5432> lbits:12 size R/W Window size, 32MB -> 32GB lbits:20 base_addr R/W Sets bits 45:25 of base address {} or p0_mem_0 060 pcix0 to DDR window 0 description <byte 5432> ulong value As longword endunion p0_mem_0 060 pcix0 to DDR window 0 description <byte 5436> union p0_sel_tra_0 064 pcix0 to DDR window 0 select address translation bits <byte 5436> {field (By field)} <byte 5436> lbits:12 rsvd R Reserved lbits:20 trans_sel R/W Selects Translation bits 45:25 {} or p0_sel_tra_0 064 pcix0 to DDR window 0 select address translation bits <byte 5436> ulong value As longword endunion p0_sel_tra_0 064 pcix0 to DDR window 0 select address translation bits <byte 5440> union p0_tra_0 068 pcix0 to DDR window 0 address translation value <byte 5440> {field (By field)} <byte 5440> lbits:12 rsvd R Reserved lbits:20 trans_val R/W Translation Value, bits 45:25 {} or p0_tra_0 068 pcix0 to DDR window 0 address translation value <byte 5440> ulong value As longword endunion p0_tra_0 068 pcix0 to DDR window 0 address translation value <byte 5444> union p0_mem_1 06c pcix0 to DDR window 1 description <byte 5444> {field (By field)} <byte 5444> lbits:12 size R/W Window size, 32MB -> 32GB lbits:20 base_addr R/W Sets bits 45:25 of base address {} or p0_mem_1 06c pcix0 to DDR window 1 description <byte 5444> ulong value As longword endunion p0_mem_1 06c pcix0 to DDR window 1 description <byte 5448> union p0_sel_tra_1 070 pcix0 to DDR window 1 select address translation bits <byte 5448> {field (By field)} <byte 5448> lbits:12 rsvd R Reserved lbits:20 trans_sel R/W Selects Translation bits 45:25 {} or p0_sel_tra_1 070 pcix0 to DDR window 1 select address translation bits <byte 5448> ulong value As longword endunion p0_sel_tra_1 070 pcix0 to DDR window 1 select address translation bits <byte 5452> union p0_tra_1 074 pcix0 to DDR window 1 address translation value <byte 5452> {field (By field)}

<byte 5452> lbits:12 rsvd R Reserved lbits:20 trans_val R/W Translation Value, bits 45:25 {} or p0_tra_1 074 pcix0 to DDR window 1 address translation value <byte 5452> ulong value As longword endunion p0_tra_1 074 pcix0 to DDR window 1 address translation value <byte 5456> union p0_csr 078 pcix0 control and status <byte 5456> {field (By field)} <byte 5456> lbits:1 err_mabort R/W1C Sprite performed a Master Abort lbits:1 err_tabort R/W1C Sprite received a Target Abort lbits:1 err_sa_serr R/W1C Sprite asserted SERR lbits:1 err_sd_serr R/W1C Sprite detected SERR lbits:1 err_perr R/W1C PERR asserted lbits:1 err_scit R/W1C SC Invalid Termination PCIX Errors: lbits:1 err_uesc R/W1C UnExpected SC lbits:1 err_scemr R/W1C SC Error Message or SC Received lbits:1 err_irce R/W1C Initiator Retry-Count Exceeded Split-Completion (SC) Erro rs: lbits:1 err_trce R/W1C Target Retry-Count Exceeded lbits:1 err_bcmm R/W1C Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) S prite Retry-Counts Exceeded: lbits:1 err_terpe R/W1C Transaction Entry RD Parity Err lbits:1 err_tlmm R/W1C Transaction Length MisMatch lbits:1 err_scce R/W1C Split-Completion Count Exceeded lbits:1 rsvd R Reserved lbits:1 err_nbofisd R/W1C No Beginning-Of-Frame or Invalid Single Destination lbits:1 sel_mabort R/W Select P_INT(0/1)_L for mabort lbits:1 sel_tabort R/W Select P_INT(0/1)_L for tabort lbits:1 sel_sa_serr R/W Select P_INT(0/1)_L for sa_serr lbits:1 sel_sd_serr R/W Select P_INT(0/1)_L for sd_serr lbits:1 sel_perr R/W Select P_INT(0/1)_L for perr lbits:1 sel_scit R/W Select P_INT(0/1)_L for scit lbits:1 sel_uesc R/W Select P_INT(0/1)_L for uesc lbits:1 sel_scemr R/W Select P_INT(0/1)_L for scemr lbits:1 sel_irce R/W Select P_INT(0/1)_L for irce lbits:1 sel_trce R/W Select P_INT(0/1)_L for trce lbits:1 sel_bcmm R/W Select P_INT(0/1)_L for bcmm lbits:1 sel_terpe R/W Select P_INT(0/1)_L for terpe lbits:1 sel_tlmm R/W Select P_INT(0/1)_L for tlmm lbits:1 sel_scce R/W Select P_INT(0/1)_L for scce lbits:1 sel_bt32bm R/W Select P_INT(0/1)_L for bt32bm lbits:1 sel_nbofisd R/W Select P_INT(0/1)_L for nbofisd {} or p0_csr 078 pcix0 control and status <byte 5456> ulong value As longword endunion p0_csr 078 pcix0 control and status <byte 5460> union p0_ecr 07c pcix0 error counters <byte 5460> {field (By field)} <byte 5460> lbits:12 sc_delay R/W Split-Completion Delay lbits:10 i_retries R/W Initiator Retry Count lbits:10 t_retries R/W Target Retry Count (N/A Mirror)

{} or p0_ecr 07c pcix0 error counters <byte 5460> ulong value As longword endunion p0_ecr 07c pcix0 error counters <byte 5464> union p0_edr 080 pcix0 error disables <byte 5464> {field (By field)} <byte 5464> lbits:1 dis_mabort R/W Sprite performed a Master Abort lbits:1 dis_tabort R/W Sprite received a Target Abort lbits:1 dis_sa_serr R/W Sprite asserted SERR lbits:1 dis_sd_serr R/W Sprite detected SERR lbits:1 dis_perr R/W PERR asserted lbits:1 dis_scit R/W SC Invalid Termination PCIX Errors: lbits:1 dis_uesc R/W UnExpected SC lbits:1 dis_scemr R/W SC Error Message or SC Received lbits:1 dis_irce R/W Initiator Retry-Count Exceeded Split-Completion (SC) Erro rs: lbits:1 dis_trce R/W Target Retry-Count Exceeded lbits:1 dis_bcmm R/W Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) S prite Retry-Counts Exceeded: lbits:1 dis_terpe R/W Transaction Entry RD Parity Err lbits:1 dis_tlmm R/W Transaction Length MisMatch lbits:1 dis_scce R/W Split-Completion Count Exceeded lbits:1 rsvd1 R Reserved lbits:1 dis_nbofisd R/W No Beginning-Of-Frame or Invalid Single Destination lbits:1 dis_scwopsr R/W Split-Completion without a previous Split-Response lbits:13 rsvd R Reserved DISABLE interrupts from: lbits:1 ignore_mir_bad R/W Sprite ignores err_mir_bad bit (rsvd in p0_csr & p1 _csr) lbits:1 ena_perr_serr R/W Enable PERR and SERR {} or p0_edr 080 pcix0 error disables <byte 5464> ulong value As longword endunion p0_edr 080 pcix0 error disables <byte 5468> union p0_pcix_atr 084 pcix0 attributes <byte 5468> {field (By field)} <byte 5468> lbits:8 rsvd1 R Reserved lbits:3 function R/W Transaction Function Number lbits:5 device R/W Transaction Device Number lbits:8 bus R/W Transaction Bus Number lbits:5 tag R/W Transaction Tag Number lbits:3 rsvd R Reserved {} or p0_pcix_atr 084 pcix0 attributes <byte 5468> ulong value As longword endunion p0_pcix_atr 084 pcix0 attributes <byte 5472> union p0_csr2 088 pcix0 control and status continued <byte 5472> {field (By field previous Split-Response)} <byte 5472> lbits:1 err_scwopsr R/W1C Split-Completion without a

lbits:14 rsvd1 R Reserved lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK (rsvd in p0_csr & p1_csr) lbits:1 sel_scwopsr R/W Select P_INT(0/1)_L for scnosr lbits:14 rsvd R Reserved lbits:1 sel_mir_bad R/W Sprite P_INT(0/1)_L for scnosr (rsvd in p0_csr & p1_cs r) {} or p0_csr2 088 pcix0 control and status continued <byte 5472> ulong value As longword endunion p0_csr2 088 pcix0 control and status continued <byte 5476> {rsvd3[0] (08c - 09c unused)} <byte 5476> ulong value {} <byte 5480> {rsvd3[1] (08c - 09c unused)} <byte 5480> ulong value {} <byte 5484> {rsvd3[2] (08c - 09c unused)} <byte 5484> ulong value {} <byte 5488> {rsvd3[3] (08c - 09c unused)} <byte 5488> ulong value {} <byte 5492> {rsvd3[4] (08c - 09c unused)} <byte 5492> ulong value {} <byte 5496> union p1_mem_0 0a0 pcix1 to DDR window 0 description <byte 5496> {field (By field)} <byte 5496> lbits:12 size R/W Window size, 32MB -> 32GB lbits:20 base_addr R/W Sets bits 45:25 of base address {} or p1_mem_0 0a0 pcix1 to DDR window 0 description <byte 5496> ulong value As longword endunion p1_mem_0 0a0 pcix1 to DDR window 0 description <byte 5500> union p1_sel_tra_0 0a4 pcix1 to DDR window 0 select address translation bits <byte 5500> {field (By field)} <byte 5500> lbits:12 rsvd R Reserved lbits:20 trans_sel R/W Selects Translation bits 45:25 {} or p1_sel_tra_0 0a4 pcix1 to DDR window 0 select address translation bits <byte 5500> ulong value As longword endunion p1_sel_tra_0 0a4 pcix1 to DDR window 0 select address translation bits

<byte 5504> union p1_tra_0 0a8 pcix1 to DDR window 0 address translation value <byte 5504> {field (By field)} <byte 5504> lbits:12 rsvd R Reserved lbits:20 trans_val R/W Translation Value, bits 45:25 {} or p1_tra_0 0a8 pcix1 to DDR window 0 address translation value <byte 5504> ulong value As longword endunion p1_tra_0 0a8 pcix1 to DDR window 0 address translation value <byte 5508> union p1_mem_1 0ac pcix1 to DDR window 1 description <byte 5508> {field (By field)} <byte 5508> lbits:12 size R/W Window size, 32MB -> 32GB lbits:20 base_addr R/W Sets bits 45:25 of base address {} or p1_mem_1 0ac pcix1 to DDR window 1 description <byte 5508> ulong value As longword endunion p1_mem_1 0ac pcix1 to DDR window 1 description <byte 5512> union p1_sel_tra_1 0b0 pcix1 to DDR window 1 select address translation bits <byte 5512> {field (By field)} <byte 5512> lbits:12 rsvd R Reserved lbits:20 trans_sel R/W Selects Translation bits 45:25 {} or p1_sel_tra_1 0b0 pcix1 to DDR window 1 select address translation bits <byte 5512> ulong value As longword endunion p1_sel_tra_1 0b0 pcix1 to DDR window 1 select address translation bits <byte 5516> union p1_tra_1 0b4 pcix1 to DDR window 1 address translation value <byte 5516> {field (By field)} <byte 5516> lbits:12 rsvd R Reserved lbits:20 trans_val R/W Translation Value, bits 45:25 {} or p1_tra_1 0b4 pcix1 to DDR window 1 address translation value <byte 5516> ulong value As longword endunion p1_tra_1 0b4 pcix1 to DDR window 1 address translation value <byte 5520> union p1_csr 0b8 pcix1 control and status <byte 5520> {field (By field)} <byte 5520> lbits:1 err_mabort R/W1C Sprite performed a Master Abort lbits:1 err_tabort R/W1C Sprite received a Target Abort lbits:1 err_sa_serr R/W1C Sprite asserted SERR lbits:1 err_sd_serr R/W1C Sprite detected SERR lbits:1 err_perr R/W1C PERR asserted lbits:1 err_scit R/W1C SC Invalid Termination PCIX Errors: lbits:1 err_uesc R/W1C UnExpected SC

lbits:1 err_scemr R/W1C SC Error Message or SC Received lbits:1 err_irce R/W1C Initiator Retry-Count Exceeded Split-Completion (SC) Erro rs: lbits:1 err_trce R/W1C Target Retry-Count Exceeded lbits:1 err_bcmm R/W1C Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) S prite Retry-Counts Exceeded: lbits:1 err_terpe R/W1C Transaction Entry RD Parity Err lbits:1 err_tlmm R/W1C Transaction Length MisMatch lbits:1 err_scce R/W1C Split-Completion Count Exceeded lbits:1 rsvd R Reserved lbits:1 err_nbofisd R/W1C No Beginning-Of-Frame or Invalid Single Destination lbits:1 sel_mabort R/W Select P_INT(0/1)_L for mabort lbits:1 sel_tabort R/W Select P_INT(0/1)_L for tabort lbits:1 sel_sa_serr R/W Select P_INT(0/1)_L for sa_serr lbits:1 sel_sd_serr R/W Select P_INT(0/1)_L for sd_serr lbits:1 sel_perr R/W Select P_INT(0/1)_L for perr lbits:1 sel_scit R/W Select P_INT(0/1)_L for scit lbits:1 sel_uesc R/W Select P_INT(0/1)_L for uesc lbits:1 sel_scemr R/W Select P_INT(0/1)_L for scemr lbits:1 sel_irce R/W Select P_INT(0/1)_L for irce lbits:1 sel_trce R/W Select P_INT(0/1)_L for trce lbits:1 sel_bcmm R/W Select P_INT(0/1)_L for bcmm lbits:1 sel_terpe R/W Select P_INT(0/1)_L for terpe lbits:1 sel_tlmm R/W Select P_INT(0/1)_L for tlmm lbits:1 sel_scce R/W Select P_INT(0/1)_L for scce lbits:1 sel_bt32bm R/W Select P_INT(0/1)_L for bt32bm lbits:1 sel_nbofisd R/W Select P_INT(0/1)_L for nbofisd {} or p1_csr 0b8 pcix1 control and status <byte 5520> ulong value As longword endunion p1_csr 0b8 pcix1 control and status <byte 5524> union p1_ecr 0bc pcix1 error counters <byte 5524> {field (By field)} <byte 5524> lbits:12 sc_delay R/W Split-Completion Delay lbits:10 i_retries R/W Initiator Retry Count lbits:10 t_retries R/W Target Retry Count (N/A Mirror) {} or p1_ecr 0bc pcix1 error counters <byte 5524> ulong value As longword endunion p1_ecr 0bc pcix1 error counters <byte 5528> union p1_edr 0c0 pcix1 error disables <byte 5528> {field (By field)} <byte 5528> lbits:1 dis_mabort R/W Sprite performed a Master Abort lbits:1 dis_tabort R/W Sprite received a Target Abort lbits:1 dis_sa_serr R/W Sprite asserted SERR lbits:1 dis_sd_serr R/W Sprite detected SERR lbits:1 dis_perr R/W PERR asserted lbits:1 dis_scit R/W SC Invalid Termination PCIX Errors: lbits:1 dis_uesc R/W UnExpected SC lbits:1 dis_scemr R/W SC Error Message or SC Received lbits:1 dis_irce R/W Initiator Retry-Count Exceeded Split-Completion (SC) Erro rs:

lbits:1 dis_trce R/W Target Retry-Count Exceeded lbits:1 dis_bcmm R/W Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) S prite Retry-Counts Exceeded: lbits:1 dis_terpe R/W Transaction Entry RD Parity Err lbits:1 dis_tlmm R/W Transaction Length MisMatch lbits:1 dis_scce R/W Split-Completion Count Exceeded lbits:1 rsvd1 R Reserved lbits:1 dis_nbofisd R/W No Beginning-Of-Frame or Invalid Single Destination lbits:1 dis_scwopsr R/W Split-Completion without a previous Split-Response lbits:13 rsvd R Reserved DISABLE interrupts from: lbits:1 ignore_mir_bad R/W Sprite ignores err_mir_bad bit (rsvd in p0_csr & p1 _csr) lbits:1 ena_perr_serr R/W Enable PERR and SERR {} or p1_edr 0c0 pcix1 error disables <byte 5528> ulong value As longword endunion p1_edr 0c0 pcix1 error disables <byte 5532> union p1_pcix_atr 0c4 pcix1 attributes <byte 5532> {field (By field)} <byte 5532> lbits:8 rsvd1 R Reserved lbits:3 function R/W Transaction Function Number lbits:5 device R/W Transaction Device Number lbits:8 bus R/W Transaction Bus Number lbits:5 tag R/W Transaction Tag Number lbits:3 rsvd R Reserved {} or p1_pcix_atr 0c4 pcix1 attributes <byte 5532> ulong value As longword endunion p1_pcix_atr 0c4 pcix1 attributes <byte 5536> union p1_csr2 0c8 pcix1 control and status continued <byte 5536> {field (By field previous Split-Response)} <byte 5536> lbits:1 err_scwopsr R/W1C Split-Completion without a lbits:14 rsvd1 R Reserved lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK (rsvd in p0_csr & p1_csr) lbits:1 sel_scwopsr R/W Select P_INT(0/1)_L for scnosr lbits:14 rsvd R Reserved lbits:1 sel_mir_bad R/W Sprite P_INT(0/1)_L for scnosr (rsvd in p0_csr & p1_cs r) {} or p1_csr2 0c8 pcix1 control and status continued <byte 5536> ulong value As longword endunion p1_csr2 0c8 pcix1 control and status continued <byte 5540> {rsvd4[0] (0cc - 0dc unused)} <byte 5540> ulong value {} <byte 5544> {rsvd4[1] (0cc - 0dc unused)} <byte 5544> ulong value

{} <byte 5548> {rsvd4[2] (0cc - 0dc unused)} <byte 5548> ulong value {} <byte 5552> {rsvd4[3] (0cc - 0dc unused)} <byte 5552> ulong value {} <byte 5556> {rsvd4[4] (0cc - 0dc unused)} <byte 5556> ulong value {} <byte 5560> union q_mir 0e0 mirror window description <byte 5560> {field (By field)} <byte 5560> lbits:12 size R/W Window size, 32MB -> 32GB lbits:9 rsvd R Reserved lbits:11 base_addr R/W Sets bits 35:25 of base address {} or q_mir 0e0 mirror window description <byte 5560> ulong value As longword endunion q_mir 0e0 mirror window description <byte 5564> union q_wsb 0e4 write sensitive base <byte 5564> {field (By field)} <byte 5564> lbits:1 ena_perf_int R/W Enable Performance Interrupt lbits:31 base_addr R/W Sets bits 35:5 of base address {} or q_wsb 0e4 write sensitive base <byte 5564> ulong value As longword endunion q_wsb 0e4 write sensitive base <byte 5568> union q_pint 0e8 performance interrupt <byte 5568> {field (By field)} <byte 5568> lbits:1 wsa000 R/W1C Write Sensitive Area 0x000 lbits:1 wsa020 R/W1C Write Sensitive Area 0x020 lbits:1 wsa040 R/W1C Write Sensitive Area 0x040 lbits:1 wsa060 R/W1C Write Sensitive Area 0x060 lbits:1 wsa080 R/W1C Write Sensitive Area 0x080 lbits:1 wsa0A0 R/W1C Write Sensitive Area 0x0A0 lbits:1 wsa0C0 R/W1C Write Sensitive Area 0x0C0 lbits:1 wsa0E0 R/W1C Write Sensitive Area 0x0E0 lbits:1 wsa100 R/W1C Write Sensitive Area 0x100 lbits:1 wsa120 R/W1C Write Sensitive Area 0x120 lbits:1 wsa140 R/W1C Write Sensitive Area 0x140 lbits:1 wsa160 R/W1C Write Sensitive Area 0x160 lbits:1 wsa180 R/W1C Write Sensitive Area 0x180 lbits:1 wsa1A0 R/W1C Write Sensitive Area 0x1A0

lbits:1 wsa1C0 R/W1C Write Sensitive Area 0x1C0 lbits:1 wsa1E0 R/W1C Write Sensitive Area 0x1E0 lbits:1 wsa200 R/W1C Write Sensitive Area 0x200 lbits:1 wsa220 R/W1C Write Sensitive Area 0x220 lbits:1 wsa240 R/W1C Write Sensitive Area 0x240 lbits:1 wsa260 R/W1C Write Sensitive Area 0x260 lbits:1 wsa280 R/W1C Write Sensitive Area 0x280 lbits:1 wsa2A0 R/W1C Write Sensitive Area 0x2A0 lbits:1 wsa2C0 R/W1C Write Sensitive Area 0x2C0 lbits:1 wsa2E0 R/W1C Write Sensitive Area 0x2E0 lbits:1 wsa300 R/W1C Write Sensitive Area 0x300 lbits:1 wsa320 R/W1C Write Sensitive Area 0x320 lbits:1 wsa340 R/W1C Write Sensitive Area 0x340 lbits:1 wrt_mir_dls R/W1C Write to Mirror Data has Left Sprite register lbits:1 dma_cmp_err R/W1C XOR-DMA Compare Error lbits:1 dma_complete R/W1C XOR-DMA Operation Completed lbits:1 int1 R/W1C INT_IN_1_L is asserted lbits:1 int0 R/W1C INT_IN_0_L is asserted {} or q_pint 0e8 performance interrupt <byte 5568> ulong value As longword endunion q_pint 0e8 performance interrupt <byte 5572> union q_csr 0ec queue control and status <byte 5572> {field (By field)} <byte 5572> lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK lbits:1 err_qdid R/W1C Queue Detected an Invalid Destination lbits:6 rsvd2 R Reserved lbits:1 ena_mir_bad R/W Enable mir_bad to error & halt lbits:1 ena_qdid R/W Enable qdid to error & halt lbits:6 rsvd1 R Reserved lbits:1 sel_mir_bad R/W Select P_INT(0/1)_L for mir_bad lbits:1 sel_qdid R/W Select P_INT(0/1)_L for qdid lbits:12 rsvd R Reserved lbits:1 gp2ppc_rd R/W Give priority to PowerPC Read transactions lbits:1 max_xfer_len R/W Max. Xfer Length 0=1K, 1=2K {} or q_csr 0ec queue control and status <byte 5572> ulong value As longword endunion q_csr 0ec queue control and status <byte 5576> union q_egen 0f0 error generation <byte 5576> {field (By field)} <byte 5576> lbits:3 pdf R/W Port Detector Field lbits:1 qrice R/W Queue Received an Invalid Command Entry lbits:1 tmpdb R/W Transaction Missing Proper Destination Bit lbits:1 twalanob R/W Transaction With a Low Actual Number of Bytes lbits:1 peifte R/W Parity Error in First Transaction Entry lbits:1 twnleb R/W Transaction With No Last-Entry Bit lbits:1 twnfeb R/W Transaction With No First-Entry Bit lbits:23 rsvd R Reserved {} or q_egen 0f0 error generation <byte 5576>

ulong value As longword endunion q_egen 0f0 error generation <byte 5580> union q_pcix 0f4 pci-x arbitration and bootstrapping - new for sprite3 <byte 5580> {field (By field)} <byte 5580> lbits:2 ctrl1 R/W PCIX0 Arb Control lbits:2 state1 R PCIX0 Arb State lbits:2 ctrl0 R/W PCIX1 Arb Control lbits:2 state0 R PCIX1 Arb State lbits:16 rsvd2 R Reserved lbits:1 pcix1_init_stop_l R/W PCIX1 Initialization value for Stop_l lbits:1 pcix1_init_trdy_l R/W PCIX1 Initialization value for Trdy_l lbits:1 rsvd1 R Reserved lbits:1 pcix1_init_req64_l R/W PCIX1 Initialization value for Req64_l lbits:1 pcix0_init_stop_l R/W PCIX0 Initialization value for Stop_l lbits:1 pcix0_init_trdy_l R/W PCIX0 Initialization value for Trdy_l lbits:1 rsvd R Reserved lbits:1 pcix0_init_req64_l R/W PCIX0 Initialization value for Req64_l {} or q_pcix 0f4 pci-x arbitration and bootstrapping - new for sprite3 <byte 5580> ulong value As longword endunion q_pcix 0f4 pci-x arbitration and bootstrapping - new for sprite3 <byte 5584> {rsvd5[0] (0f8 - 0fc unused)} <byte 5584> ulong value {} <byte 5588> {rsvd5[1] (0f8 - 0fc unused)} <byte 5588> ulong value {} <byte 5592> union mir_csr 100 mirror control and status <byte 5592> {field (By field)} <byte 5592> lbits:1 err_mabort R/W1C Sprite performed a Master Abort lbits:1 err_tabort R/W1C Sprite received a Target Abort lbits:1 err_sa_serr R/W1C Sprite asserted SERR lbits:1 err_sd_serr R/W1C Sprite detected SERR lbits:1 err_perr R/W1C PERR asserted lbits:1 err_scit R/W1C SC Invalid Termination PCIX Errors: lbits:1 err_uesc R/W1C UnExpected SC lbits:1 err_scemr R/W1C SC Error Message or SC Received lbits:1 err_irce R/W1C Initiator Retry-Count Exceeded Split-Completion (SC) Erro rs: lbits:1 err_trce R/W1C Target Retry-Count Exceeded lbits:1 err_bcmm R/W1C Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) S prite Retry-Counts Exceeded: lbits:1 err_terpe R/W1C Transaction Entry RD Parity Err lbits:1 err_tlmm R/W1C Transaction Length MisMatch lbits:1 err_scce R/W1C Split-Completion Count Exceeded lbits:1 rsvd R Reserved lbits:1 err_nbofisd R/W1C No Beginning-Of-Frame or Invalid Single Destination lbits:1 sel_mabort R/W Select P_INT(0/1)_L for mabort lbits:1 sel_tabort R/W Select P_INT(0/1)_L for tabort

lbits:1 sel_sa_serr R/W Select P_INT(0/1)_L for sa_serr lbits:1 sel_sd_serr R/W Select P_INT(0/1)_L for sd_serr lbits:1 sel_perr R/W Select P_INT(0/1)_L for perr lbits:1 sel_scit R/W Select P_INT(0/1)_L for scit lbits:1 sel_uesc R/W Select P_INT(0/1)_L for uesc lbits:1 sel_scemr R/W Select P_INT(0/1)_L for scemr lbits:1 sel_irce R/W Select P_INT(0/1)_L for irce lbits:1 sel_trce R/W Select P_INT(0/1)_L for trce lbits:1 sel_bcmm R/W Select P_INT(0/1)_L for bcmm lbits:1 sel_terpe R/W Select P_INT(0/1)_L for terpe lbits:1 sel_tlmm R/W Select P_INT(0/1)_L for tlmm lbits:1 sel_scce R/W Select P_INT(0/1)_L for scce lbits:1 sel_bt32bm R/W Select P_INT(0/1)_L for bt32bm lbits:1 sel_nbofisd R/W Select P_INT(0/1)_L for nbofisd {} or mir_csr 100 mirror control and status <byte 5592> ulong value As longword endunion mir_csr 100 mirror control and status <byte 5596> union mir_ecr 104 mirror error counters <byte 5596> {field (By field)} <byte 5596> lbits:12 sc_delay R/W Split-Completion Delay lbits:10 i_retries R/W Initiator Retry Count lbits:10 t_retries R/W Target Retry Count (N/A Mirror) {} or mir_ecr 104 mirror error counters <byte 5596> ulong value As longword endunion mir_ecr 104 mirror error counters <byte 5600> union mir_edr 108 mirror error disables <byte 5600> {field (By field)} <byte 5600> lbits:1 dis_mabort R/W Sprite performed a Master Abort lbits:1 dis_tabort R/W Sprite received a Target Abort lbits:1 dis_sa_serr R/W Sprite asserted SERR lbits:1 dis_sd_serr R/W Sprite detected SERR lbits:1 dis_perr R/W PERR asserted lbits:1 dis_scit R/W SC Invalid Termination PCIX Errors: lbits:1 dis_uesc R/W UnExpected SC lbits:1 dis_scemr R/W SC Error Message or SC Received lbits:1 dis_irce R/W Initiator Retry-Count Exceeded Split-Completion (SC) Erro rs: lbits:1 dis_trce R/W Target Retry-Count Exceeded lbits:1 dis_bcmm R/W Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) S prite Retry-Counts Exceeded: lbits:1 dis_terpe R/W Transaction Entry RD Parity Err lbits:1 dis_tlmm R/W Transaction Length MisMatch lbits:1 dis_scce R/W Split-Completion Count Exceeded lbits:1 rsvd1 R Reserved lbits:1 dis_nbofisd R/W No Beginning-Of-Frame or Invalid Single Destination lbits:1 dis_scwopsr R/W Split-Completion without a previous Split-Response lbits:13 rsvd R Reserved DISABLE interrupts from: lbits:1 ignore_mir_bad R/W Sprite ignores err_mir_bad bit (rsvd in p0_csr & p1 _csr) lbits:1 ena_perr_serr R/W Enable PERR and SERR

{} or mir_edr 108 mirror error disables <byte 5600> ulong value As longword endunion mir_edr 108 mirror error disables <byte 5604> union mir_pcix_atr 10c mirror pcix attributes <byte 5604> {field (By field)} <byte 5604> lbits:8 rsvd1 R Reserved lbits:3 function R/W Transaction Function Number lbits:5 device R/W Transaction Device Number lbits:8 bus R/W Transaction Bus Number lbits:5 tag R/W Transaction Tag Number lbits:3 rsvd R Reserved {} or mir_pcix_atr 10c mirror pcix attributes <byte 5604> ulong value As longword endunion mir_pcix_atr 10c mirror pcix attributes <byte 5608> union mir_dls 110 mirror data has left sprite counter <byte 5608> {field (By field)} <byte 5608> lbits:16 count R/WTI Count of writes to this reg. lbits:16 rsvd R Reserved {} or mir_dls 110 mirror data has left sprite counter <byte 5608> ulong value As longword endunion mir_dls 110 mirror data has left sprite counter <byte 5612> union mir_csr2 114 mirror control and status continued <byte 5612> {field (By field previous Split-Response)} <byte 5612> lbits:1 err_scwopsr R/W1C Split-Completion without a lbits:14 rsvd1 R Reserved lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK (rsvd in p0_csr & p1_csr) lbits:1 sel_scwopsr R/W Select P_INT(0/1)_L for scnosr lbits:14 rsvd R Reserved lbits:1 sel_mir_bad R/W Sprite P_INT(0/1)_L for scnosr (rsvd in p0_csr & p1_cs r) {} or mir_csr2 114 mirror control and status continued <byte 5612> ulong value As longword endunion mir_csr2 114 mirror control and status continued <byte 5616> {rsvd6[0] (118 - 11c unused)} <byte 5616> ulong value {} <byte 5620> {rsvd6[1] (118 - 11c unused)} <byte 5620> ulong value {}

<byte 5624> union x_cb 120 xor-dma command block base address <byte 5624> {field (By field)} <byte 5624> lbits:19 base_addr R/W Base Address of XOR-DMA SCDBs lbits:13 rsvd R Reserved {} or x_cb 120 xor-dma command block base address <byte 5624> ulong value As longword endunion x_cb 120 xor-dma command block base address <byte 5628> union x_pi 124 xor-dma producer index <byte 5628> {field (By field)} <byte 5628> lbits:11 index R/W SCDB index lbits:21 rsvd R Reserved {} or x_pi 124 xor-dma producer index <byte 5628> ulong value As longword endunion x_pi 124 xor-dma producer index <byte 5632> union x_ci 128 xor-dma consumer index <byte 5632> {field (By field)} <byte 5632> lbits:11 index R/W SCDB index lbits:21 rsvd R Reserved {} or x_ci 128 xor-dma consumer index <byte 5632> ulong value As longword endunion x_ci 128 xor-dma consumer index <byte 5636> union x_cc 12c xor-dma current command <byte 5636> {field (By field)} <byte 5636> lbits:4 rsvd R Reserved lbits:20 qword_cnt R Transfer Size in Qwords lbits:7 opcode R DMA Operation lbits:1 I R Interrupt on command completion {} or x_cc 12c xor-dma current command <byte 5636> ulong value As longword endunion x_cc 12c xor-dma current command <byte 5640> union x_usa 130 xor-dma upper source address <byte 5640> {field (By field)} <byte 5640> lbits:8 x_sa3 R Upper Source Address for x_sa3 lbits:8 x_sa2 R Upper Source Address for x_sa2 lbits:8 x_sa1 R Upper Source Address for x_sa1 lbits:8 x_sa0 R Upper Source Address for x_sa0 {}

or x_usa 130 xor-dma upper source address <byte 5640> ulong value As longword endunion x_usa 130 xor-dma upper source address <byte 5644> union x_sa[0] 134 - 140 xor-dma source addresses 0-3 <byte 5644> {field (By field)} <byte 5644> lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {} or x_sa[0] 134 - 140 xor-dma source addresses 0-3 <byte 5644> ulong value As longword endunion x_sa[0] 134 - 140 xor-dma source addresses 0-3 <byte 5648> union x_sa[1] 134 - 140 xor-dma source addresses 0-3 <byte 5648> {field (By field)} <byte 5648> lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {} or x_sa[1] 134 - 140 xor-dma source addresses 0-3 <byte 5648> ulong value As longword endunion x_sa[1] 134 - 140 xor-dma source addresses 0-3 <byte 5652> union x_sa[2] 134 - 140 xor-dma source addresses 0-3 <byte 5652> {field (By field)} <byte 5652> lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {} or x_sa[2] 134 - 140 xor-dma source addresses 0-3 <byte 5652> ulong value As longword endunion x_sa[2] 134 - 140 xor-dma source addresses 0-3 <byte 5656> union x_sa[3] 134 - 140 xor-dma source addresses 0-3 <byte 5656> {field (By field)} <byte 5656> lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {} or x_sa[3] 134 - 140 xor-dma source addresses 0-3 <byte 5656> ulong value As longword endunion x_sa[3] 134 - 140 xor-dma source addresses 0-3 <byte 5660> union x_da 144 xor-dma destination address <byte 5660> {field (By field)} <byte 5660> lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {}

or x_da 144 xor-dma destination address <byte 5660> ulong value As longword endunion x_da 144 xor-dma destination address <byte 5664> union x_uda 148 xor-dma upper destination address <byte 5664> {field (By field)} <byte 5664> lbits:24 rsvd R Reserved lbits:8 x_da R Upper Destination Addr for x_da {} or x_uda 148 xor-dma upper destination address <byte 5664> ulong value As longword endunion x_uda 148 xor-dma upper destination address <byte 5668> {x_spare (14c xor-dma spare)} <byte 5668> ulong value {} <byte 5672> {x_tmo (150 xor-dma transfer time out)} <byte 5672> ulong value {} <byte 5676> union x_csr 154 xor-dma control and status <byte 5676> {field (By field ** in q_pint and W1C in q_pint))} <byte 5676> lbits:1 cmp_err R Compare Error -- (duplicated lbits:1 err_count R/W1C Error, Count lbits:1 err_invop R/W1C Error, Invalid Opcode lbits:1 err_parity R/W1C Error, Parity lbits:1 err_efe R/W1C Error, End Frame Error lbits:1 err_sfe R/W1C Error, Start Frame Error lbits:1 err_toe R/W1C Error, TimeOut Error lbits:2 rsvd2 R Reserved lbits:1 sel_count R/W Select P_INT(0/1)_L for count lbits:1 sel_invop R/W Select P_INT(0/1)_L for invop lbits:1 sel_parity R/W Select P_INT(0/1)_L for parity lbits:1 sel_efe R/W Select P_INT(0/1)_L for efe lbits:1 sel_sfe R/W Select P_INT(0/1)_L for sfe lbits:1 sel_toe R/W Select P_INT(0/1)_L for toe lbits:2 rsvd1 R Reserved lbits:1 ena_count R/W Enable Count Errors lbits:1 ena_invop R/W Enable Invalid Opcode Errors lbits:1 ena_parity R/W Enable Parity Errors lbits:1 ena_efe R/W Enable End Frame Errors lbits:1 ena_sfe R/W Enable Start Frame Errors lbits:9 rsvd R Reserved lbits:1 ena_dma R/W Enables XOR-DMA operations {} or x_csr 154 xor-dma control and status <byte 5676> ulong value As longword endunion x_csr 154 xor-dma control and status <byte 5680> {x_qda (158 xor_dma q destination address 1 - new for Sprite 4)}

<byte 5680> ulong value {} <byte 5684> {x_co (15c xor_dma RAID 6 coefficients - new for Sprite 4)} <byte 5684> ulong value {} <byte 5688> union m_tr 160 memory timing <byte 5688> {field (By field)} <byte 5688> lbits:1 Twtr R/W Timing, WR to RD cmd delay lbits:3 Trc R/W Timing, Activate to active cmd (same bnk) or Autoref to ' ' lbits:2 Trcd R/W Timing, Activate to RD or WR lbits:3 Tras R/W Timing, Activate to Precharge lbits:2 Trp R/W Timing, Precharge to Activate lbits:3 Trfc R/W Timing, Autoref cmd to Autoref or Activate cmd lbits:1 sdram_avail R Memory Unavailable When Cleared lbits:1 ecc_disable R/W Disable ECC Correction lbits:1 self_ref R/W Refresh Mode: 1=DIMMs,0=Sprite lbits:1 rsvd1 R/W Reserved (R/W from prev. use) lbits:14 rsvd R Reserved {} or m_tr 160 memory timing <byte 5688> ulong value As longword endunion m_tr 160 memory timing <byte 5692> union m_cfg 164 memory configuration <byte 5692> {field (By field)} <byte 5692> lbits:9 refrate R/W Refresh Rate Count lbits:1 refcnten R/W Enable Refresh Rate Counter lbits:1 init_rfsh R/W Issue Auto Refresh Commands lbits:1 rsvd1 R/W Reserved (R/W from prev. use) lbits:12 rfcntr R/W Refresh Cycles with init_rfsh lbits:1 ss_dimms R/W Single Sided DIMMs Installed lbits:1 scrub_en R/W Enable HW Scrubbing lbits:6 rsvd R Reserved {} or m_cfg 164 memory configuration <byte 5692> ulong value As longword endunion m_cfg 164 memory configuration <byte 5696> union m_mrs 168 mode register set <byte 5696> {field (By field)} <byte 5696> lbits:3 burst_length R Burst Length lbits:1 burst_type R Burst Type lbits:3 cas_latency R/W CAS Latency lbits:5 op_mode R/W Operating Mode lbits:20 rsvd R Reserved {} or m_mrs 168 mode register set <byte 5696>

ulong value As longword endunion m_mrs 168 mode register set <byte 5700> union m_emrs 16c extended mode register set <byte 5700> {field (By field)} <byte 5700> lbits:1 sdram_dll_dis R/W Disable DLL in DDR SDRAMs lbits:1 ds R/W Drive Strength(1=Weak,0=Normal) lbits:1 qfc R/W QFC FET Isolation Control lbits:9 xemrs R/W Rsvd emrs JEDEC bits, set 0 lbits:20 rsvd R Reserved {} or m_emrs 16c extended mode register set <byte 5700> ulong value As longword endunion m_emrs 16c extended mode register set <byte 5704> union m_siz 170 DDR SRAM Size <byte 5704> {field (By field)} <byte 5704> lbits:3 ddr_size R/W DDR Memory Size Code lbits:2 installed_dimms R/W Number of DIMMs Installed lbits:1 scrub_test R/W Test bit for HW Scrub Circuit lbits:2 la_socket R/W Socket Number of L.A. (0->3) lbits:1 lap R/W Logic Analyzer Probe Installed lbits:23 rsvd R Reserved {} or m_siz 170 DDR SRAM Size <byte 5704> ulong value As longword endunion m_siz 170 DDR SRAM Size <byte 5708> union m_ese 174 ECC error status even <byte 5708> {field (By field)} <byte 5708> lbits:1 ude R/WCA Test bit for HW Scrub Circuit lbits:1 cde R/WCA Socket Number of L.A. (0->3) lbits:22 rsvd R Reserved lbits:8 syndrome R/WCA Syndrome when cde or ude == 1 {} or m_ese 174 ECC error status even <byte 5708> ulong value As longword endunion m_ese 174 ECC error status even <byte 5712> union m_eso 178 ECC error status odd <byte 5712> {field (By field)} <byte 5712> lbits:1 ude R/WCA Test bit for HW Scrub Circuit lbits:1 cde R/WCA Socket Number of L.A. (0->3) lbits:22 rsvd R Reserved lbits:8 syndrome R/WCA Syndrome when cde or ude == 1 {} or m_eso 178 ECC error status odd <byte 5712> ulong value As longword

endunion m_eso 178 ECC error status odd <byte 5716> union m_eae 17c ECC address error even <byte 5716> {field (By field)} <byte 5716> lbits:32 ecc_aoe_35_4 R ECC Address of Error, bits 35:4 {} or m_eae 17c ECC address error even <byte 5716> ulong value As longword endunion m_eae 17c ECC address error even <byte 5720> union m_eao 180 ECC address error odd <byte 5720> {field (By field)} <byte 5720> lbits:32 ecc_aoe_35_4 R ECC Address of Error, bits 35:4 {} or m_eao 180 ECC address error odd <byte 5720> ulong value As longword endunion m_eao 180 ECC address error odd <byte 5724> union m_esc 184 ECC syndrome preset, correctable error counter <byte 5724> {field (By field)} <byte 5724> lbits:16 cec R/W Correctable Error Counter lbits:8 odd_egs R/W Odd Error Generating Syndrome lbits:8 even_egs R/W Even Error Generating Syndrome {} or m_esc 184 ECC syndrome preset, correctable error counter <byte 5724> ulong value As longword endunion m_esc 184 ECC syndrome preset, correctable error counter <byte 5728> union m_es 188 DDR error status <byte 5728> {field (By field Halts chip - h)} <byte 5728> lbits:1 err_ncb R/W1C New Command Bad h lbits:1 err_cdpe R/W1C Cmd/Data Parity Error h lbits:1 err_ude R/CLL Uncorrectable Data Error h lbits:1 err_bwde R/W1C Bad Write Data Error h lbits:1 err_cde R/CLL Correctable Data Error lbits:3 rsvd2 R Reserved lbits:1 sel_ncb R/W Select P_INT(0/1)_L for ncb's lbits:1 sel_cdpe R/W Select P_INT(0/1)_L for cdpe's lbits:1 sel_ude R/W Select P_INT(0/1)_L for ude's lbits:1 sel_bwde R/W Select P_INT(0/1)_L for bwde's lbits:1 sel_cde R/W Select P_INT(0/1)_L for cde's lbits:3 rsvd1 R Reserved lbits:1 dis_ncb R/W Disable New Command Bad lbits:1 dis_cdpe R/W Disable Cmd/Data Parity Error lbits:1 dis_ude R/W Disable Uncorrectable Data Err lbits:1 dis_bwde R/W Disable Bad Write Data Error lbits:1 dis_cde R/W Disable Correctable Data Error lbits:11 rsvd R Reserved {}

or m_es 188 DDR error status <byte 5728> ulong value As longword endunion m_es 188 DDR error status <byte 5732> union m_sta 18c scrub test address <byte 5732> {field (By field)} <byte 5732> lbits:32 start_addr_35_5 R/W Scrub Test Address, bits 35:5 {} or m_sta 18c scrub test address <byte 5732> ulong value As longword endunion m_sta 18c scrub test address {} <byte 5736> do_not_display[624] union_pad Union Element Padding (DO NOT DISPLAY!) endunion csr Sprite CSR Registers {} <byte 6360> {quartcr[0] (SC28L194 Quad UART Control Registers a, b, c, d)} <byte 6360> union bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6360> {field (By field)} <byte 6360> tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6360> utiny value As byte endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6361> union iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6361> {field (By field)} <byte 6361> tbits:2 io0_control Bits 1:0 I/O0 control tbits:2 io1_control Bits 3:2 I/O1 control tbits:2 io2_control Bits 5:4 I/O2 control tbits:2 io3_control Bits 7:6 I/O3 control {} or iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6361> utiny value As byte endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6362> union mr1 (Offset 0x01) R/W Mode Register 1 <byte 6362> {field (By field)} <byte 6362> tbits:2 bits_per_character Bit 1:0 Bits per Character tbits:1 parity_type Bit 2 Parity Type tbits:2 parity_mode Bit 4:3 Parity Mode tbits:1 error_mode Bit 5 Error Mode tbits:1 isr_read_mode Bit 6 ISR Read Mode tbits:1 rx_rts_control Bit 7 Receiver RTS Control {}

or mr1 (Offset 0x01) R/W Mode Register 1 <byte 6362> utiny value As byte endunion mr1 (Offset 0x01) R/W Mode Register 1 <byte 6363> union mr0 (Offset 0x00) R/W Mode Register 0 <byte 6363> {field (By field)} <byte 6363> tbits:2 ar_control Bit 1:0 Address Recognition control tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition tbits:1 ar_transparency Bit 6 Address Recognition transparency tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency {} or mr0 (Offset 0x00) R/W Mode Register 0 <byte 6363> utiny value As byte endunion mr0 (Offset 0x00) R/W Mode Register 0 <byte 6364> union bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6364> {field (By field)} <byte 6364> tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interr upt bid tbits:5 reserved Bits 7:3 Reserved {} or bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6364> utiny value As byte endunion bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6365> union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6365> {field (By field)} <byte 6365> tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6365> utiny value As byte endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6366> {rsvd1 ((Offset 0x05) NA Reserved)} <byte 6366> utiny value {} <byte 6367> union bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6367> {field (By field)} <byte 6367> tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6367> utiny value As byte

endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6368> union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6368> {field (By field)} <byte 6368> tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Thres hold tbits:1 reserved Bit 7 Reserved. Set to 0 {} or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6368> utiny value As byte endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6369> union arcr (Offset 0x0A) R/W Address Recognition Character <byte 6369> {field (By field)} <byte 6369> tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Chara cter Recognition {} or arcr (Offset 0x0A) R/W Address Recognition Character <byte 6369> utiny value As byte endunion arcr (Offset 0x0A) R/W Address Recognition Character <byte 6370> union xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6370> {field (By field)} <byte 6370> tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recogni tion {} or xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6370> utiny value As byte endunion xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6371> union xoncr (Offset 0x08) R/W Xon Character Register <byte 6371> {field (By field)} <byte 6371> tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recogniti on {} or xoncr (Offset 0x08) R/W Xon Character Register <byte 6371> utiny value As byte endunion xoncr (Offset 0x08) R/W Xon Character Register <byte 6372> union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6372> union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6372> {field (By field)} <byte 6372> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control

tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6372> utiny value As byte endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6372> union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6372> {field (By field)} <byte 6372> tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector {} or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6372> utiny value As byte endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6372> utiny value As byte endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6373> union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6373> {field (By field)} <byte 6373> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6373> utiny value As byte endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6374> union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-d og Timer Run Control (UARTB only) <byte 6374> {testreg ((Offset 0x0D) R/W Test Register (UARTA only))} <byte 6374> utiny value {} or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6374> union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6374> {field (By field)} <byte 6374> tbits:1 wdt_a Bit 0 WDT a tbits:1 wdt_b Bit 1 WDT b tbits:1 wdt_c Bit 2 WDT c tbits:1 wdt_d Bit 3 WDT d tbits:4 reserved Bits 7:4 Reserved {}

or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6374> utiny value As byte endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6374> utiny value As byte endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watc h-dog Timer Run Control (UARTB only) <byte 6375> union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6375> {field (By field)} <byte 6375> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6375> utiny value As byte endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {} <byte 6376> {quartcr[1] (SC28L194 Quad UART Control Registers a, b, c, d)} <byte 6376> union bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6376> {field (By field)} <byte 6376> tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6376> utiny value As byte endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6377> union iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6377> {field (By field)} <byte 6377> tbits:2 io0_control Bits 1:0 I/O0 control tbits:2 io1_control Bits 3:2 I/O1 control tbits:2 io2_control Bits 5:4 I/O2 control tbits:2 io3_control Bits 7:6 I/O3 control {} or iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6377> utiny value As byte endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6378> union mr1 (Offset 0x01) R/W Mode Register 1 <byte 6378> {field (By field)} <byte 6378> tbits:2 bits_per_character Bit 1:0 Bits per Character tbits:1 parity_type Bit 2 Parity Type tbits:2 parity_mode Bit 4:3 Parity Mode tbits:1 error_mode Bit 5 Error Mode

tbits:1 isr_read_mode Bit 6 ISR Read Mode tbits:1 rx_rts_control Bit 7 Receiver RTS Control {} or mr1 (Offset 0x01) R/W Mode Register 1 <byte 6378> utiny value As byte endunion mr1 (Offset 0x01) R/W Mode Register 1 <byte 6379> union mr0 (Offset 0x00) R/W Mode Register 0 <byte 6379> {field (By field)} <byte 6379> tbits:2 ar_control Bit 1:0 Address Recognition control tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition tbits:1 ar_transparency Bit 6 Address Recognition transparency tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency {} or mr0 (Offset 0x00) R/W Mode Register 0 <byte 6379> utiny value As byte endunion mr0 (Offset 0x00) R/W Mode Register 0 <byte 6380> union bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6380> {field (By field)} <byte 6380> tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interr upt bid tbits:5 reserved Bits 7:3 Reserved {} or bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6380> utiny value As byte endunion bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6381> union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6381> {field (By field)} <byte 6381> tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6381> utiny value As byte endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6382> {rsvd1 ((Offset 0x05) NA Reserved)} <byte 6382> utiny value {} <byte 6383> union bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6383> {field (By field)} <byte 6383> tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid tbits:5 reserved Bits 7:3 Reserved {}

or bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6383> utiny value As byte endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6384> union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6384> {field (By field)} <byte 6384> tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Thres hold tbits:1 reserved Bit 7 Reserved. Set to 0 {} or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6384> utiny value As byte endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6385> union arcr (Offset 0x0A) R/W Address Recognition Character <byte 6385> {field (By field)} <byte 6385> tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Chara cter Recognition {} or arcr (Offset 0x0A) R/W Address Recognition Character <byte 6385> utiny value As byte endunion arcr (Offset 0x0A) R/W Address Recognition Character <byte 6386> union xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6386> {field (By field)} <byte 6386> tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recogni tion {} or xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6386> utiny value As byte endunion xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6387> union xoncr (Offset 0x08) R/W Xon Character Register <byte 6387> {field (By field)} <byte 6387> tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recogniti on {} or xoncr (Offset 0x08) R/W Xon Character Register <byte 6387> utiny value As byte endunion xoncr (Offset 0x08) R/W Xon Character Register <byte 6388> union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6388> union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6388> {field (By field)}

<byte 6388> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6388> utiny value As byte endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6388> union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6388> {field (By field)} <byte 6388> tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector {} or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6388> utiny value As byte endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6388> utiny value As byte endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6389> union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6389> {field (By field)} <byte 6389> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6389> utiny value As byte endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6390> union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-d og Timer Run Control (UARTB only) <byte 6390> {testreg ((Offset 0x0D) R/W Test Register (UARTA only))} <byte 6390> utiny value {} or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6390> union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6390> {field (By field)} <byte 6390> tbits:1 wdt_a Bit 0 WDT a tbits:1 wdt_b Bit 1 WDT b tbits:1 wdt_c Bit 2 WDT c

tbits:1 wdt_d Bit 3 WDT d tbits:4 reserved Bits 7:4 Reserved {} or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6390> utiny value As byte endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6390> utiny value As byte endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watc h-dog Timer Run Control (UARTB only) <byte 6391> union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6391> {field (By field)} <byte 6391> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6391> utiny value As byte endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {} <byte 6392> {quartcr[2] (SC28L194 Quad UART Control Registers a, b, c, d)} <byte 6392> union bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6392> {field (By field)} <byte 6392> tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6392> utiny value As byte endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6393> union iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6393> {field (By field)} <byte 6393> tbits:2 io0_control Bits 1:0 I/O0 control tbits:2 io1_control Bits 3:2 I/O1 control tbits:2 io2_control Bits 5:4 I/O2 control tbits:2 io3_control Bits 7:6 I/O3 control {} or iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6393> utiny value As byte endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6394> union mr1 (Offset 0x01) R/W Mode Register 1 <byte 6394> {field (By field)} <byte 6394> tbits:2 bits_per_character Bit 1:0 Bits per Character

tbits:1 parity_type Bit 2 Parity Type tbits:2 parity_mode Bit 4:3 Parity Mode tbits:1 error_mode Bit 5 Error Mode tbits:1 isr_read_mode Bit 6 ISR Read Mode tbits:1 rx_rts_control Bit 7 Receiver RTS Control {} or mr1 (Offset 0x01) R/W Mode Register 1 <byte 6394> utiny value As byte endunion mr1 (Offset 0x01) R/W Mode Register 1 <byte 6395> union mr0 (Offset 0x00) R/W Mode Register 0 <byte 6395> {field (By field)} <byte 6395> tbits:2 ar_control Bit 1:0 Address Recognition control tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition tbits:1 ar_transparency Bit 6 Address Recognition transparency tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency {} or mr0 (Offset 0x00) R/W Mode Register 0 <byte 6395> utiny value As byte endunion mr0 (Offset 0x00) R/W Mode Register 0 <byte 6396> union bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6396> {field (By field)} <byte 6396> tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interr upt bid tbits:5 reserved Bits 7:3 Reserved {} or bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6396> utiny value As byte endunion bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6397> union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6397> {field (By field)} <byte 6397> tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6397> utiny value As byte endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6398> {rsvd1 ((Offset 0x05) NA Reserved)} <byte 6398> utiny value {} <byte 6399> union bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6399> {field (By field)} <byte 6399>

tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6399> utiny value As byte endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6400> union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6400> {field (By field)} <byte 6400> tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Thres hold tbits:1 reserved Bit 7 Reserved. Set to 0 {} or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6400> utiny value As byte endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6401> union arcr (Offset 0x0A) R/W Address Recognition Character <byte 6401> {field (By field)} <byte 6401> tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Chara cter Recognition {} or arcr (Offset 0x0A) R/W Address Recognition Character <byte 6401> utiny value As byte endunion arcr (Offset 0x0A) R/W Address Recognition Character <byte 6402> union xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6402> {field (By field)} <byte 6402> tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recogni tion {} or xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6402> utiny value As byte endunion xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6403> union xoncr (Offset 0x08) R/W Xon Character Register <byte 6403> {field (By field)} <byte 6403> tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recogniti on {} or xoncr (Offset 0x08) R/W Xon Character Register <byte 6403> utiny value As byte endunion xoncr (Offset 0x08) R/W Xon Character Register <byte 6404> union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6404>

union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6404> {field (By field)} <byte 6404> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6404> utiny value As byte endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6404> union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6404> {field (By field)} <byte 6404> tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector {} or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6404> utiny value As byte endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6404> utiny value As byte endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6405> union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6405> {field (By field)} <byte 6405> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6405> utiny value As byte endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6406> union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-d og Timer Run Control (UARTB only) <byte 6406> {testreg ((Offset 0x0D) R/W Test Register (UARTA only))} <byte 6406> utiny value {} or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6406> union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6406> {field (By field)} <byte 6406>

tbits:1 wdt_a Bit 0 WDT a tbits:1 wdt_b Bit 1 WDT b tbits:1 wdt_c Bit 2 WDT c tbits:1 wdt_d Bit 3 WDT d tbits:4 reserved Bits 7:4 Reserved {} or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6406> utiny value As byte endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6406> utiny value As byte endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watc h-dog Timer Run Control (UARTB only) <byte 6407> union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6407> {field (By field)} <byte 6407> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6407> utiny value As byte endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {} <byte 6408> {quartcr[3] (SC28L194 Quad UART Control Registers a, b, c, d)} <byte 6408> union bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6408> {field (By field)} <byte 6408> tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6408> utiny value As byte endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6409> union iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6409> {field (By field)} <byte 6409> tbits:2 io0_control Bits 1:0 I/O0 control tbits:2 io1_control Bits 3:2 I/O1 control tbits:2 io2_control Bits 5:4 I/O2 control tbits:2 io3_control Bits 7:6 I/O3 control {} or iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6409> utiny value As byte endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6410> union mr1 (Offset 0x01) R/W Mode Register 1 <byte 6410>

{field (By field)} <byte 6410> tbits:2 bits_per_character Bit 1:0 Bits per Character tbits:1 parity_type Bit 2 Parity Type tbits:2 parity_mode Bit 4:3 Parity Mode tbits:1 error_mode Bit 5 Error Mode tbits:1 isr_read_mode Bit 6 ISR Read Mode tbits:1 rx_rts_control Bit 7 Receiver RTS Control {} or mr1 (Offset 0x01) R/W Mode Register 1 <byte 6410> utiny value As byte endunion mr1 (Offset 0x01) R/W Mode Register 1 <byte 6411> union mr0 (Offset 0x00) R/W Mode Register 0 <byte 6411> {field (By field)} <byte 6411> tbits:2 ar_control Bit 1:0 Address Recognition control tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition tbits:1 ar_transparency Bit 6 Address Recognition transparency tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency {} or mr0 (Offset 0x00) R/W Mode Register 0 <byte 6411> utiny value As byte endunion mr0 (Offset 0x00) R/W Mode Register 0 <byte 6412> union bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6412> {field (By field)} <byte 6412> tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interr upt bid tbits:5 reserved Bits 7:3 Reserved {} or bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6412> utiny value As byte endunion bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6413> union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6413> {field (By field)} <byte 6413> tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6413> utiny value As byte endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6414> {rsvd1 ((Offset 0x05) NA Reserved)} <byte 6414> utiny value {} <byte 6415> union bcrcos (Offset 0x04) R/W Bid Control, Change of State

<byte 6415> {field (By field)} <byte 6415> tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6415> utiny value As byte endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6416> union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6416> {field (By field)} <byte 6416> tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Thres hold tbits:1 reserved Bit 7 Reserved. Set to 0 {} or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6416> utiny value As byte endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6417> union arcr (Offset 0x0A) R/W Address Recognition Character <byte 6417> {field (By field)} <byte 6417> tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Chara cter Recognition {} or arcr (Offset 0x0A) R/W Address Recognition Character <byte 6417> utiny value As byte endunion arcr (Offset 0x0A) R/W Address Recognition Character <byte 6418> union xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6418> {field (By field)} <byte 6418> tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recogni tion {} or xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6418> utiny value As byte endunion xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6419> union xoncr (Offset 0x08) R/W Xon Character Register <byte 6419> {field (By field)} <byte 6419> tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recogniti on {} or xoncr (Offset 0x08) R/W Xon Character Register <byte 6419> utiny value As byte endunion xoncr (Offset 0x08) R/W Xon Character Register <byte 6420>

union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6420> union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6420> {field (By field)} <byte 6420> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6420> utiny value As byte endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6420> union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6420> {field (By field)} <byte 6420> tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector {} or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6420> utiny value As byte endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6420> utiny value As byte endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6421> union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6421> {field (By field)} <byte 6421> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6421> utiny value As byte endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6422> union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-d og Timer Run Control (UARTB only) <byte 6422> {testreg ((Offset 0x0D) R/W Test Register (UARTA only))} <byte 6422> utiny value {} or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6422> union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)

<byte 6422> {field (By field)} <byte 6422> tbits:1 wdt_a Bit 0 WDT a tbits:1 wdt_b Bit 1 WDT b tbits:1 wdt_c Bit 2 WDT c tbits:1 wdt_d Bit 3 WDT d tbits:4 reserved Bits 7:4 Reserved {} or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6422> utiny value As byte endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6422> utiny value As byte endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watc h-dog Timer Run Control (UARTB only) <byte 6423> union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6423> {field (By field)} <byte 6423> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6423> utiny value As byte endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {} <byte 6424> {quartdr[0] (SC28L194 Quad UART Data Registers a, b, c, d)} <byte 6424> union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register <byte 6424> union rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6424> {field (By field)} <byte 6424> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6424> utiny value As byte endunion rxfifo (Offset 0x83) R Receiver FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6424> union txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6424> {field (By field)} <byte 6424> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6424> utiny value As byte

endunion txfifo (Offset 0x83) W Transmitter FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6424> utiny value As byte endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmit ter FIFO Register <byte 6425> union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrup t Mask Register <byte 6425> union isr (Offset 0x82) R Interrupt Status Register <byte 6425> {field (By field)} <byte 6425> tbits:1 txrdy Bit 0 Transmitter has entered arbitration process tbits:1 rxrdy Bit 1 Receiver has entered arbitration process tbits:1 change_break_state Bit 2 Change of Break State tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event Bit 4 Xon/off event tbits:1 ar_event Bit 5 Address recognition event tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out tbits:1 io_port_change_state Bit 7 I/O Port change of state {} or isr (Offset 0x82) R Interrupt Status Register <byte 6425> utiny value As byte endunion isr (Offset 0x82) R Interrupt Status Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6425> union imr (Offset 0x82) W Interrupt Mask Register <byte 6425> {field (By field)} <byte 6425> tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enab le tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out inter rupt enable tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupt ed enable {} or imr (Offset 0x82) W Interrupt Mask Register <byte 6425> utiny value As byte endunion imr (Offset 0x82) W Interrupt Mask Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6425> utiny value As byte endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Inter rupt Mask Register <byte 6426> union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Re gister

<byte 6426> union sr (Offset 0x81) R Channel Status Register <byte 6426> {field (By field)} <byte 6426> tbits:1 rx_ready Bit 0 Receiver Ready tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full tbits:1 tx_ready Bit 2 Transmitter Ready tbits:1 tx_empty Bit 3 Transmitter Empty tbits:1 overrun_error Bit 4 Overrun Error tbits:1 parity_error Bit 5 Parity Error tbits:1 framing_error Bit 6 Framing Error tbits:1 received_break Bit 7 Received Break {} or sr (Offset 0x81) R Channel Status Register <byte 6426> utiny value As byte endunion sr (Offset 0x81) R Channel Status Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6426> union cr (Offset 0x81) W Command Register <byte 6426> {field (By field)} <byte 6426> tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Re ceiver enables/Change Transmitter & Receiver enable conditions tbits:5 channel_command Bits 7:3 Channel Command {} or cr (Offset 0x81) W Command Register <byte 6426> utiny value As byte endunion cr (Offset 0x81) W Command Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6426> utiny value As byte endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register <byte 6427> union mr2 (Offset 0x80) R/W Mode Register 2 <byte 6427> {field (By field)} <byte 6427> tbits:2 stop_length Bit 1:0 Stop Length tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter tbits:1 tx_rts_control Bit 5 Transmitter RTS Control tbits:2 channel_mode Bits 7:6 Channel Mode {} or mr2 (Offset 0x80) R/W Mode Register 2 <byte 6427> utiny value As byte endunion mr2 (Offset 0x80) R/W Mode Register 2 <byte 6428> union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6428>

union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only ) <byte 6428> {field (By field)} <byte 6428> tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection {} or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) <byte 6428> utiny value As byte endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA o nly) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6428> union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6428> {field (By field)} <byte 6428> tbits:1 gpor_0 Bit 0 GPOR(0) tbits:1 gpor_1 Bit 1 GPOR(1) tbits:1 gpor_2 Bit 2 GPOR(2) tbits:1 gpor_3 Bit 3 GPOR(3) tbits:4 reserved Bits 7:4 Reserved {} or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6428> utiny value As byte endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6428> utiny value As byte endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA onl y) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6429> union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6429> {field (By field)} <byte 6429> tbits:2 txd_character_status Bits 1:0 TxD character status tbits:2 txd_flow_status Bits 3:2 TxD flow status tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmissi on status tbits:2 received_x_character_status Bits 7:6 Received X Character Status {} or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6429> utiny value As byte endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6430> union iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6430> {field (By field)} <byte 6430> tbits:1 io0_output Bit 0 I/O0 output tbits:1 io1_output Bit 1 I/O1 output tbits:1 io2_output Bit 2 I/O2 output tbits:1 io3_output Bit 3 I/O3 output

tbits:1 io0_enable Bit 4 I/O0 enable tbits:1 io1_enable Bit 5 I/O1 enable tbits:1 io2_enable Bit 6 I/O2 enable tbits:1 io3_enable Bit 7 I/O3 enable {} or iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6430> utiny value As byte endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6431> union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Gene rator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) <byte 6431> union ipr (Offset 0x84) R Input Port Register <byte 6431> {field (By field)} <byte 6431> tbits:1 io0_state Bit 0 I/O0 state tbits:1 io1_state Bit 1 I/O1 state tbits:1 io2_state Bit 2 I/O2 state tbits:1 io3_state Bit 3 I/O3 state tbits:1 io0_change Bit 4 I/O0 change tbits:1 io1_change Bit 5 I/O1 change tbits:1 io2_change Bit 6 I/O2 change tbits:1 io3_change Bit 7 I/O3 change {} or ipr (Offset 0x84) R Input Port Register <byte 6431> utiny value As byte endunion ipr (Offset 0x84) R Input Port Register or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6431> union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UART A only) <byte 6431> {field (By field)} <byte 6431> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA o nly) <byte 6431> utiny value As byte endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (U ARTA only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6431> union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UART B only) <byte 6431> {field (By field)} <byte 6431> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor

{} or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB o nly) <byte 6431> utiny value As byte endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (U ARTB only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6431> utiny value As byte endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate G enerator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generat or Timer Register Lower a (UARTB only) <byte 6432> union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) ( Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6432> union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6432> {field (By field)} <byte 6432> tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0) tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1) tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2) tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3) {} or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6432> utiny value As byte endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA onl y) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6432> union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6432> {field (By field)} <byte 6432> tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0) tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1) tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2) tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3) {} or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6432> utiny value As byte endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only ) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6432> utiny value As byte endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only ) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6433> {rsvd3 ((Offset 0x8A) NA Reserved)} <byte 6433> utiny value

{} <byte 6434> {rsvd2 ((Offset 0x89) NA Reserved)} <byte 6434> utiny value {} <byte 6435> {rsvd1 ((Offset 0x88) NA Reserved)} <byte 6435> utiny value {} <byte 6436> union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6436> union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6436> {field (By field)} <byte 6436> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6436> utiny value As byte endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6436> union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6436> {field (By field)} <byte 6436> tbits:3 other_types Bit 2:0 Other types tbits:2 reserved Bit 4:3 Reserved tbits:1 tx_interrupt Bit 5 Transmitter Interrupt tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt {} or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6436> utiny value As byte endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6436> utiny value As byte endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6437> union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x 8E) W Global Transmit FIFO Register (UARTA only) <byte 6437> union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6437> {field (By field)} <byte 6437> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data

{} or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6437> utiny value As byte endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6437> union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6437> {field (By field)} <byte 6437> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6437> utiny value As byte endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6437> utiny value As byte endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6438> union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8 D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6438> union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6438> {field (By field)} <byte 6438> tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code tbits:4 reserved Bits 7:4 Reserved {} or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6438> utiny value As byte endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6438> union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UART A only) <byte 6438> {field (By field)} <byte 6438> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA o nly) <byte 6438> utiny value As byte endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (U ARTA only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba

ud Rate Generator Timer Register Lower b (UARTB only) <byte 6438> union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UART B only) <byte 6438> {field (By field)} <byte 6438> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB o nly) <byte 6438> utiny value As byte endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (U ARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6438> utiny value As byte endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6439> union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C ) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Cu rrent Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Time r Control Register (UARTB only) <byte 6439> union cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6439> {field (By field)} <byte 6439> tbits:3 channel_number Bits 2:0 Channel number tbits:3 current_byte_count_type Bits 5:3 Current byte count/type tbits:2 type Bits 7:6 Type {} or cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6439> utiny value As byte endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6439> union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6439> {field (By field)} <byte 6439> tbits:3 channel_code Bits 2:0 Channel code tbits:5 reserved Bits 7:3 Reserved {} or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6439> utiny value As byte endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre

nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6439> {ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))} <byte 6439> utiny value {} or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6439> union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) <byte 6439> {field (By field)} <byte 6439> tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control {} or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB on ly) <byte 6439> utiny value As byte endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UA RTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6439> utiny value As byte endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0 x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator T imer Control Register (UARTB only) {} <byte 6440> {quartdr[1] (SC28L194 Quad UART Data Registers a, b, c, d)} <byte 6440> union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register <byte 6440> union rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6440> {field (By field)} <byte 6440> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6440> utiny value As byte endunion rxfifo (Offset 0x83) R Receiver FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6440> union txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6440>

{field (By field)} <byte 6440> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6440> utiny value As byte endunion txfifo (Offset 0x83) W Transmitter FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6440> utiny value As byte endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmit ter FIFO Register <byte 6441> union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrup t Mask Register <byte 6441> union isr (Offset 0x82) R Interrupt Status Register <byte 6441> {field (By field)} <byte 6441> tbits:1 txrdy Bit 0 Transmitter has entered arbitration process tbits:1 rxrdy Bit 1 Receiver has entered arbitration process tbits:1 change_break_state Bit 2 Change of Break State tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event Bit 4 Xon/off event tbits:1 ar_event Bit 5 Address recognition event tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out tbits:1 io_port_change_state Bit 7 I/O Port change of state {} or isr (Offset 0x82) R Interrupt Status Register <byte 6441> utiny value As byte endunion isr (Offset 0x82) R Interrupt Status Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6441> union imr (Offset 0x82) W Interrupt Mask Register <byte 6441> {field (By field)} <byte 6441> tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enab le tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out inter rupt enable tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupt ed enable {} or imr (Offset 0x82) W Interrupt Mask Register <byte 6441> utiny value As byte endunion imr (Offset 0x82) W Interrupt Mask Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register

<byte 6441> utiny value As byte endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Inter rupt Mask Register <byte 6442> union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Re gister <byte 6442> union sr (Offset 0x81) R Channel Status Register <byte 6442> {field (By field)} <byte 6442> tbits:1 rx_ready Bit 0 Receiver Ready tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full tbits:1 tx_ready Bit 2 Transmitter Ready tbits:1 tx_empty Bit 3 Transmitter Empty tbits:1 overrun_error Bit 4 Overrun Error tbits:1 parity_error Bit 5 Parity Error tbits:1 framing_error Bit 6 Framing Error tbits:1 received_break Bit 7 Received Break {} or sr (Offset 0x81) R Channel Status Register <byte 6442> utiny value As byte endunion sr (Offset 0x81) R Channel Status Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6442> union cr (Offset 0x81) W Command Register <byte 6442> {field (By field)} <byte 6442> tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Re ceiver enables/Change Transmitter & Receiver enable conditions tbits:5 channel_command Bits 7:3 Channel Command {} or cr (Offset 0x81) W Command Register <byte 6442> utiny value As byte endunion cr (Offset 0x81) W Command Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6442> utiny value As byte endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register <byte 6443> union mr2 (Offset 0x80) R/W Mode Register 2 <byte 6443> {field (By field)} <byte 6443> tbits:2 stop_length Bit 1:0 Stop Length tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter tbits:1 tx_rts_control Bit 5 Transmitter RTS Control tbits:2 channel_mode Bits 7:6 Channel Mode {} or mr2 (Offset 0x80) R/W Mode Register 2

<byte 6443> utiny value As byte endunion mr2 (Offset 0x80) R/W Mode Register 2 <byte 6444> union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6444> union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only ) <byte 6444> {field (By field)} <byte 6444> tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection {} or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) <byte 6444> utiny value As byte endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA o nly) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6444> union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6444> {field (By field)} <byte 6444> tbits:1 gpor_0 Bit 0 GPOR(0) tbits:1 gpor_1 Bit 1 GPOR(1) tbits:1 gpor_2 Bit 2 GPOR(2) tbits:1 gpor_3 Bit 3 GPOR(3) tbits:4 reserved Bits 7:4 Reserved {} or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6444> utiny value As byte endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6444> utiny value As byte endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA onl y) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6445> union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6445> {field (By field)} <byte 6445> tbits:2 txd_character_status Bits 1:0 TxD character status tbits:2 txd_flow_status Bits 3:2 TxD flow status tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmissi on status tbits:2 received_x_character_status Bits 7:6 Received X Character Status {} or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6445> utiny value As byte endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6446> union iopior (Offset 0x85) R/W I/O Port Interrupt and Output

<byte 6446> {field (By field)} <byte 6446> tbits:1 io0_output Bit 0 I/O0 output tbits:1 io1_output Bit 1 I/O1 output tbits:1 io2_output Bit 2 I/O2 output tbits:1 io3_output Bit 3 I/O3 output tbits:1 io0_enable Bit 4 I/O0 enable tbits:1 io1_enable Bit 5 I/O1 enable tbits:1 io2_enable Bit 6 I/O2 enable tbits:1 io3_enable Bit 7 I/O3 enable {} or iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6446> utiny value As byte endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6447> union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Gene rator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) <byte 6447> union ipr (Offset 0x84) R Input Port Register <byte 6447> {field (By field)} <byte 6447> tbits:1 io0_state Bit 0 I/O0 state tbits:1 io1_state Bit 1 I/O1 state tbits:1 io2_state Bit 2 I/O2 state tbits:1 io3_state Bit 3 I/O3 state tbits:1 io0_change Bit 4 I/O0 change tbits:1 io1_change Bit 5 I/O1 change tbits:1 io2_change Bit 6 I/O2 change tbits:1 io3_change Bit 7 I/O3 change {} or ipr (Offset 0x84) R Input Port Register <byte 6447> utiny value As byte endunion ipr (Offset 0x84) R Input Port Register or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6447> union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UART A only) <byte 6447> {field (By field)} <byte 6447> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA o nly) <byte 6447> utiny value As byte endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (U ARTA only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6447>

union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UART B only) <byte 6447> {field (By field)} <byte 6447> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB o nly) <byte 6447> utiny value As byte endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (U ARTB only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6447> utiny value As byte endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate G enerator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generat or Timer Register Lower a (UARTB only) <byte 6448> union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) ( Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6448> union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6448> {field (By field)} <byte 6448> tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0) tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1) tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2) tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3) {} or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6448> utiny value As byte endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA onl y) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6448> union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6448> {field (By field)} <byte 6448> tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0) tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1) tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2) tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3) {} or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6448> utiny value As byte endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only ) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6448>

utiny value As byte endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only ) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6449> {rsvd3 ((Offset 0x8A) NA Reserved)} <byte 6449> utiny value {} <byte 6450> {rsvd2 ((Offset 0x89) NA Reserved)} <byte 6450> utiny value {} <byte 6451> {rsvd1 ((Offset 0x88) NA Reserved)} <byte 6451> utiny value {} <byte 6452> union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6452> union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6452> {field (By field)} <byte 6452> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6452> utiny value As byte endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6452> union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6452> {field (By field)} <byte 6452> tbits:3 other_types Bit 2:0 Other types tbits:2 reserved Bit 4:3 Reserved tbits:1 tx_interrupt Bit 5 Transmitter Interrupt tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt {} or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6452> utiny value As byte endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6452> utiny value As byte endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6453> union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x

8E) W Global Transmit FIFO Register (UARTA only) <byte 6453> union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6453> {field (By field)} <byte 6453> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6453> utiny value As byte endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6453> union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6453> {field (By field)} <byte 6453> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6453> utiny value As byte endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6453> utiny value As byte endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6454> union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8 D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6454> union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6454> {field (By field)} <byte 6454> tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code tbits:4 reserved Bits 7:4 Reserved {} or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6454> utiny value As byte endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6454> union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UART A only) <byte 6454> {field (By field)} <byte 6454> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA o

nly) <byte 6454> utiny value As byte endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (U ARTA only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6454> union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UART B only) <byte 6454> {field (By field)} <byte 6454> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB o nly) <byte 6454> utiny value As byte endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (U ARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6454> utiny value As byte endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6455> union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C ) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Cu rrent Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Time r Control Register (UARTB only) <byte 6455> union cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6455> {field (By field)} <byte 6455> tbits:3 channel_number Bits 2:0 Channel number tbits:3 current_byte_count_type Bits 5:3 Current byte count/type tbits:2 type Bits 7:6 Type {} or cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6455> utiny value As byte endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6455> union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6455> {field (By field)} <byte 6455> tbits:3 channel_code Bits 2:0 Channel code tbits:5 reserved Bits 7:3 Reserved

{} or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6455> utiny value As byte endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6455> {ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))} <byte 6455> utiny value {} or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6455> union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) <byte 6455> {field (By field)} <byte 6455> tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control {} or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB on ly) <byte 6455> utiny value As byte endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UA RTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6455> utiny value As byte endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0 x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator T imer Control Register (UARTB only) {} <byte 6456> {quartdr[2] (SC28L194 Quad UART Data Registers a, b, c, d)} <byte 6456> union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register <byte 6456> union rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6456> {field (By field)} <byte 6456> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6456>

utiny value As byte endunion rxfifo (Offset 0x83) R Receiver FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6456> union txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6456> {field (By field)} <byte 6456> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6456> utiny value As byte endunion txfifo (Offset 0x83) W Transmitter FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6456> utiny value As byte endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmit ter FIFO Register <byte 6457> union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrup t Mask Register <byte 6457> union isr (Offset 0x82) R Interrupt Status Register <byte 6457> {field (By field)} <byte 6457> tbits:1 txrdy Bit 0 Transmitter has entered arbitration process tbits:1 rxrdy Bit 1 Receiver has entered arbitration process tbits:1 change_break_state Bit 2 Change of Break State tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event Bit 4 Xon/off event tbits:1 ar_event Bit 5 Address recognition event tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out tbits:1 io_port_change_state Bit 7 I/O Port change of state {} or isr (Offset 0x82) R Interrupt Status Register <byte 6457> utiny value As byte endunion isr (Offset 0x82) R Interrupt Status Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6457> union imr (Offset 0x82) W Interrupt Mask Register <byte 6457> {field (By field)} <byte 6457> tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enab le tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out inter rupt enable tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupt ed enable

{} or imr (Offset 0x82) W Interrupt Mask Register <byte 6457> utiny value As byte endunion imr (Offset 0x82) W Interrupt Mask Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6457> utiny value As byte endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Inter rupt Mask Register <byte 6458> union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Re gister <byte 6458> union sr (Offset 0x81) R Channel Status Register <byte 6458> {field (By field)} <byte 6458> tbits:1 rx_ready Bit 0 Receiver Ready tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full tbits:1 tx_ready Bit 2 Transmitter Ready tbits:1 tx_empty Bit 3 Transmitter Empty tbits:1 overrun_error Bit 4 Overrun Error tbits:1 parity_error Bit 5 Parity Error tbits:1 framing_error Bit 6 Framing Error tbits:1 received_break Bit 7 Received Break {} or sr (Offset 0x81) R Channel Status Register <byte 6458> utiny value As byte endunion sr (Offset 0x81) R Channel Status Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6458> union cr (Offset 0x81) W Command Register <byte 6458> {field (By field)} <byte 6458> tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Re ceiver enables/Change Transmitter & Receiver enable conditions tbits:5 channel_command Bits 7:3 Channel Command {} or cr (Offset 0x81) W Command Register <byte 6458> utiny value As byte endunion cr (Offset 0x81) W Command Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6458> utiny value As byte endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register <byte 6459> union mr2 (Offset 0x80) R/W Mode Register 2 <byte 6459> {field (By field)} <byte 6459>

tbits:2 stop_length Bit 1:0 Stop Length tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter tbits:1 tx_rts_control Bit 5 Transmitter RTS Control tbits:2 channel_mode Bits 7:6 Channel Mode {} or mr2 (Offset 0x80) R/W Mode Register 2 <byte 6459> utiny value As byte endunion mr2 (Offset 0x80) R/W Mode Register 2 <byte 6460> union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6460> union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only ) <byte 6460> {field (By field)} <byte 6460> tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection {} or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) <byte 6460> utiny value As byte endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA o nly) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6460> union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6460> {field (By field)} <byte 6460> tbits:1 gpor_0 Bit 0 GPOR(0) tbits:1 gpor_1 Bit 1 GPOR(1) tbits:1 gpor_2 Bit 2 GPOR(2) tbits:1 gpor_3 Bit 3 GPOR(3) tbits:4 reserved Bits 7:4 Reserved {} or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6460> utiny value As byte endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6460> utiny value As byte endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA onl y) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6461> union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6461> {field (By field)} <byte 6461> tbits:2 txd_character_status Bits 1:0 TxD character status tbits:2 txd_flow_status Bits 3:2 TxD flow status tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmissi on status tbits:2 received_x_character_status Bits 7:6 Received X Character Status

{} or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6461> utiny value As byte endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6462> union iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6462> {field (By field)} <byte 6462> tbits:1 io0_output Bit 0 I/O0 output tbits:1 io1_output Bit 1 I/O1 output tbits:1 io2_output Bit 2 I/O2 output tbits:1 io3_output Bit 3 I/O3 output tbits:1 io0_enable Bit 4 I/O0 enable tbits:1 io1_enable Bit 5 I/O1 enable tbits:1 io2_enable Bit 6 I/O2 enable tbits:1 io3_enable Bit 7 I/O3 enable {} or iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6462> utiny value As byte endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6463> union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Gene rator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) <byte 6463> union ipr (Offset 0x84) R Input Port Register <byte 6463> {field (By field)} <byte 6463> tbits:1 io0_state Bit 0 I/O0 state tbits:1 io1_state Bit 1 I/O1 state tbits:1 io2_state Bit 2 I/O2 state tbits:1 io3_state Bit 3 I/O3 state tbits:1 io0_change Bit 4 I/O0 change tbits:1 io1_change Bit 5 I/O1 change tbits:1 io2_change Bit 6 I/O2 change tbits:1 io3_change Bit 7 I/O3 change {} or ipr (Offset 0x84) R Input Port Register <byte 6463> utiny value As byte endunion ipr (Offset 0x84) R Input Port Register or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6463> union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UART A only) <byte 6463> {field (By field)} <byte 6463> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA o nly) <byte 6463>

utiny value As byte endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (U ARTA only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6463> union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UART B only) <byte 6463> {field (By field)} <byte 6463> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB o nly) <byte 6463> utiny value As byte endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (U ARTB only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6463> utiny value As byte endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate G enerator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generat or Timer Register Lower a (UARTB only) <byte 6464> union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) ( Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6464> union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6464> {field (By field)} <byte 6464> tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0) tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1) tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2) tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3) {} or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6464> utiny value As byte endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA onl y) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6464> union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6464> {field (By field)} <byte 6464> tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0) tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1) tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2) tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3) {} or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)

<byte 6464> utiny value As byte endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only ) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6464> utiny value As byte endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only ) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6465> {rsvd3 ((Offset 0x8A) NA Reserved)} <byte 6465> utiny value {} <byte 6466> {rsvd2 ((Offset 0x89) NA Reserved)} <byte 6466> utiny value {} <byte 6467> {rsvd1 ((Offset 0x88) NA Reserved)} <byte 6467> utiny value {} <byte 6468> union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6468> union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6468> {field (By field)} <byte 6468> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6468> utiny value As byte endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6468> union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6468> {field (By field)} <byte 6468> tbits:3 other_types Bit 2:0 Other types tbits:2 reserved Bit 4:3 Reserved tbits:1 tx_interrupt Bit 5 Transmitter Interrupt tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt {} or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6468> utiny value As byte endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset

0x8F) R Global Interrupt Type Register (UARTB only) <byte 6468> utiny value As byte endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6469> union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x 8E) W Global Transmit FIFO Register (UARTA only) <byte 6469> union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6469> {field (By field)} <byte 6469> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6469> utiny value As byte endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6469> union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6469> {field (By field)} <byte 6469> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6469> utiny value As byte endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6469> utiny value As byte endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6470> union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8 D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6470> union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6470> {field (By field)} <byte 6470> tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code tbits:4 reserved Bits 7:4 Reserved {} or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6470> utiny value As byte endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6470> union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UART A only)

<byte 6470> {field (By field)} <byte 6470> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA o nly) <byte 6470> utiny value As byte endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (U ARTA only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6470> union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UART B only) <byte 6470> {field (By field)} <byte 6470> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB o nly) <byte 6470> utiny value As byte endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (U ARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6470> utiny value As byte endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6471> union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C ) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Cu rrent Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Time r Control Register (UARTB only) <byte 6471> union cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6471> {field (By field)} <byte 6471> tbits:3 channel_number Bits 2:0 Channel number tbits:3 current_byte_count_type Bits 5:3 Current byte count/type tbits:2 type Bits 7:6 Type {} or cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6471> utiny value As byte endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only)

<byte 6471> union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6471> {field (By field)} <byte 6471> tbits:3 channel_code Bits 2:0 Channel code tbits:5 reserved Bits 7:3 Reserved {} or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6471> utiny value As byte endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6471> {ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))} <byte 6471> utiny value {} or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6471> union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) <byte 6471> {field (By field)} <byte 6471> tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control {} or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB on ly) <byte 6471> utiny value As byte endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UA RTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6471> utiny value As byte endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0 x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator T imer Control Register (UARTB only) {} <byte 6472> {quartdr[3] (SC28L194 Quad UART Data Registers a, b, c, d)} <byte 6472> union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register <byte 6472> union rxfifo (Offset 0x83) R Receiver FIFO Register

<byte 6472> {field (By field)} <byte 6472> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6472> utiny value As byte endunion rxfifo (Offset 0x83) R Receiver FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6472> union txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6472> {field (By field)} <byte 6472> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6472> utiny value As byte endunion txfifo (Offset 0x83) W Transmitter FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6472> utiny value As byte endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmit ter FIFO Register <byte 6473> union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrup t Mask Register <byte 6473> union isr (Offset 0x82) R Interrupt Status Register <byte 6473> {field (By field)} <byte 6473> tbits:1 txrdy Bit 0 Transmitter has entered arbitration process tbits:1 rxrdy Bit 1 Receiver has entered arbitration process tbits:1 change_break_state Bit 2 Change of Break State tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event Bit 4 Xon/off event tbits:1 ar_event Bit 5 Address recognition event tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out tbits:1 io_port_change_state Bit 7 I/O Port change of state {} or isr (Offset 0x82) R Interrupt Status Register <byte 6473> utiny value As byte endunion isr (Offset 0x82) R Interrupt Status Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6473> union imr (Offset 0x82) W Interrupt Mask Register <byte 6473> {field (By field)} <byte 6473> tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enab le

tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out inter rupt enable tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupt ed enable {} or imr (Offset 0x82) W Interrupt Mask Register <byte 6473> utiny value As byte endunion imr (Offset 0x82) W Interrupt Mask Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6473> utiny value As byte endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Inter rupt Mask Register <byte 6474> union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Re gister <byte 6474> union sr (Offset 0x81) R Channel Status Register <byte 6474> {field (By field)} <byte 6474> tbits:1 rx_ready Bit 0 Receiver Ready tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full tbits:1 tx_ready Bit 2 Transmitter Ready tbits:1 tx_empty Bit 3 Transmitter Empty tbits:1 overrun_error Bit 4 Overrun Error tbits:1 parity_error Bit 5 Parity Error tbits:1 framing_error Bit 6 Framing Error tbits:1 received_break Bit 7 Received Break {} or sr (Offset 0x81) R Channel Status Register <byte 6474> utiny value As byte endunion sr (Offset 0x81) R Channel Status Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6474> union cr (Offset 0x81) W Command Register <byte 6474> {field (By field)} <byte 6474> tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Re ceiver enables/Change Transmitter & Receiver enable conditions tbits:5 channel_command Bits 7:3 Channel Command {} or cr (Offset 0x81) W Command Register <byte 6474> utiny value As byte endunion cr (Offset 0x81) W Command Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6474> utiny value As byte

endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register <byte 6475> union mr2 (Offset 0x80) R/W Mode Register 2 <byte 6475> {field (By field)} <byte 6475> tbits:2 stop_length Bit 1:0 Stop Length tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter tbits:1 tx_rts_control Bit 5 Transmitter RTS Control tbits:2 channel_mode Bits 7:6 Channel Mode {} or mr2 (Offset 0x80) R/W Mode Register 2 <byte 6475> utiny value As byte endunion mr2 (Offset 0x80) R/W Mode Register 2 <byte 6476> union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6476> union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only ) <byte 6476> {field (By field)} <byte 6476> tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection {} or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) <byte 6476> utiny value As byte endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA o nly) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6476> union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6476> {field (By field)} <byte 6476> tbits:1 gpor_0 Bit 0 GPOR(0) tbits:1 gpor_1 Bit 1 GPOR(1) tbits:1 gpor_2 Bit 2 GPOR(2) tbits:1 gpor_3 Bit 3 GPOR(3) tbits:4 reserved Bits 7:4 Reserved {} or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6476> utiny value As byte endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6476> utiny value As byte endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA onl y) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6477> union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6477>

{field (By field)} <byte 6477> tbits:2 txd_character_status Bits 1:0 TxD character status tbits:2 txd_flow_status Bits 3:2 TxD flow status tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmissi on status tbits:2 received_x_character_status Bits 7:6 Received X Character Status {} or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6477> utiny value As byte endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6478> union iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6478> {field (By field)} <byte 6478> tbits:1 io0_output Bit 0 I/O0 output tbits:1 io1_output Bit 1 I/O1 output tbits:1 io2_output Bit 2 I/O2 output tbits:1 io3_output Bit 3 I/O3 output tbits:1 io0_enable Bit 4 I/O0 enable tbits:1 io1_enable Bit 5 I/O1 enable tbits:1 io2_enable Bit 6 I/O2 enable tbits:1 io3_enable Bit 7 I/O3 enable {} or iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6478> utiny value As byte endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6479> union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Gene rator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) <byte 6479> union ipr (Offset 0x84) R Input Port Register <byte 6479> {field (By field)} <byte 6479> tbits:1 io0_state Bit 0 I/O0 state tbits:1 io1_state Bit 1 I/O1 state tbits:1 io2_state Bit 2 I/O2 state tbits:1 io3_state Bit 3 I/O3 state tbits:1 io0_change Bit 4 I/O0 change tbits:1 io1_change Bit 5 I/O1 change tbits:1 io2_change Bit 6 I/O2 change tbits:1 io3_change Bit 7 I/O3 change {} or ipr (Offset 0x84) R Input Port Register <byte 6479> utiny value As byte endunion ipr (Offset 0x84) R Input Port Register or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6479> union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UART A only) <byte 6479> {field (By field)}

<byte 6479> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA o nly) <byte 6479> utiny value As byte endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (U ARTA only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6479> union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UART B only) <byte 6479> {field (By field)} <byte 6479> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB o nly) <byte 6479> utiny value As byte endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (U ARTB only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6479> utiny value As byte endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate G enerator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generat or Timer Register Lower a (UARTB only) <byte 6480> union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) ( Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6480> union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6480> {field (By field)} <byte 6480> tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0) tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1) tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2) tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3) {} or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6480> utiny value As byte endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA onl y) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6480> union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6480> {field (By field)}

<byte 6480> tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0) tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1) tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2) tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3) {} or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6480> utiny value As byte endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only ) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6480> utiny value As byte endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only ) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6481> {rsvd3 ((Offset 0x8A) NA Reserved)} <byte 6481> utiny value {} <byte 6482> {rsvd2 ((Offset 0x89) NA Reserved)} <byte 6482> utiny value {} <byte 6483> {rsvd1 ((Offset 0x88) NA Reserved)} <byte 6483> utiny value {} <byte 6484> union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6484> union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6484> {field (By field)} <byte 6484> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6484> utiny value As byte endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6484> union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6484> {field (By field)} <byte 6484> tbits:3 other_types Bit 2:0 Other types tbits:2 reserved Bit 4:3 Reserved tbits:1 tx_interrupt Bit 5 Transmitter Interrupt

tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt {} or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6484> utiny value As byte endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6484> utiny value As byte endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6485> union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x 8E) W Global Transmit FIFO Register (UARTA only) <byte 6485> union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6485> {field (By field)} <byte 6485> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6485> utiny value As byte endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6485> union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6485> {field (By field)} <byte 6485> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6485> utiny value As byte endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6485> utiny value As byte endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6486> union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8 D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6486> union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6486> {field (By field)} <byte 6486> tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code tbits:4 reserved Bits 7:4 Reserved {} or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6486> utiny value As byte

endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6486> union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UART A only) <byte 6486> {field (By field)} <byte 6486> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA o nly) <byte 6486> utiny value As byte endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (U ARTA only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6486> union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UART B only) <byte 6486> {field (By field)} <byte 6486> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB o nly) <byte 6486> utiny value As byte endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (U ARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6486> utiny value As byte endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6487> union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C ) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Cu rrent Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Time r Control Register (UARTB only) <byte 6487> union cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6487> {field (By field)} <byte 6487> tbits:3 channel_number Bits 2:0 Channel number tbits:3 current_byte_count_type Bits 5:3 Current byte count/type tbits:2 type Bits 7:6 Type {} or cir (Offset 0x8C) R Current Interrupt Register (UARTA only)

<byte 6487> utiny value As byte endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6487> union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6487> {field (By field)} <byte 6487> tbits:3 channel_code Bits 2:0 Channel code tbits:5 reserved Bits 7:3 Reserved {} or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6487> utiny value As byte endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6487> {ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))} <byte 6487> utiny value {} or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6487> union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) <byte 6487> {field (By field)} <byte 6487> tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control {} or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB on ly) <byte 6487> utiny value As byte endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UA RTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6487> utiny value As byte endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0 x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator T imer Control Register (UARTB only) {}

<byte 6488> {tachyon (Tachyon DX2+ register save area)} <byte 6488> union portcorr[0] Port Correlation <byte 6488> ulong portcorra Port Correlation As Longword or portcorr[0] Port Correlation <byte 6488> {portcorr (Port Correlation By Field)} <byte 6488> utiny real_port Real hardware port number <byte 6489> utiny port_type Port type <byte 6490> ushort reserved Reserved {} endunion portcorr[0] Port Correlation <byte 6492> union portcorr[1] Port Correlation <byte 6492> ulong portcorra Port Correlation As Longword or portcorr[1] Port Correlation <byte 6492> {portcorr (Port Correlation By Field)} <byte 6492> utiny real_port Real hardware port number <byte 6493> utiny port_type Port type <byte 6494> ushort reserved Reserved {} endunion portcorr[1] Port Correlation <byte 6496> union portcorr[2] Port Correlation <byte 6496> ulong portcorra Port Correlation As Longword or portcorr[2] Port Correlation <byte 6496> {portcorr (Port Correlation By Field)} <byte 6496> utiny real_port Real hardware port number <byte 6497> utiny port_type Port type <byte 6498> ushort reserved Reserved {} endunion portcorr[2] Port Correlation <byte 6500> union portcorr[3] Port Correlation <byte 6500> ulong portcorra Port Correlation As Longword or portcorr[3] Port Correlation <byte 6500> {portcorr (Port Correlation By Field)} <byte 6500> utiny real_port Real hardware port number <byte 6501> utiny port_type Port type <byte 6502> ushort reserved Reserved

{} endunion portcorr[3] Port Correlation <byte 6504> union portcorr[4] Port Correlation <byte 6504> ulong portcorra Port Correlation As Longword or portcorr[4] Port Correlation <byte 6504> {portcorr (Port Correlation By Field)} <byte 6504> utiny real_port Real hardware port number <byte 6505> utiny port_type Port type <byte 6506> ushort reserved Reserved {} endunion portcorr[4] Port Correlation <byte 6508> union portcorr[5] Port Correlation <byte 6508> ulong portcorra Port Correlation As Longword or portcorr[5] Port Correlation <byte 6508> {portcorr (Port Correlation By Field)} <byte 6508> utiny real_port Real hardware port number <byte 6509> utiny port_type Port type <byte 6510> ushort reserved Reserved {} endunion portcorr[5] Port Correlation <byte 6512> union portcorr[6] Port Correlation <byte 6512> ulong portcorra Port Correlation As Longword or portcorr[6] Port Correlation <byte 6512> {portcorr (Port Correlation By Field)} <byte 6512> utiny real_port Real hardware port number <byte 6513> utiny port_type Port type <byte 6514> ushort reserved Reserved {} endunion portcorr[6] Port Correlation <byte 6516> union portcorr[7] Port Correlation <byte 6516> ulong portcorra Port Correlation As Longword or portcorr[7] Port Correlation <byte 6516> {portcorr (Port Correlation By Field)} <byte 6516> utiny real_port Real hardware port number <byte 6517> utiny port_type Port type <byte 6518> ushort reserved Reserved

{} endunion portcorr[7] Port Correlation <byte 6520> union portcorr[8] Port Correlation <byte 6520> ulong portcorra Port Correlation As Longword or portcorr[8] Port Correlation <byte 6520> {portcorr (Port Correlation By Field)} <byte 6520> utiny real_port Real hardware port number <byte 6521> utiny port_type Port type <byte 6522> ushort reserved Reserved {} endunion portcorr[8] Port Correlation <byte 6524> union portcorr[9] Port Correlation <byte 6524> ulong portcorra Port Correlation As Longword or portcorr[9] Port Correlation <byte 6524> {portcorr (Port Correlation By Field)} <byte 6524> utiny real_port Real hardware port number <byte 6525> utiny port_type Port type <byte 6526> ushort reserved Reserved {} endunion portcorr[9] Port Correlation <byte 6528> union portcorr[10] Port Correlation <byte 6528> ulong portcorra Port Correlation As Longword or portcorr[10] Port Correlation <byte 6528> {portcorr (Port Correlation By Field)} <byte 6528> utiny real_port Real hardware port number <byte 6529> utiny port_type Port type <byte 6530> ushort reserved Reserved {} endunion portcorr[10] Port Correlation <byte 6532> union portcorr[11] Port Correlation <byte 6532> ulong portcorra Port Correlation As Longword or portcorr[11] Port Correlation <byte 6532> {portcorr (Port Correlation By Field)} <byte 6532> utiny real_port Real hardware port number <byte 6533> utiny port_type Port type <byte 6534> ushort reserved Reserved

{} endunion portcorr[11] Port Correlation <byte 6536> union csr[0] Tachyon DX2+ CSR Registers <byte 6536> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[0] Tachyon DX2+ CSR Registers <byte 6536> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 6536> union erq_base (Offset 000) ERQ Base (write only) <byte 6536> {field (By field)} <byte 6536> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 6536> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 6540> union erq_len (Offset 004) ERQ Length (write only) <byte 6540> {field (By field)} <byte 6540> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 6540> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 6544> union erq_prod (Offset 008) ERQ Producer Index <byte 6544> {field (By field)} <byte 6544> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 6544> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 6548> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 6548> {field (By field)} <byte 6548> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 6548> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 6552> union erq_cons (Offset 010) ERQ Consumer Index <byte 6552> {field (By field)} <byte 6552>

lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 6552> ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index <byte 6556> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 6556> ulong value {} <byte 6560> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 6560> ulong value {} <byte 6564> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 6564> ulong value {} <byte 6568> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 6568> ulong value {} <byte 6572> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 6572> ulong value {} <byte 6576> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 6576> ulong value {} <byte 6580> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 6580> ulong value {} <byte 6584> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 6584> ulong value {} <byte 6588> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 6588> ulong value {} <byte 6592> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 6592> ulong value {} <byte 6596> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 6596>

ulong value {} <byte 6600> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 6600> ulong value {} <byte 6604> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 6604> ulong value {} <byte 6608> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 6608> ulong value {} <byte 6612> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 6612> ulong value {} <byte 6616> union sfq_base (Offset 050) SFQ Base (write only) <byte 6616> {field (By field)} <byte 6616> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 6616> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 6620> union sfq_len (Offset 054) SFQ Length (write only) <byte 6620> {field (By field)} <byte 6620> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 6620> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 6624> union sfq_cons (Offset 058) SFQ Consumer Index <byte 6624> {field (By field)} <byte 6624> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 6624> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 6628> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 6628>

ulong value {} <byte 6632> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 6632> ulong value {} <byte 6636> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 6636> ulong value {} <byte 6640> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 6640> ulong value {} <byte 6644> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 6644> ulong value {} <byte 6648> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 6648> ulong value {} <byte 6652> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 6652> ulong value {} <byte 6656> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 6656> ulong value {} <byte 6660> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 6660> {field (By field)} <byte 6660> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 6660> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 6664> union imq_base (Offset 080) IMQ Base (write only) <byte 6664> {field (By field)} <byte 6664> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 6664>

ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 6668> union imq_len (Offset 084) IMQ Length (write only) <byte 6668> {field (By field)} <byte 6668> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 6668> ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 6672> union imq_cons (Offset 088) IMQ Consumer Index <byte 6672> {field (By field)} <byte 6672> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 6672> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 6676> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 6676> {field (By field)} <byte 6676> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 6676> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 6680> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 6680> ulong value {} <byte 6684> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 6684> ulong value {} <byte 6688> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 6688> ulong value {} <byte 6692> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 6692> ulong value {} <byte 6696> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 6696>

ulong value {} <byte 6700> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 6700> ulong value {} <byte 6704> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 6704> ulong value {} <byte 6708> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 6708> ulong value {} <byte 6712> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 6712> ulong value {} <byte 6716> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 6716> ulong value {} <byte 6720> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 6720> ulong value {} <byte 6724> {rsvd3[11] ((Offset 090-0FC) Reserved)} <byte 6724> ulong value {} <byte 6728> {rsvd3[12] ((Offset 090-0FC) Reserved)} <byte 6728> ulong value {} <byte 6732> {rsvd3[13] ((Offset 090-0FC) Reserved)} <byte 6732> ulong value {} <byte 6736> {rsvd3[14] ((Offset 090-0FC) Reserved)} <byte 6736> ulong value {} <byte 6740> {rsvd3[15] ((Offset 090-0FC) Reserved)} <byte 6740> ulong value {} <byte 6744> {rsvd3[16] ((Offset 090-0FC) Reserved)} <byte 6744>

ulong value {} <byte 6748> {rsvd3[17] ((Offset 090-0FC) Reserved)} <byte 6748> ulong value {} <byte 6752> {rsvd3[18] ((Offset 090-0FC) Reserved)} <byte 6752> ulong value {} <byte 6756> {rsvd3[19] ((Offset 090-0FC) Reserved)} <byte 6756> ulong value {} <byte 6760> {rsvd3[20] ((Offset 090-0FC) Reserved)} <byte 6760> ulong value {} <byte 6764> {rsvd3[21] ((Offset 090-0FC) Reserved)} <byte 6764> ulong value {} <byte 6768> {rsvd3[22] ((Offset 090-0FC) Reserved)} <byte 6768> ulong value {} <byte 6772> {rsvd3[23] ((Offset 090-0FC) Reserved)} <byte 6772> ulong value {} <byte 6776> {rsvd3[24] ((Offset 090-0FC) Reserved)} <byte 6776> ulong value {} <byte 6780> {rsvd3[25] ((Offset 090-0FC) Reserved)} <byte 6780> ulong value {} <byte 6784> {rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 6784> ulong value {} <byte 6788> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 6788> ulong value {} <byte 6792> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 6792>

{field (By field)} <byte 6792> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 6792> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 6796> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 6796> {field (By field)} <byte 6796> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 6796> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 6800>

{rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 6800> ulong value {} <byte 6804> {rsvd3a[1] ((Offset 108-10f) Reserved)} <byte 6804> ulong value {} <byte 6808> union sfp_cmd_status (Offset 110) SFP command and status <byte 6808> {field (No description available)} <byte 6808> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 6808> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 6812> union sfp_data (Offset 114) SFP data <byte 6812> {field (By field)} <byte 6812> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 6812> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 6816> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 6816> {field (By field)} <byte 6816> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS

lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 6816> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 6820> union fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 6820> {field (By field)} <byte 6820> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 6820> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 6824> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 6824> ulong value {} <byte 6828> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 6828> ulong value {} <byte 6832> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 6832> ulong value {} <byte 6836> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 6836> ulong value {} <byte 6840> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 6840> ulong value {} <byte 6844> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 6844> ulong value {} <byte 6848> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 6848> ulong value {} <byte 6852> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 6852> ulong value

{} <byte 6856> union sest_base (Offset 140) SEST Base (write only) <byte 6856> {field (By field)} <byte 6856> lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 6856> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) <byte 6860> union sest_len (Offset 144) SEST Length (write only) <byte 6860> {field (By field)} <byte 6860> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 6860> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 6864> {rsvd4 ((Offset 148) Reserved)} <byte 6864> ulong value {} <byte 6868> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 6868> {field (By field)} <byte 6868> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 6868> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 6872> union prog_addr (Offset 150) Programmable Address register <byte 6872> {field (By field)} <byte 6872> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 6872> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 6876> union prog_data (Offset 154) programmable data register <byte 6876> {field (By field)} <byte 6876> lbits:32 pdr Programmable data

{} or prog_data (Offset 154) programmable data register <byte 6876> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 6880> {rsvd5[0] ((Offset 158-15F) Reserved)} <byte 6880> ulong value {} <byte 6884> {rsvd5[1] ((Offset 158-15F) Reserved)} <byte 6884> ulong value {} <byte 6888> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 6888> {field (By field)} <byte 6888> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 6888> ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 6892> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 6892> {field (By field)} <byte 6892> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 6892> ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 6896> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 6896> {field (By field)} <byte 6896> lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 6896> ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 6900> union my_id (Offset 16C) My ID <byte 6900> {field (By field)} <byte 6900> lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 6900> ulong value As longword

endunion my_id (Offset 16C) My ID <byte 6904> union gpio (Offset 170) General Purpose I/O <byte 6904> {field (By field)} <byte 6904> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O <byte 6904> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 6908> {rsvd6a ((Offset 174-177) Reserved)} <byte 6908> ulong value {} <byte 6912> union edc_config (Offset 178) EDC Configuration Register <byte 6912> {field (By field)} <byte 6912> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register <byte 6912> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 6916> union dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 6916> {field (By field)} <byte 6916> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 6916> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3

<byte 6920> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 6920> {field (By field)} <byte 6920> lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 6920> ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 6924> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 6924> {field (By field)} <byte 6924> lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 6924> ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 6928> union tach_control (Offset 188) Tachyon DX2+ Control <byte 6928> {field (By field)} <byte 6928> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved

lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control <byte 6928> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 6932> union tach_status (Offset 18C) Tachyon DX2+ Status <byte 6932> {field (By field)} <byte 6932> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 6932> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status <byte 6936> {rsvd7 ((Offset 190) Reserved)} <byte 6936> ulong value {} <byte 6940> union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 6940> {field (By field)} <byte 6940> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 6940> ulong value As longword

endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 6944> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 6944> {field (By field)} <byte 6944> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 6944> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 6948> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 6948> {field (By field)} <byte 6948> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 6948> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 6952> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 6952> {field (By field)} <byte 6952> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 6952> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 6956> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 6956> {field (By field)} <byte 6956> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 6956> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 6960> union up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 6960> {field (By field)} <byte 6960> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address

{} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 6960> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 6964> union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 6964> {field (By field)} <byte 6964> lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 6964> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 6968> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 6968> {field (By field)} <byte 6968> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 6968> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 6972> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2

<byte 6972> {field (By field)} <byte 6972> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 6972> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 6976> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 6976> {field (By field)} <byte 6976> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information

lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 6976> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 6980> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 6980> {field (By field)} <byte 6980> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {}

or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 6980> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 6984> union fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 6984> {field (By field)} <byte 6984> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 6984> ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 6988> union fm_control (Offset 1C4) Frame Manager Control <byte 6988> {field (By field)} <byte 6988> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 6988> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control <byte 6992> union fm_status (Offset 1C8) Frame Manager Status <byte 6992> {field (By field)} <byte 6992> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure

lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 6992> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status <byte 6996> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 6996> {field (By field)} <byte 6996> lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 6996> ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 7000> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 7000> {field (By field)} <byte 7000> lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 7000> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 7004> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 7004> {field (By field)} <byte 7004> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa

{} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 7004> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 7008> union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 7008> {field (By field)} <byte 7008> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 7008> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 7012> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 7012> {field (By field)} <byte 7012> lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 7012> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 7016> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 7016> {field (By field)} <byte 7016> lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 7016> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 7020> union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 7020> {field (By field)} <byte 7020> lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 7020> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 7024> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 7024> {field (By field)} <byte 7024> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed

lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 7024> ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 7028> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 7028> {field (By field)} <byte 7028> lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 7028> ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 7032> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 7032> {field (By field)} <byte 7032> lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 7032> ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 7036> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 7036> {field (By field)} <byte 7036> lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 7036> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 7040> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED

<byte 7040> {field (By field)} <byte 7040> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 7040> utiny value {} <byte 7041> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 7041> utiny value {} <byte 7042> union romctr (Offset 1FA) PCI ROM Control <byte 7042> {field (By field)} <byte 7042> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 7042> utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 7043> union mctr (Offset 1FB) PCI Master Control <byte 7043> {field (By field)} <byte 7043> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control <byte 7043> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 7040> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 7044> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 7044> {field (By field)} <byte 7044> union softrst (Offset 1FC) PCI Interface Reset Control <byte 7044> {field (By field)} <byte 7044> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 7044> utiny value As byte

endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 7045> union intpend (Offset 1FD) PCI Interrupt Pending <byte 7045> {field (By field)} <byte 7045> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending <byte 7045> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 7046> union inten (Offset 1FE) PCI Interrupt Enable <byte 7046> {field (By field)} <byte 7046> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable <byte 7046> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 7047> union intstat (Offset 1FF) PCI Interrupt Status <byte 7047> {field (By field)} <byte 7047> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 7047> utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 7044> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[0] Tachyon DX2+ CSR Registers <byte 7048> union csr[1] Tachyon DX2+ CSR Registers <byte 7048> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords

or csr[1] Tachyon DX2+ CSR Registers <byte 7048> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 7048> union erq_base (Offset 000) ERQ Base (write only) <byte 7048> {field (By field)} <byte 7048> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 7048> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 7052> union erq_len (Offset 004) ERQ Length (write only) <byte 7052> {field (By field)} <byte 7052> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 7052> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 7056> union erq_prod (Offset 008) ERQ Producer Index <byte 7056> {field (By field)} <byte 7056> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 7056> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 7060> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 7060> {field (By field)} <byte 7060> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 7060> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 7064> union erq_cons (Offset 010) ERQ Consumer Index <byte 7064> {field (By field)} <byte 7064> lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 7064> ulong value As longword

endunion erq_cons (Offset 010) ERQ Consumer Index <byte 7068> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 7068> ulong value {} <byte 7072> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 7072> ulong value {} <byte 7076> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 7076> ulong value {} <byte 7080> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 7080> ulong value {} <byte 7084> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 7084> ulong value {} <byte 7088> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 7088> ulong value {} <byte 7092> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 7092> ulong value {} <byte 7096> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 7096> ulong value {} <byte 7100> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 7100> ulong value {} <byte 7104> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 7104> ulong value {} <byte 7108> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 7108> ulong value {} <byte 7112> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 7112> ulong value

{} <byte 7116> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 7116> ulong value {} <byte 7120> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 7120> ulong value {} <byte 7124> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 7124> ulong value {} <byte 7128> union sfq_base (Offset 050) SFQ Base (write only) <byte 7128> {field (By field)} <byte 7128> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 7128> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 7132> union sfq_len (Offset 054) SFQ Length (write only) <byte 7132> {field (By field)} <byte 7132> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 7132> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 7136> union sfq_cons (Offset 058) SFQ Consumer Index <byte 7136> {field (By field)} <byte 7136> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 7136> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 7140> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 7140> ulong value {} <byte 7144> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 7144> ulong value

{} <byte 7148> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 7148> ulong value {} <byte 7152> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 7152> ulong value {} <byte 7156> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 7156> ulong value {} <byte 7160> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 7160> ulong value {} <byte 7164> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 7164> ulong value {} <byte 7168> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 7168> ulong value {} <byte 7172> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 7172> {field (By field)} <byte 7172> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 7172> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 7176> union imq_base (Offset 080) IMQ Base (write only) <byte 7176> {field (By field)} <byte 7176> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 7176> ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 7180> union imq_len (Offset 084) IMQ Length (write only) <byte 7180> {field (By field)}

<byte 7180> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 7180> ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 7184> union imq_cons (Offset 088) IMQ Consumer Index <byte 7184> {field (By field)} <byte 7184> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 7184> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 7188> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 7188> {field (By field)} <byte 7188> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 7188> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 7192> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 7192> ulong value {} <byte 7196> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 7196> ulong value {} <byte 7200> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 7200> ulong value {} <byte 7204> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 7204> ulong value {} <byte 7208> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 7208> ulong value {} <byte 7212> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 7212> ulong value

{} <byte 7216> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 7216> ulong value {} <byte 7220> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 7220> ulong value {} <byte 7224> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 7224> ulong value {} <byte 7228> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 7228> ulong value {} <byte 7232> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 7232> ulong value {} <byte 7236> {rsvd3[11] ((Offset 090-0FC) Reserved)} <byte 7236> ulong value {} <byte 7240> {rsvd3[12] ((Offset 090-0FC) Reserved)} <byte 7240> ulong value {} <byte 7244> {rsvd3[13] ((Offset 090-0FC) Reserved)} <byte 7244> ulong value {} <byte 7248> {rsvd3[14] ((Offset 090-0FC) Reserved)} <byte 7248> ulong value {} <byte 7252> {rsvd3[15] ((Offset 090-0FC) Reserved)} <byte 7252> ulong value {} <byte 7256> {rsvd3[16] ((Offset 090-0FC) Reserved)} <byte 7256> ulong value {} <byte 7260> {rsvd3[17] ((Offset 090-0FC) Reserved)} <byte 7260> ulong value

{} <byte 7264> {rsvd3[18] ((Offset 090-0FC) Reserved)} <byte 7264> ulong value {} <byte 7268> {rsvd3[19] ((Offset 090-0FC) Reserved)} <byte 7268> ulong value {} <byte 7272> {rsvd3[20] ((Offset 090-0FC) Reserved)} <byte 7272> ulong value {} <byte 7276> {rsvd3[21] ((Offset 090-0FC) Reserved)} <byte 7276> ulong value {} <byte 7280> {rsvd3[22] ((Offset 090-0FC) Reserved)} <byte 7280> ulong value {} <byte 7284> {rsvd3[23] ((Offset 090-0FC) Reserved)} <byte 7284> ulong value {} <byte 7288> {rsvd3[24] ((Offset 090-0FC) Reserved)} <byte 7288> ulong value {} <byte 7292> {rsvd3[25] ((Offset 090-0FC) Reserved)} <byte 7292> ulong value {} <byte 7296> {rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 7296> ulong value {} <byte 7300> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 7300> ulong value {} <byte 7304> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 7304> {field (By field)} <byte 7304> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved

lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 7304> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 7308> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 7308> {field (By field)} <byte 7308> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 7308> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 7312> {rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 7312> ulong value {} <byte 7316> {rsvd3a[1] ((Offset 108-10f) Reserved)}

<byte 7316> ulong value {} <byte 7320> union sfp_cmd_status (Offset 110) SFP command and status <byte 7320> {field (No description available)} <byte 7320> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 7320> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 7324> union sfp_data (Offset 114) SFP data <byte 7324> {field (By field)} <byte 7324> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 7324> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 7328> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 7328> {field (By field)} <byte 7328> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {}

or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 7328> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 7332> union fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 7332> {field (By field)} <byte 7332> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 7332> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 7336> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 7336> ulong value {} <byte 7340> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 7340> ulong value {} <byte 7344> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 7344> ulong value {} <byte 7348> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 7348> ulong value {} <byte 7352> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 7352> ulong value {} <byte 7356> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 7356> ulong value {} <byte 7360> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 7360> ulong value {} <byte 7364> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 7364> ulong value {} <byte 7368> union sest_base (Offset 140) SEST Base (write only) <byte 7368> {field (By field)} <byte 7368>

lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 7368> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) <byte 7372> union sest_len (Offset 144) SEST Length (write only) <byte 7372> {field (By field)} <byte 7372> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 7372> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 7376> {rsvd4 ((Offset 148) Reserved)} <byte 7376> ulong value {} <byte 7380> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 7380> {field (By field)} <byte 7380> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 7380> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 7384> union prog_addr (Offset 150) Programmable Address register <byte 7384> {field (By field)} <byte 7384> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 7384> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 7388> union prog_data (Offset 154) programmable data register <byte 7388> {field (By field)} <byte 7388> lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register <byte 7388> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 7392>

{rsvd5[0] ((Offset 158-15F) Reserved)} <byte 7392> ulong value {} <byte 7396> {rsvd5[1] ((Offset 158-15F) Reserved)} <byte 7396> ulong value {} <byte 7400> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 7400> {field (By field)} <byte 7400> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 7400> ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 7404> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 7404> {field (By field)} <byte 7404> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 7404> ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 7408> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 7408> {field (By field)} <byte 7408> lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 7408> ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 7412> union my_id (Offset 16C) My ID <byte 7412> {field (By field)} <byte 7412> lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 7412> ulong value As longword endunion my_id (Offset 16C) My ID <byte 7416> union gpio (Offset 170) General Purpose I/O <byte 7416> {field (By field)} <byte 7416>

lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O <byte 7416> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 7420> {rsvd6a ((Offset 174-177) Reserved)} <byte 7420> ulong value {} <byte 7424> union edc_config (Offset 178) EDC Configuration Register <byte 7424> {field (By field)} <byte 7424> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register <byte 7424> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 7428> union dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 7428> {field (By field)} <byte 7428> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 7428> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 7432> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 7432> {field (By field)} <byte 7432> lbits:9 pfs Programmable Frame Size

lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 7432> ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 7436> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 7436> {field (By field)} <byte 7436> lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 7436> ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 7440> union tach_control (Offset 188) Tachyon DX2+ Control <byte 7440> {field (By field)} <byte 7440> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {}

or tach_control (Offset 188) Tachyon DX2+ Control <byte 7440> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 7444> union tach_status (Offset 18C) Tachyon DX2+ Status <byte 7444> {field (By field)} <byte 7444> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 7444> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status <byte 7448> {rsvd7 ((Offset 190) Reserved)} <byte 7448> ulong value {} <byte 7452> union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 7452> {field (By field)} <byte 7452> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 7452> ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 7456> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 7456> {field (By field)} <byte 7456>

lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 7456> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 7460> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 7460> {field (By field)} <byte 7460> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 7460> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 7464> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 7464> {field (By field)} <byte 7464> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 7464> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 7468> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 7468> {field (By field)} <byte 7468> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 7468> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 7472> union up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 7472> {field (By field)} <byte 7472> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 7472> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 7476>

union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 7476> {field (By field)} <byte 7476> lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 7476> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 7480> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 7480> {field (By field)} <byte 7480> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 7480> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 7484> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 7484> {field (By field)} <byte 7484> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information

lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 7484> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 7488> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 7488> {field (By field)} <byte 7488> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information

lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 7488> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 7492> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 7492> {field (By field)} <byte 7492> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 7492> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 7496> union fm_config1 (Offset 1C0) Frame Manager Configuration 1

<byte 7496> {field (By field)} <byte 7496> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 7496> ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 7500> union fm_control (Offset 1C4) Frame Manager Control <byte 7500> {field (By field)} <byte 7500> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 7500> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control <byte 7504> union fm_status (Offset 1C8) Frame Manager Status <byte 7504> {field (By field)} <byte 7504> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out

lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 7504> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status <byte 7508> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 7508> {field (By field)} <byte 7508> lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 7508> ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 7512> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 7512> {field (By field)} <byte 7512> lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 7512> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 7516> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 7516> {field (By field)} <byte 7516> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 7516> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 7520>

union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 7520> {field (By field)} <byte 7520> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 7520> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 7524> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 7524> {field (By field)} <byte 7524> lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 7524> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 7528> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 7528> {field (By field)} <byte 7528> lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 7528> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 7532> union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 7532> {field (By field)} <byte 7532> lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 7532> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 7536> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 7536> {field (By field)} <byte 7536> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 7536> ulong value As longword

endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 7540> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 7540> {field (By field)} <byte 7540> lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 7540> ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 7544> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 7544> {field (By field)} <byte 7544> lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 7544> ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 7548> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 7548> {field (By field)} <byte 7548> lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 7548> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 7552> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 7552> {field (By field)} <byte 7552> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 7552> utiny value

{} <byte 7553> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 7553> utiny value {} <byte 7554> union romctr (Offset 1FA) PCI ROM Control <byte 7554> {field (By field)} <byte 7554> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 7554> utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 7555> union mctr (Offset 1FB) PCI Master Control <byte 7555> {field (By field)} <byte 7555> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control <byte 7555> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 7552> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 7556> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 7556> {field (By field)} <byte 7556> union softrst (Offset 1FC) PCI Interface Reset Control <byte 7556> {field (By field)} <byte 7556> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 7556> utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 7557> union intpend (Offset 1FD) PCI Interrupt Pending <byte 7557> {field (By field)} <byte 7557>

tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending <byte 7557> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 7558> union inten (Offset 1FE) PCI Interrupt Enable <byte 7558> {field (By field)} <byte 7558> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable <byte 7558> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 7559> union intstat (Offset 1FF) PCI Interrupt Status <byte 7559> {field (By field)} <byte 7559> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 7559> utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 7556> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[1] Tachyon DX2+ CSR Registers <byte 7560> union csr[2] Tachyon DX2+ CSR Registers <byte 7560> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[2] Tachyon DX2+ CSR Registers <byte 7560> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 7560> union erq_base (Offset 000) ERQ Base (write only) <byte 7560>

{field (By field)} <byte 7560> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 7560> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 7564> union erq_len (Offset 004) ERQ Length (write only) <byte 7564> {field (By field)} <byte 7564> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 7564> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 7568> union erq_prod (Offset 008) ERQ Producer Index <byte 7568> {field (By field)} <byte 7568> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 7568> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 7572> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 7572> {field (By field)} <byte 7572> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 7572> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 7576> union erq_cons (Offset 010) ERQ Consumer Index <byte 7576> {field (By field)} <byte 7576> lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 7576> ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index <byte 7580> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 7580> ulong value {}

<byte 7584> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 7584> ulong value {} <byte 7588> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 7588> ulong value {} <byte 7592> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 7592> ulong value {} <byte 7596> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 7596> ulong value {} <byte 7600> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 7600> ulong value {} <byte 7604> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 7604> ulong value {} <byte 7608> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 7608> ulong value {} <byte 7612> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 7612> ulong value {} <byte 7616> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 7616> ulong value {} <byte 7620> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 7620> ulong value {} <byte 7624> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 7624> ulong value {} <byte 7628> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 7628> ulong value {}

<byte 7632> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 7632> ulong value {} <byte 7636> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 7636> ulong value {} <byte 7640> union sfq_base (Offset 050) SFQ Base (write only) <byte 7640> {field (By field)} <byte 7640> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 7640> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 7644> union sfq_len (Offset 054) SFQ Length (write only) <byte 7644> {field (By field)} <byte 7644> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 7644> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 7648> union sfq_cons (Offset 058) SFQ Consumer Index <byte 7648> {field (By field)} <byte 7648> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 7648> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 7652> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 7652> ulong value {} <byte 7656> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 7656> ulong value {} <byte 7660> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 7660> ulong value {}

<byte 7664> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 7664> ulong value {} <byte 7668> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 7668> ulong value {} <byte 7672> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 7672> ulong value {} <byte 7676> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 7676> ulong value {} <byte 7680> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 7680> ulong value {} <byte 7684> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 7684> {field (By field)} <byte 7684> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 7684> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 7688> union imq_base (Offset 080) IMQ Base (write only) <byte 7688> {field (By field)} <byte 7688> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 7688> ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 7692> union imq_len (Offset 084) IMQ Length (write only) <byte 7692> {field (By field)} <byte 7692> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 7692>

ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 7696> union imq_cons (Offset 088) IMQ Consumer Index <byte 7696> {field (By field)} <byte 7696> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 7696> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 7700> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 7700> {field (By field)} <byte 7700> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 7700> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 7704> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 7704> ulong value {} <byte 7708> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 7708> ulong value {} <byte 7712> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 7712> ulong value {} <byte 7716> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 7716> ulong value {} <byte 7720> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 7720> ulong value {} <byte 7724> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 7724> ulong value {} <byte 7728> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 7728> ulong value {}

<byte 7732> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 7732> ulong value {} <byte 7736> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 7736> ulong value {} <byte 7740> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 7740> ulong value {} <byte 7744> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 7744> ulong value {} <byte 7748> {rsvd3[11] ((Offset 090-0FC) Reserved)} <byte 7748> ulong value {} <byte 7752> {rsvd3[12] ((Offset 090-0FC) Reserved)} <byte 7752> ulong value {} <byte 7756> {rsvd3[13] ((Offset 090-0FC) Reserved)} <byte 7756> ulong value {} <byte 7760> {rsvd3[14] ((Offset 090-0FC) Reserved)} <byte 7760> ulong value {} <byte 7764> {rsvd3[15] ((Offset 090-0FC) Reserved)} <byte 7764> ulong value {} <byte 7768> {rsvd3[16] ((Offset 090-0FC) Reserved)} <byte 7768> ulong value {} <byte 7772> {rsvd3[17] ((Offset 090-0FC) Reserved)} <byte 7772> ulong value {} <byte 7776> {rsvd3[18] ((Offset 090-0FC) Reserved)} <byte 7776> ulong value {}

<byte 7780> {rsvd3[19] ((Offset 090-0FC) Reserved)} <byte 7780> ulong value {} <byte 7784> {rsvd3[20] ((Offset 090-0FC) Reserved)} <byte 7784> ulong value {} <byte 7788> {rsvd3[21] ((Offset 090-0FC) Reserved)} <byte 7788> ulong value {} <byte 7792> {rsvd3[22] ((Offset 090-0FC) Reserved)} <byte 7792> ulong value {} <byte 7796> {rsvd3[23] ((Offset 090-0FC) Reserved)} <byte 7796> ulong value {} <byte 7800> {rsvd3[24] ((Offset 090-0FC) Reserved)} <byte 7800> ulong value {} <byte 7804> {rsvd3[25] ((Offset 090-0FC) Reserved)} <byte 7804> ulong value {} <byte 7808> {rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 7808> ulong value {} <byte 7812> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 7812> ulong value {} <byte 7816> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 7816> {field (By field)} <byte 7816> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode

lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 7816> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 7820> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 7820> {field (By field)} <byte 7820> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 7820> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 7824> {rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 7824> ulong value {} <byte 7828> {rsvd3a[1] ((Offset 108-10f) Reserved)} <byte 7828> ulong value {} <byte 7832> union sfp_cmd_status (Offset 110) SFP command and status <byte 7832>

{field (No description available)} <byte 7832> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 7832> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 7836> union sfp_data (Offset 114) SFP data <byte 7836> {field (By field)} <byte 7836> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 7836> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 7840> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 7840> {field (By field)} <byte 7840> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 7840> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 7844> union fm_config5 (Offset 11C) Frame Manager Configuration 5

<byte 7844> {field (By field)} <byte 7844> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 7844> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 7848> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 7848> ulong value {} <byte 7852> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 7852> ulong value {} <byte 7856> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 7856> ulong value {} <byte 7860> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 7860> ulong value {} <byte 7864> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 7864> ulong value {} <byte 7868> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 7868> ulong value {} <byte 7872> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 7872> ulong value {} <byte 7876> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 7876> ulong value {} <byte 7880> union sest_base (Offset 140) SEST Base (write only) <byte 7880> {field (By field)} <byte 7880> lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 7880> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only)

<byte 7884> union sest_len (Offset 144) SEST Length (write only) <byte 7884> {field (By field)} <byte 7884> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 7884> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 7888> {rsvd4 ((Offset 148) Reserved)} <byte 7888> ulong value {} <byte 7892> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 7892> {field (By field)} <byte 7892> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 7892> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 7896> union prog_addr (Offset 150) Programmable Address register <byte 7896> {field (By field)} <byte 7896> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 7896> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 7900> union prog_data (Offset 154) programmable data register <byte 7900> {field (By field)} <byte 7900> lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register <byte 7900> ulong value As longword enduni