Acer Aspire 5235 5535 5735 - Wistron Cathedral Peak II

5
Cathedral Peak II Block Diagram
Project code: 91.4K801.001

PCB P/N
: 48.4K801.0SC
REVISION
: 08219-SC
SYSTEM DC/DC
CLK GEN.
ICS 9LPRS365BKLFT (71.09365.A03)

RTM 875N-606-LFT (71.00875.C03)
3
35
TPS51125
Mobile CPU
PCB STACKUP
THERMAL EMC2102
Penryn 479
21
INPUTS
OUTPUTS
TOP
5V_S5
HOST BUS
DDR2 DIMM1
LCD
GND
INPUTS
1D05V_S0
DCBATOUT
1D8V_S3
LVDS, CRT I/F
6,7,8,9,10,11
DDR_VREF_S3
PCIex1
PCI/PCI BRIDGE
28
88E8071
ACPI 2.0
MIC In
4 SATA
PCIex1
12 USB 2.0/1.1 ports
29
1D8V_S3
LAN
Giga LAN
TXFM
27
DCBATOUT
Kedron a/b/g/n
27
APA205729
Matrix Storage Technology(DO)
29
Winbond
W25X16
16M Bits
KBC
ENE3310
30
17,18,19,20
USB
23
Blue Tooth
23
(USB)
Camera
(USB) 14
Touch
Pad 30
LPC
31
0.35~1.5V
CHARGER
Launch
Buttom
16
39
BQ24745
INPUTS
INT.
KB 30
OUTPUTS
BT+
23
CardReader
Realtek
RTS5158E
24
DCBATOUT
MS/MS Pro/xD
/MMC/SD
5 in 1
om
22
USB
24
ai
l.c
USB
3 Port
tm
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
ho
SATA
Title
Launch Board
LED Board
BLOCK DIAGRAM
16
Size
A3
Document Number
Date: Wednesday, July 16, 2008

5
VCC_CORE_S0
DCBATOUT
HDD SATA
22
34
OUTPUTS
DCBATOUT
DEBUG
CONN.31
SATA
ODD SATA
0.7~1.25V
INPUTS
BIOS
MODEM
MDC Card
VGFXCORE
ISL6266A
LPC BUS
Active Managemnet Technology(DO)
Line Out
(NO SPDIF)
OUTPUTS
CPU DC/DC
Serial Peripheral I/F
INT.SPKR
38
INPUTS
Mini Card
LPC I/F
OP AMP
CFXCORE DC/DC
ISL6263
New card
PCIex1
High Definition Audio
26
PWR SW
TPS2231
27
ETHERNET (10/100/1000MbE)
RJ45
26
25
1D5V_S0
f@
ALC268
36
RT9018A
6 PCIe ports
xa
in
AZALIA
1D8V_S3
C-Link0
ICH9M
Codec
36
RT9026
DDR_VREF_S0
X4 DMI
400MHz
RJ11
OUTPUTS
DDR Memory I/F
16
37
TPS51124
BOTTOM
INTEGRATED GRAHPICS
667/800MHz
INT.MIC
29
SYSTEM DC/DC
14
AGTL+ CPU I/F
13
3D3V_S5
15
Cantiga
DDR2 DIMM2
C
S
S
667/800MHz
12
667/800 MHz
667/800/1067MHz@1.05V
CRT
Rev
SC
Cathedral Peak II
he
667/800 MHz
DCBATOUT
VCC
4, 5
Sheet
1
of
43
ICH9M Functional Strap Definitions

ICH9 EDS 642879 Rev.1.5
Signal
ICH9M Integrated Pull-up

and Pull-down Resistors
page 92
Comment
Usage/When Sampled
ICH9 EDS 642879
HDA_SDOUT
XOR Chain Entrance/

Allows entrance to XOR Chain testing when TP3
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge
Rising Edge of PWROK
of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h). This signal has weak internal pull-down
HDA_SYNC
PCIE config1 bit0,

Rising Edge of PWROK.
This signal has a weak internal pull-down.

Sets bit0 of RPC.PC(Config Registers:Offset 224h)
GNT2#/
GPIO53
PCIE config2 bit2,

GPIO20
Reserved
This signal has a weak internal pull-up.

Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)
This signal should not be pulled high.
GNT1#/
GPIO51
ESI Strap (Server Only) ESI compatible mode is for server platforms only.
This signal should not be pulled low for desttop
and mobile.
SIGNAL
CL_CLK[1:0]
PULL-UP 20K
CL_DATA[1:0]
PULL-UP 20K
CL_RST0#
PULL-UP 20K
DPRSLPVR/GPIO16
PULL-DOWN 20K
ENERGY_DETECT
PULL-UP 20K
HDA_BIT_CLK
PULL-DOWN 20K
HDA_DOCK_EN#/GPIO33
PULL-UP 20K
HDA_RST#
PULL-DOWN 20K
HDA_SDIN[3:0]
PULL-DOWN 20K
HDA_SDOUT
PULL-DOWN 20K
PULL-UP 20K
GPIO[20]
PULL-DOWN 20K
Integrated TPM Enable,

Rising Edge of CLPWROK
Sample low: the Integrated TPM will be disabled.

Sample high: the MCH TPM enable strap is sampled
low and the TPM Disable bit is clear, the
Integrated TPM will be enable.
GPIO[49]
PULL-UP 20K
LDA[3:0]#/FHW[3:0]#
PULL-UP 20K
LAN_RXD[2:0]
PULL-UP 20K
LDRQ[0]
PULL-UP 20K
LDRQ[1]/GPIO23
PULL-UP 20K
PME#
PULL-UP 20K
PWRBTN#
PULL-UP 20K
SATALED#
PULL-UP 15K
GPIO33/
HDA_DOCK
_EN#
HDA_SYNC
Signal has weak internal pull-up. Sets bit 27

of MPC.LR(Device 28:Function 0:Offset D8)
No Reboot.
If sampled high, the system is strapped to the

"No Reboot" mode(ICH9 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.
SPI_CS1#/GPIO58/CLGPIO6
PULL-UP 20K
SPI_MOSI
PULL-DOWN 20K
SPI_MISO
PULL-UP 20K
This signal should not be pull low unless using

XOR Chain testing.
SPKR
PULL-DOWN 20K
TACH_[3:0]
PULL-UP 20K
TP[3]
PULL-UP 20K
USB[11:0][P,N]
PULL-DOWN 15K
Flash Descriptor
Sampled low:the Flash Descriptor Security will be
Security Override Strap overridden. If high,the security measures will be
in effect.This should only be enabled in manufacturing
environments using an external pull-up resister.
iTPM Host
Interface
0 = DMI x2
1 = DMI x4 (Default)
0= The iTPM Host Interface is enabled(Note2)
1=The iTPM Host Interface is disalbed(default)
CFG10
PCIE Loopback enable
CFG[13:12]
XOR/ALL
CFG16
CFG19
0 = Enable (Note 3)
1= Disabled (default)
00 = Reserve
10 = XOR mode Enabled
01 = ALLZ mode Enabled (Note 3)
11 = Disabled (default)
FSB Dynamic ODT
0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled (Default)
DMI Lane Reversal
0 = Normal operation(Default):
Lane Numbered in Order
1 = Reverse Lanes
DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
DMI x2 mode[MCH -> ICH]:(3->0,2->1)
CFG20
Digital Display Port 0 = Only Digital Display Port

(SDVO/DP/iHDMI)
or PCIE is operational (Default)
Concurrent with PCIe 1 =Digital display Port and PCIe are
operting simulataneously via the PEG port
0 =No SDVO Card Present (Default)
SDVO_CTRLDATA
SDVO Present
1 = SDVO Card Present
0 = LFP Disabled (Default)
L_DDC_DATA
Local Flat Panel

(LFP) Present
1= LFP Card Present; PCIE disabled
NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
Flash-decriptor section of the Firmware. This 'Soft-Strap' is
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
DMI x2 Select
PULL-DOWN 20K
GLAN_DOCK#
PCI Express Lane

Reversal. Rising Edge
of PWROK.
XOR Chain Entrance.

CFG5
CFG6
0 = Reverse Lanes,15->0,14->1 ect..

1= Normal operation(Default):Lane
Numbered in order
GNT[3:0]#/GPIO[55,53,51]
TP3
Reserved
CFG[4:3]
CFG8
CFG[15:14]
CFG[18:17]
PCIE Graphics Lane
Controllable via Boot BIOS Destination bit

(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
SPKR
000 = FSB1067
011 = FSB667
010 = FSB800
others = Reserved
The pull-up or pull-down active when configured for native CFG9

GLAN_DOCK# functionality and determined by LAN controller
Boot BIOS Destination

Selection 0:1.
SATALED#
FSB Frequency
Select
CFG[2:0]
0.5
Configuration
0 = Transport Layer Security (TLS) cipher

suite with no confidentiality
1 = TLS cipher suite with
confidentiality (default)
GNT0#:
SPI_CS1#/
GPIO58
DMI Termination Voltage, The signal is required to be low for desktop

applications and required to be high for
mobile applications.
Strap Description
Intel Management
engine Crypto strap
Sampled low:Top-Block Swap mode(inverts A16 for

all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
GPIO49
page 218
Pin Name
CFG7
Top-Block
Swap Override.
Montevina Platform Design guide 22339
Rev.1.5
Resistor Type/Value
GNT3#/
GPIO55
SPI_MOSI
E
CantigaDchipset and ICH9M I/O controller
Hub strapping configuration
SMBus
EMC2102
USB Table
USB
PCIE Routing
LANE1
LAN MARVELL 88E8071
LANE2
MiniCard WLAN
LANE3
NC
LANE4
NC
LANE5
NewCard
LANE6
NC
Pair
USB1
NC
USB2
NC
BAT_SCL
Device
Thermal
KBC
BATTERY
USB3
Bluetooth
NC
MINIC1
Wistron Corporation
WEBCAM

ICH9M
NEW1
10
Card Reader
11
NC
Title
SMBC_ICH
9LPRS365BKLFT
Reference
Size
A3
DDR
Date:
Document Number
Rev
SC
Cathedral Peak II
Wednesday, July 16, 2008
Sheet
of
43
3D3V_S0
3D3V_S0
3D3V_S0
-1
1
2
1
2
1
2
C184
DY
4,7
1
45
44
18 PM_STPPCI#
18 PM_STPCPU#
CPU_SEL2
8
7
6
5
2
R155
RN59
SRN10KJ-6-GP
DY
18 CLK_PWRGD
PCI_STOP#
CPU_STOP#
R150 1
DY 2
475R2F-L1-GP
PCLKCLK2
CPU_SEL2_R
PCLKCLK4
PCLKCLK5
30
18
PCLK_KBC
PCLK_ICH
RN17 1
2
PCLKCLK4
PCLKCLK5
4
3
CK_PWRGD/PD#
8
10
11
12
13
14
PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_SELECT
PCI_F5/ITP_EN
CPU_SEL1
CPU_SEL2_R
64
5
ICS9LPRS365BKLFT-GP-U
ICS9LPRS365BKLFT setting table

PIN NAME
DESCRIPTION
71.09365.A03
PCI0/CR#_A
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
PCI1/CR#_B
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
PCI2/TME
0 = Overclocking of CPU and SRC Allowed

1 = Overclocking of CPU and SRC NOT allowed
PCI3
3.3V PCI clock output
PCI4/27M_SEL
0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96#

1 = Pin24 as 27MHz, Pin25 as 27MHz_SS, Pin20 as SRC-0, Pin21 as SRC-0#
PCI_F5/ITP_EN
0 =SRC8/SRC8#
1 = ITP/ITP#
SRCT3/CR#_C
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
GND
GNDSRC
GNDSRC
GNDSRC
GNDCPU
GND
NC#55
RN70
SRN33J-5-GP-U
DY
22
30
36
49
59
26
PCLKCLK3
55
GND48
GNDPCI
GNDREF
4
3
18
15
1
EC59
SC22P50V2JN-4GP
1
2
CLK_ICH14
PCLK_FWH
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
NB
CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8
54
53
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
R173 1
R176 1
2 0R0402-PAD
2 0R0402-PAD
CLK_PCIE_LAN 25
CLK_PCIE_LAN# 25
LAN
SRCT7/CR#_F
SRCC7/CR#_E
51
50
CLK_PCIE_NEW_R
CLK_PCIE_NEW#_R
R182 1
R181 1
2 0R0402-PAD
2 0R0402-PAD
CLK_PCIE_NEW 27
CLK_PCIE_NEW# 27
New Card
SRCT6
SRCC6
48
47
CLK_PCIE_ICH_1
CLK_PCIE_ICH_1#
R195 1
R194 1
2 0R0402-PAD
2 0R0402-PAD
CLK_PCIE_ICH 18
CLK_PCIE_ICH# 18
SB DMI
41
42
SRCT9
SRCC9
37
38
SRCT4
SRCC4
34
35
CLK_PCIE_MINI_1
CLK_PCIE_MINI_1#
R192 1
R193 1
2 0R0402-PAD
2 0R0402-PAD
CLK_PCIE_MINI1 27
CLK_PCIE_MINI1# 27
MINI1
SRCT3/CR#_C
SRCC3/CR#_D
31
32
CLK_MCH_3GPLL_1
CLK_MCH_3GPLL_1#
R180 1
R184 1
2 0R0402-PAD
2 0R0402-PAD
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
NB CLK
SRCT2/SATAT
SRCC2/SATAC
28
29
CLK_PCIE_SATA_1
CLK_PCIE_SATA_1#
R174 1
R177 1
2 0R0402-PAD
2 0R0402-PAD
CLK_PCIE_SATA 17
CLK_PCIE_SATA# 17
SB SATA
27MHZ_NONSS/SRCT1/SE1
27MHZ_SS/SRCC1/SE2
24
25
DREFSSCLK_1
DREFSSCLK#_1
R168 1
R171 1
2 0R0402-PAD
2 0R0402-PAD
DREFSSCLK 7
DREFSSCLK# 7
SRCT0/DOTT_96
SRCC0/DOTC_96
20
21
DREFCLK_1
DREFCLK#_1
R158 1
R161 1
2 0R0402-PAD
2 0R0402-PAD
DREFCLK 7
DREFCLK# 7
FSLB/TEST_MODE
REF0/FSLC/TEST_SEL
1
2
EC56
SC5P50V2CN-2GP
18
31
CPU
2 0R0402-PAD
2 0R0402-PAD
40
39
GND
4,7
PCLK_FWH
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
CPUT1_F
CPUC1_F
SRCT10
SRCC10
SRN33J-5-GP-U
SB,-1
PCLKCLK0
PCLKCLK1
PCLKCLK2
PCLKCLK3
2 0R0402-PAD
2 0R0402-PAD
R167 1
R169 1
SRCT11/CR#_H
SRCC11/CR#_G
SCLK
SDATA
63
1
10KR2J-3-GP
CLK_MCH_OE#
R160 1
R166 1
CLK_MCH_BCLK_1
CLK_MCH_BCLK_1#
NB CLK
NB CLK
(96 MHz)
SEL2 SEL1 SEL0

FSC FSB FSA
PIN NAME
DESCRIPTION
SRCC3/CR#_D
Byte 5, bit 1
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default)
1= CR#_D controls SRC4 pair
SRCC7/CR#_E
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_F controls SRC6
SRCT7/CR#_F
Byte 6, bit 6
1= CR#_F controls SRC8
SRCC11/CR#_G
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
SRCT11/CR#_H
Byte 6, bit 4
1= CR#_H controls SRC10
1
0
0
0
0
0
0
1
1
0
1
1
1
0
0
CPU
FSB
100M
133M
166M
200M
266M
X
533M
667M
800M
1066M
Wistron Corporation
Title
Size
Clock Generator
Document Number
Rev
he
Cathedral Peak II
B
2nd:
71.00875.C03
RTM875N-606-LFT QFN 64P

A
65
1
2
3
4
TPAD30 TP158
7
6
12,13,20 SMBC_ICH
12,13,20 SMBD_ICH
3D3V_S0
CLK_CPU_BCLK_1
CLK_CPU_BCLK_1#
58
57
USB_48MHZ/FSLA
2K2R2J-2-GP
3D3V_S0
PCLK_KBC
1
2
19
27
43
52
33
56
VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
VDDREF
VDD48
VDDPCI
VDDSRC
VDDCPU
VDDPLL3
2
R156
CPU_SEL0
CLK48 17
61
60
om
4 SRN33J-5-GP-U
3
1
2
CLK48_5158E
CLK48_ICH
X1
X2
CPUT0
CPUC0
ai
l.c
3
2
RN51
24
18
C176
SC33P50V2JN-3GP
GEN_XTAL_OUT
1
0R0402-PAD
tm
82.30005.951
GEN_XTAL_OUT_R
1 10MR2J-L-GP
ho
X3
X-14D31818M-44GP
DY
2
R153
f@
R154 2
xa
in
CL=20pF0.2pF
C177
SC33P50V2JN-3GP
GEN_XTAL_IN
1
2
EC55
SC5P50V2CN-2GP
DY
DY
4
16
9
46
62
23
SB
1
2
1
2
1
2
3D3V_CLKPLL_S0
3D3V_48MPWR_S0
EC137
SC5P50V2CN-2GP
U19
C198
CLK_ICH14
CLK48_ICH
EC57
SC5P50V2CN-2GP
DY
C453
SCD1U16V2ZY-2GP
PCLK_ICH
4,7
C214
1 R157
2
0R0603-PAD
C234
SCD1U16V2ZY-2GP
3D3V_CLKGEN_S0
C195
SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
C246
SCD1U16V2ZY-2GP
DY
SC4D7U10V5ZY-3GP
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C231
DY
3D3V_CLKGEN_S0
1 R197
2
0R0603-PAD
C462
C465
SCD1U16V2ZY-2GP
C459
SCD1U16V2ZY-2GP
C235
C463
DY
SC4D7U10V5ZY-3GP
DY
SCD1U16V2ZY-2GP
EC58
SCD1U16V2ZY-2GP
C183
SC1U16V3ZY-GP
SC4D7U6D3V3KX-GP
C190
DY
3D3V_CLKPLL_S0
3D3V_48MPWR_S0
1 R146
2
0R0603-PAD
Sheet
E
SC
of
43
H_A#[35..3]
H_A#[35..3]
H_DINV#[3..0]
U33A 1 OF 4
TPAD30
TP93
RSVD_CPU_11
B1
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
THERMTRIP#
BCLK0
BCLK1
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
H_DSTBN#1
H_DSTBP#1
H_DINV#1
H_D#16 N22
H_D#17 K25
H_D#18 P26
H_D#19 R23
H_D#20 L23
H_D#21 M24
H_D#22 L22
H_D#23 M23
H_D#24 P25
H_D#25 P23
H_D#26 P22
H_D#27 T24
H_D#28 R24
H_D#29 L25
H_D#30 T25
H_D#31 N25
L26
M26
N24
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
H_TRDY# 6
H_HIT#
H_HITM#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
TP27
TP25
TP28
TP41
TP30
TP37
TP29
TP39
TP40
TP44
TP34
TP91
H_THERMDA
6
6
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
DY
H_THERMDC
C136
SC2200P50V2KX-2GP
1D05V_S0
6
6
6
R123
68R2-GP
DY
CPU_PROCHOT#
D21
A24
B25
1
R124
H_THERMDA 21
H_THERMDC 21
C7
CPU_PROCHOT#_R
34
0R2J-2-GP
PM_THRMTRIP-A# 7,17,32
A22
A21
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
1D05V_S0
PM_THRMTRIP#
should connect to
ICH9 and MCH
without T-ing
( No stub)
6
6
6
R263
1KR2F-3-GP
Layout Note:
"CPU_GTLREF0"
0.5" max length.
CPU_GTLREF0
TP21
TP150
AD26
TEST1
C23
TEST2
D25
RSVD_CPU_12 C24
TEST4
AF26
RSVD_CPU_13 AF1
RSVD_CPU_14 A26
R266
2KR2F-3-GP
DY C352
KEY_NC
2nd: 62.10053.401
CPU_SEL0
CPU_SEL1
CPU_SEL2
B22
B23
C21
TPAD30 TP86
TPAD30
TPAD30
3,7
3,7
3,7
1D05V_S0
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
DATA GRP2
G6
E4
HCLK
MISC
BSEL0
BSEL1
BSEL2
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
R26
U26
AA1
Y1
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
E5
B5
D24
D6
D7
AE6
R101 1
2 54D9R2F-L1-GP
R97
2 54D9R2F-L1-GP
H_CPURST#
R116 1
DY
1
R118
DY
TEST1
1KR2J-1-GP
DY
2 51R2F-2-GP
1
R295
TEST2
1KR2J-1-GP
2
C351
XDP_TCK
R94
2 54D9R2F-L1-GP
XDP_TRST#
R96
2 54D9R2F-L1-GP
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
COMP0
COMP1
COMP2
COMP3
R105
R104
R98
R99
1
1
1
1
2
2
2
2
27D4R2F-L1-GP
54D9R2F-L1-GP
27D4R2F-L1-GP
54D9R2F-L1-GP
H_DPRSTP# 7,17,34
H_DPSLP# 17
H_DPWR# 6
H_PWRGD 17,32,41
H_CPUSLP# 6
PSI#
34
62.10079.001
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
2 54D9R2F-L1-GP
XDP_BPM#5
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
BGA479-SKT6-GPU7
Follow Demo Circuit

XDP_TDI
U33B 2 OF 4
6
DATA GRP3
HIT#
HITM#
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
H_RS#0
H_RS#1
H_RS#2
62.10079.001
R102 1
H_D#[63..0]
TPAD30
BGA479-SKT6-GPU7
XDP_TMS
1
C1
F3
F4
G3
G2
PROCHOT#
THRMDA
THRMDC
RSVD#M4
RSVD#N5
RSVD#T2
RSVD#V3
RSVD#B2
RSVD#C3
RSVD#D2
RSVD#D22
RSVD#D3
RSVD#F6
H_DSTBP#[3..0]
17
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
RESET#
RS0#
RS1#
RS2#
TRDY#
TP95
H_INIT#
H_LOCK# 6
H_CPURST# 6,41
H_RS#[2..0]
SC1KP50V2KX-1GP
RSVD_CPU_1
RSVD_CPU_2
RSVD_CPU_3
RSVD_CPU_4
RSVD_CPU_5
RSVD_CPU_6
RSVD_CPU_7
RSVD_CPU_8
RSVD_CPU_9
RSVD_CPU_10
H4
THERMAL
ICH
TP52
TP49
TP48
TP47
TP89
TP92
TP87
TP90
TP88
TP72
ADDR GROUP 1
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
LOCK#
H_BREQ#0 6
H_IERR#
STPCLK#
LINT0
LINT1
SMI#
F1
D20
B3
D5
C6
B4
A3
BR0#
IERR#
INIT#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
H_DSTBN#[3..0]
Place testpoint on
H_IERR# with a GND
0.1" away
R125
56R2J-4-GP
17
17
17
17
DEFER#
DRDY#
DBSY#
A20M#
FERR#
IGNNE#
H_D#[63..0]
A6
A5
C4
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_DSTBP#[3..0]
1D05V_S0
H_A20M#
H_FERR#
H_IGNNE#
H5
F21
E1
6
6
6
17
17
17
Side Band
Non GTL
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADSTB1#
H_ADS#
H_BNR#
H_BPRI#
DATA GRP1
H_ADSTB#1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
CONTROL
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
H_DINV#[3..0]
H_DSTBN#[3..0]
H1
E2
G5
DATA GRP0
K3
H2
K2
J3
L1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
ADS#
BNR#
BPRI#
XDP/ITP SIGNALS
H_ADSTB#0
H_REQ#[4..0]
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB0#
RESERVED
6
6
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP 0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
TP57 TPAD30
Net "TEST4" as short as possible,

make sure "TEST4" routing is
reference to GND and away other
noisy signals
TEST4
1
SCD1U10V2KX-4GP
DY
1
3D3V_S0
All place within 2" to CPU

XDP_DBRESET# R121 1
DY
2 1KR2J-1-GP
DY
2 54D9R2F-L1-GP
Wistron Corporation
1D05V_S0
Title
XDP_TDO
R100 1
CPU (1 of 2)
Size
Document Number
Rev
SC
Cathedral Peak II
Date:
A
Sheet
E
of
43
VCC_CORE
VCC_CORE
VCC_CORE
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
1
4
TC9
ST900U2D5VM-1-GP
TP22
TPAD30
NEC
2
3
DY
2
1
2
1
2
1
2
DY
C89
SCD1U10V2KX-4GP
DY
C130
SCD1U10V2KX-4GP
DY
C124
SCD1U10V2KX-4GP
DY
C90
SCD1U10V2KX-4GP
DY
C88
SCD1U10V2KX-4GP
DY
C122
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
C120
C86
77.E9071.011
C105
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
2
C103
DY
2
C71
DY
2
C106
DY
2
C94
DY
2
C70
SC10U6D3V5MX-3GP
DY
2
C374
SC10U6D3V5MX-3GP
DY
2
C381
SC10U6D3V5MX-3GP
DY
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
CAP
C375
C380
CAP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
CAP
C93
C135
CAP
SC10U6D3V5MX-3GP
CAP
SC10U6D3V5MX-3GP
C102
C123
CAP
VCC_CORE
SC10U6D3V5MX-3GP
1D05V_S0
G5
DY
C99
C433
C98
C95
C112
1
2
R77
100R2F-L1-GP-U
1
1
DY
1
2
VCC_CORE
C427
C110
DY
SC4D7U6D3V3KX-GP
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
C421
C108
SC4D7U6D3V3KX-GP
L11
1
34
C101
SCD1U10V2KX-4GP
1D5V_S0
1D5V_VCCA_S0
H_VID[6..0]
C104
SCD1U10V2KX-4GP
AE7
layout note: "1D5V_VCCA_S0"

as short as possible
SCD1U10V2KX-4GP
AF7
VSSSENSE
1D05V_S0
C100
SCD1U10V2KX-4GP
VCCSENSE
DY
SCD1U10V2KX-4GP
AD6
AF5
AE5
AF4
AE3
AF3
AE2
GAP-CLOSE-PWR-2U
C114
SCD1U10V2KX-4GP
VID0
VID1
VID2
VID3
VID4
VID5
VID6
SCD1U10V2KX-4GP
B26
C26
SC10U6D3V5MX-3GP
VCCA
VCCA
VCCP_1D05
SCD01U16V2KX-3GP
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
SCD1U10V2KX-4GP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SCD1U10V2KX-4GP
PBY160808T-121Y-GP
68.00206.021
VCC_SENSE 34
VSS_SENSE 34
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
SCD1U10V2KX-4GP
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
U33C 3 OF 4
BGA479-SKT6-GPU7
Layout Note:
R88
100R2F-L1-GP-U
VCCSENSE and VSSSENSE lines

should be of equal length.
62.10079.001
4 OF 4
U33D
VCC_CORE
VCC_CORE
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TPAD30
TP24
TPAD30
TP26
TP94
TPAD30
TP151
TPAD30
TP23
TPAD30
BGA479-SKT6-GPU7
62.10079.001
om
ai
l.c
tm
Wistron Corporation
f@
ho

Title
xa
in
CPU (2 of 2)
Size
Document Number
Rev
SC
Date:
A
he
Cathedral Peak II
Sheet
E
of
43
1 OF 10
U35A
H_A#[35..3]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
1D05V_S0
H_SWING routing Trace width and

Spacing use 10 / 20 mil
H_D#[63..0]
H_D#[63..0]
R317
221R2F-2-GP
H_SWING Resistors and

Capacitors close MCH
500 mil ( MAX )
1
H_SWING
R316
100R2F-L1-GP-U
C450
SCD1U10V2KX-4GP
H_RCOMP routing Trace width and

Spacing use 10 / 20 mil
1
R312
2
24D9R2F-L-GP
H_RCOMP
Place them near to the chip ( < 0.5")
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
HOST
2
1
R322
1KR2F-3-GP
4,41 H_CPURST#
4
H_CPUSLP#
H_AVREF
C455
SCD1U16V2ZY-2GP
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
J8
L3
Y13
Y1
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
L10
M7
AA5
AE6
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
L9
M8
AA6
AE5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_SWING
H_RCOMP
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
B15
K13
F13
B13
B14
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
C12
E11
H_CPURST#
H_CPUSLP#
A11
B11
H_AVREF
H_DVREF
H_RS#_0
H_RS#_1
H_RS#_2
B6
F12
C8
H_RS#0
H_RS#1
H_RS#2
H_A#[35..3]
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 3
CLK_MCH_BCLK# 3
H_DPWR# 4
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_REQ#[4..0]
H_RS#[2..0]
CANTIGA-GM-GP-U-NF
R318
2KR2F-3-GP
C5
E3
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H_DINV#[3..0]
1D05V_S0
H_SWING
H_RCOMP
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
71.CNTIG.00U
Wistron Corporation
Title
Size
Cantiga (1 of 6)
Document Number
Rev
SC
Cathedral Peak II
Date:
5
Sheet
1
of
43
2 OF 10
U35B
M_CS0#
M_CS1#
M_CS2#
M_CS3#
13
13
12
12
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
BD17
AY17
BF15
AY13
M_ODT0
M_ODT1
M_ODT2
M_ODT3
13
13
12
12
SM_RCOMP
SM_RCOMP#
BG22
BH21
M_RCOMPP
M_RCOMPN
SM_RCOMP_VOH
SM_RCOMP_VOL
BF28
BH28
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
AV42
AR36
BF17
BC36
SM_REXT
1R328
TP_SM_DRAMRST#
CLK
M_RCOMPP
PEG_CLK
PEG_CLK#
DY
2 4K02R2F-GP
CFG20
R345 1
DY
2 2K21R2F-GP
CFG5
R186 1
DY
2 2K21R2F-GP
CFG6
R188 1
DY
2 2K21R2F-GP
CFG7
CFG16
18
PM_SYNC#
4,17,34 H_DPRSTP#
DY
2 2K21R2F-GP
CFG9
R336 1
DY
2 2K21R2F-GP
CFG10
18,25,27,30,31
PLT_RST1#
2
R353
R140
1
0R0402-PAD
1
2
300R2F-GP
R190 1
DY
2 2K21R2F-GP
CFG12
R185 1
DY
2 2K21R2F-GP
CFG13
2 2K21R2F-GP
CFG16
3D3V_S0
RN32
PM_EXTTS#0
PM_EXTTS#1
4
3
1
2
SRN10KJ-5-GP
NC#BG48
NC#BF48
NC#BD48
NC#BC48
NC#BH47
NC#BG47
NC#BE47
NC#BH46
NC#BF46
NC#BG45
NC#BH44
NC#BH43
NC#BH6
NC#BH5
NC#BG4
NC#BH3
NC#BF3
NC#BH2
NC#BG2
NC#BE2
NC#BG1
NC#BF1
NC#BD1
NC#BC1
NC#F1
NC#A47
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
14 GMCH_TXBOUT014 GMCH_TXBOUT114 GMCH_TXBOUT2-
A41
H38
G37
J37
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
14 GMCH_TXBOUT0+
14 GMCH_TXBOUT1+
14 GMCH_TXBOUT2+
B42
G38
F37
K37
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
F25
H25
K25
TVA_DAC
TVB_DAC
TVC_DAC
DREFCLK 3
DREFCLK# 3
DREFSSCLK 3
DREFSSCLK# 3
F43
E43
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
AE41
AE37
AE47
AH39
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
AE40
AE38
AE48
AH40
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
H24
TV_RTN
C31
E32
TV_DCONSEL_0
TV_DCONSEL_1
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
AE35
AE43
AE46
AH42
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
GMCH_BLUE
E28
CRT_BLUE
GMCH_GREEN
G28
CRT_GREEN
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
AD35
AE44
AF46
AH43
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
C487
3
3
TVA_DAC
TVB_DAC
TVC_DAC
DMI_TXN0 18
DMI_TXN1 18
DMI_TXN2 18
DMI_TXN3 18
DMI_TXP0 18
DMI_TXP1 18
DMI_TXP2 18
DMI_TXP3 18
15
DMI_RXN0 18
DMI_RXN1 18
DMI_RXN2 18
DMI_RXN3 18
GMCH_BLUE
15 GMCH_GREEN
15
DMI_RXP0 18
DMI_RXP1 18
DMI_RXP2 18
DMI_RXP3 18
38
GMCH_DDCCLK
GMCH_DDCDATA
GMCH_HS
3
4
GMCH_VS
2
1
J28
CRT_RED
G29
CRT_IRTN
H32
J32
J29
E29
L29
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
RN71
SRN33J-5-GP-U
CRT_IREF
1
2
R347
1K02R2F-1-GP
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
B33
B32
G33
F33
E33
GMCH_RED
GMCH_RED
15 GMCH_DDCCLK
15 GMCH_DDCDATA
15 GMCH_HSYNC
15 GMCH_VSYNC
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
1
49D9R2F-GP
Close to GMCH as 500 mils.
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
FOR Cantiga: 1.02k_1% ohm
Teenah: 1.3k ohm
GFXVR_EN
GFX_VR_EN
C34
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
AH37
AH36
AN36 CLPWROK_MCH 2 R352
1
0R0402-PAD
AJ35
AH34 MCH_CLVREF
GFXVR_EN 38
CRT_IREF routing Trace

width use 20 mil
1D05V_S0
CL_CLK0 18
CL_DATA0 18
PWROK
18,32
CL_RST#0
18
C270
NC
DY
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47
499R2F-2-GP
TP120
TPAD30
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
N28
M28
G36
E36
K36
H36
TSATN#
B12
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
B28
B30
B29
C29
A28
SCD1U10V2KX-4GP
4,17,32 PM_THRMTRIP-A#
18,34 PM_DPRSLPVR
R189 1
DY
C165
SC100P50V2JN-3GP
B38 DREFCLK
A38 DREFCLK#
E41 DREFSSCLK
F41 DREFSSCLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
H48
D45
F40
B40
DDR_VREF_S3
GFX_VID[4..0]
18,21,34 VGATE_PWRGD
18,32 PWROK
R332 1
R354 0R2J-2-GP
1
DY 2
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
H47
E46
G40
A40
14 GMCH_TXAOUT0+
14 GMCH_TXAOUT1+
14 GMCH_TXAOUT2+
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_CMP 2
R208 1
14 GMCH_TXAOUT014 GMCH_TXAOUT114 GMCH_TXAOUT2-
14 GMCH_TXACLK14 GMCH_TXACLK+
14 GMCH_TXBCLK14 GMCH_TXBCLK+
R355
1KR2F-3-GP
RN72
CFG19
ME
2 4K02R2F-GP
MISC
DY
TP115 TPAD30
CLK_MCH_OE#
MCH_ICH_SYNC#
MCH_TSATN#
3
18
GMCH_RED
R356
511R2F-2-GP
GMCH_BLUE
GMCH_GREEN
1
2
3
4
8
7
6
5
B
SRN150F-1-GP
FOR Cantiga:500 ohm

Teenah: 392 ohm
TP110 TPAD30
RN62
HDA
R207 1
GRAPHICS VID
CFG12
CFG13
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
VGA
R29
B7
N33
P32
AT40
AT11
T20
R32
CFG9
CFG10
3D3V_S0
PM
PM_SYNC#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PWROK_GD
RSTIN#
PM_THRMTRIP-A#
PM_DPRSLPVR
CFG5
CFG6
CFG7
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
CFG
CFG19
CFG20
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
CPU_SEL0
CPU_SEL1
CPU_SEL2
DMI
3,4
3,4
3,4
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
M29
C44
B43
E37
E38
C41
C40
B37
A37
TV
M_RCOMPN
R330
80D6R2F-L-GP
M33
K33
J33
T37
T36
GRAPHICS
13
13
12
12
BA17
AY16
AV16
AR13
LCTLB_DATA
CLK_DDC_EDID
DAT_DDC_EDID
GMCH_LCDVDD_ON
LIBG
TPAD30 TP121
L_LVBG
14 CLK_DDC_EDID
14 DAT_DDC_EDID
14 GMCH_LCDVDD_ON
PEG_COMPI
PEG_COMPO
PCI-EXPRESS
M_CKE0
M_CKE1
M_CKE2
M_CKE3
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
R331
80D6R2F-L-GP
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
SCD1U10V2KX-4GP
1D8V_S3
13
13
12
12
layout take note
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
RESERVED#BG23
RESERVED#BF23
RESERVED#BH18
RESERVED#BF18
AR24
AR21
AU24
AV20
BC28
AY28
AY36
BB36
R214
L32
G32
M32
TPAD30 TP119
TPAD30 TP118
RESERVED#AY21
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
L_BKLTCTL
GMCH_BL_ON
LCTLA_CLK
14 L_BKLTCTL
30 GMCH_BL_ON
AY21
BG23
BF23
BH18
BF18
C470
C472
SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP
R334
1KR2F-3-GP
SM_RCOMP_VOL
13
13
12
12
RESERVED#B31
RESERVED#B2
RESERVED#M1
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
B31
B2
M1
AP24
AT21
AV24
AU20
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
LVDS
C477
C475
SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP
RSVD
R338
3K01R2F-3-GP
SM_RCOMP_VOH
D
DDR CLK/ CONTROL/COMPENSATION
1
2
R339
1KR2F-3-GP
RESERVED#M36
RESERVED#N36
RESERVED#R33
RESERVED#T33
RESERVED#AH9
RESERVED#AH10
RESERVED#AH12
RESERVED#AH13
RESERVED#K12
RESERVED#AL34
RESERVED#AK34
RESERVED#AN35
RESERVED#AM35
RESERVED#T24
1D05V_S0
3 OF 10
U35C
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24
1D8V_S3
CANTIGA-GM-GP-U-NF
TVA_DAC
TVB_DAC
TVC_DAC
1
2
3
4
8
7
6
5
SRN75J-1-GP
RN63
GMCH_LCDVDD_ON
GMCH_BL_ON
GFXVR_EN
1
2
3
4
8
7
6
5
1D05V_S0
3D3V_S0
71.CNTIG.00U
MCH_TSATN#
LIBG
SRN100KJ-8-GP-U
R216
1
2
2K37R2F-GP
RN33
LCTLB_DATA
LCTLA_CLK
CLK_MCH_OE#
R324
56R2J-4-GP
5
6
7
8
4
3
2
1
SRN10KJ-6-GP
Strap Description
Configuration
ai
l.c
om
Pin Name
f@
ho
tm
Low = Only digital DisplayPort

(SDVO/DP/HDMI) or
PCIE is operational (default)
Wistron Corporation
High = Digital DisplayPort

(SDVO/DP/HDMI) and
PCIE are operating simultaneously via the PEG port

xa
in
Digital DisplayPort
(SDVO/DP/HDMI)
Concurrent with
PCIE
Title
Cantiga (2 of 6)
Size
he
CFG20
Document Number
Rev
Cathedral Peak II
Date:
5
Sheet

1
SC
of
43
SA_RAS#
SA_CAS#
SA_WE#
BB20
BD20
AY20
M_A_RAS# 13
M_A_CAS# 13
M_A_WE# 13
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_A[14..0]
M_A_DM[7..0] 13
M_A_DQS[7..0]
13
M_A_DQS#[7..0]
13
M_A_A[14..0] 13
M_B_DQ[63..0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
5 OF 10
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_BS_0
SB_BS_1
SB_BS_2
BC16
BB17
BB33
SB_RAS#
SB_CAS#
SB_WE#
AU17
BG16
BF14
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
M_B_BS#0 12
M_B_BS#1 12
M_B_BS#2 12
M_B_RAS# 12
M_B_CAS# 12
M_B_WE# 12
D
M_B_DM[7..0]
M_A_BS#0 13
M_A_BS#1 13
M_A_BS#2 13
MEMORY
BD21
BG18
AT25
SYSTEM
U35E
12 M_B_DQ[63..0]
SA_BS_0
SA_BS_1
SA_BS_2
M_A_DM[7..0]
MEMORY
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SYSTEM
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12
DDR
M_A_DQ[63..0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
4 OF 10
U35D
13 M_A_DQ[63..0]
DDR
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
71.CNTIG.00U
M_B_DM[7..0] 12
M_B_DQS[7..0]
M_B_DQS[7..0]
M_B_DQS#[7..0]
12
M_B_DQS#[7..0]
M_B_A[14..0]
12
M_B_A[14..0] 12
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
Wistron Corporation
Title
Cantiga (3 of 6)
Size
Document Number
Rev
SC
Cathedral Peak II
Date:
5
Sheet
1
of
43
1D8V_S3
C438
Coupling CAP
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
T32
VCC
G11
VCC_GMCH_35
VCC CORE
C434
DY
SCD1U10V2KX-4GP
DY
SC10U6D3V5MX-3GP
Coupling CAP
Coupling CAP 370 mils from the Edge
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
POWER
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
C436
C236
SCD1U10V2KX-4GP
GAP-CLOSE-PWR
Place CAP where

LVDS and DDR2 taps
DY
C259
1
2
C258
Place on the Edge
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
CANTIGA-GM-GP-U-NF
C492
C491
C488
SC1U10V3KX-3GP
SCD22U10V2KX-1GP
2
C468
C178
SC1U10V3KX-3GP
C164
SCD47U16V3ZY-3GP
C464
71.CNTIG.00U
SCD22U10V2KX-1GP
VCC SM LF
VCC GFX
C255
SC10U6D3V5MX-3GP
DY
SE330U2D5VDM-LGP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
TC19
SC10U6D3V5MX-3GP
C252
SC10U6D3V5MX-3GP
C266
AV44 SM_LF1_GMCH
BA37 SM_LF2_GMCH
AM40 SM_LF3_GMCH
AV21 SM_LF4_GMCH
AY5 SM_LF5_GMCH
AM10 SM_LF6_GMCH
BB13 SM_LF7_GMCH
SCD1U10V2KX-4GP
VCC_AXG_SENSE
VSS_AXG_SENSE
SCD1U10V2KX-4GP
DY
C253
1D8V_S3
C254
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
1D05V_S0
VCC NCTF
VCC SM
C248
SCD1U10V2KX-4GP
SC1U10V3ZY-6GP
VCC GFX NCTF
C233
DY
SCD1U10V2KX-4GP
C249
DY
SCD1U10V2KX-4GP
C157
DY
C435
SC10U6D3V5MX-3GP
C244
C141
SC10U6D3V5MX-3GP
C225
C142
DY
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
FOR VCC SM
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
C167
DY
Place on the Edge
SCD1U10V2KX-4GP
AJ14
AH14
38 VCC_AXG_SENSE
38 VSS_AXG_SENSE
DY
SCD1U10V2KX-4GP
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
DY
TC18
SC10U6D3V5MX-3GP
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14
C437
SE220U2D5VDM-3GP
6 OF 10
U35F
VCC_GFXCORE
SC10U6D3V5MX-3GP
VCC_GFXCORE
1D05V_S0
SC10U6D3V5MX-3GP
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
SC10U6D3V5MX-3GP
BA36
BB24
BD16
BB21
AW16
AW13
AT13
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
SC10U6D3V5MX-3GP
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
SC10U6D3V5MX-3GP
667MTS 2400mA
800MTS 3000mA
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
POWER
U35G
VCC_GFXCORE
7 OF 10
ai
l.c
om
place near Cantiga
f@
ho
tm
Wistron Corporation
xa
in

Title
he
Size
Cantiga (4 of 6)
Document Number
Rev
SC
Cathedral Peak II
Date:
5
Sheet
1
of
43
1D05V_S0
1
2
1
2
1
2
1
2
2
1
1
2
C35
B35
A35
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
V48
U48
V47
U47
U46
VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI
AH48
AF48
AH47
AG47
C202
1
C274
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
C251
1
2
C440
SC10U6D3V5MX-3GP
DY
1D05V_S0
1
2
1
C185
C445
SCD47U6D3V2KX-GP
DY
VTTLF1
VTTLF2
VTTLF3
SCD47U6D3V2KX-GP
71.CNTIG.00U
C263
C439
DY
C441
SC10U6D3V5MX-3GP
Wistron Corporation
Title
Cantiga (5 of 6)
Size
Document Number
Rev
SC
Cathedral Peak II
Date:
C275
SC1U10V3KX-3GP
A8
L1
AB2
-1
1
1
2
VTTLF
VTTLF
VTTLF
456mA
C262
VCCD_LVDS
VCCD_LVDS
C447
DY
VCCD_PEG_PLL
1D8V_SUS_DLVDS
C271
C276
SC1KP50V2KX-1GP
1782mA
CANTIGA-GM-GP-U-NF
R212
1
2
0R0603-PAD
1D8V_S3
3D3V_HV_S0
106mA
R217
1
2
0R0603-PAD
AXF
SM CK
K47
VCC_HV
VCC_HV
VCC_HV
DMI
VCCD_HPLL
LVDS
A CK
HDA
VCCD_QDAC
VCC_TX_LVDS
C222
SC10U6D3V5MX-3GP
119mA
SC10U6D3V5MX-3GP
1
2
VCCD_TVDAC
L28
M38
L37
1D8V_SUS_SM_CK_RC
1D8V_TXLVDS_S3
SC22U6D3V5MX-2GP
M25
1D5VRUN_QDAC
C483
SCD1U10V2KX-4GP
1D05V_S0
1D5VRUN_TVDAC
AF1
R179
1
2
0R0603-PAD
1R2F-GP
VCC_HDA
BF21
BH20
BG20
BF20
A32
50mA
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
1D8V_S3
R183
1
C230
SCD1U10V2KX-4GP
SC22U6D3V5MX-2GP
124mA
SCD47U6D3V2KX-GP
R349
10R2F-L-GP
C460
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
1D8V_S3
C239
SCD1U10V2KX-4GP
60.3mA
3D3V_HV_S0
R350
2
1
0R0402-PAD
C480
DY
SC4D7U6D3V3KX-GP
SCD1U10V2KX-4GP
68.00206.041
180ohm 100MHz
A
C467
B22
B21
A21
HV
VCCA_TV_DAC
VCCA_TV_DAC
VCC_AXF
VCC_AXF
VCC_AXF
PEG
B24
A24
1D05V_RUN_PEGPLL AA47
C186
1D5VRUN_QDAC
2
PBY160808T-181Y-GP
POWER
VTTLF
C469
SCD01U16V2KX-3GP
157.2mA
L2
3D3V_S0
1D05V_HV_S0 1
1D05V_S0
TV
C471
1D05V_SUS_MCH_PLL2
1D5VRUN_TVDAC
C242
SCD1U10V2KX-4GP
322mA
D TV/CRT
79mA
1
2
DY
C484
SCD1U10V2KX-4GP
35mA
R196
1
2
0R0603-PAD
DY
D22
2
BAT54-7-F-GP
3
VTT
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
DY
2
1D8V_SUS_SM_CK
3D3VTVDAC
50mA
1D5V_S0
CRT
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
C175
SCD1U10V2KX-4GP
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
C187
1
2
DY
L14
1
2
0R0603-PAD
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16
220ohm 100MHz
VCCA_PEG_PLL
852mA
1
C260
1D05V_S0
C241
3D3V_S0_DAC
1D05V_RUN_PEGPLL
68.00217.521
C245
1
2
1
M_VCCA_MPLL
1
2
1
2
DY
139.2mA
2
FCM1608CF-221T02-GP
VCCA_PEG_BG
C256
1D05V_SM_CK
C237
SCD1U10V2KX-4GP
L15
C227
1
2
1
2
1
2
1
2
1
C219
SCD1U10V2KX-4GP
1D05V_S0
DY
C446
SCD1U10V2KX-4GP
VSSA_LVDS
26mA
1
2
R203
0R0603-PAD
DY
SC2D2U6D3V3MX-1-GP
DY
C442
SC10U6D3V5MX-3GP
120ohm 100MHz
1D05V_S0
C444
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
68.00217.161
C224
M_VCCA_HPLL
C443
120ohm 100MHz
L12
1
2
FCM1608KF-1-GP
1D05V_RUN_PEGPLL AA48
1D05V_SM
720mA
C171
AD48
VCCA_LVDS
C482
SCD1U10V2KX-4GP
SC1U10V3KX-3GP
1D05V_S0
1
2
R191
0R0603-PAD
24mA
SC4D7U6D3V3KX-GP
68.00217.161
13.2mA
J47
SC1U10V3KX-3GP
1
2
FCM1608KF-1-GP
VCCA_MPLL
VCCA_PEG_BG
1D05V_SUS_MCH_PLL2
L13
VCCA_HPLL
AE1
DY
SC4D7U6D3V3KX-GP
R310
0R0603-PAD
DY
VCCA_DPLLB
AD1
M_VCCA_MPLL
SC1U10V3KX-3GP
1D05V_S0
M_VCCA_DPLLB
C485
SCD1U10V2KX-4GP
L48
M_VCCA_HPLL
1D8V_TXLVDS_S3
R351
0R0402-PAD
1
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C489
M_VCCA_DPLLB
J48
C277
SC1KP50V2KX-1GP
DY
65mA
VCCA_DPLLA
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
C261
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
R357
1
2
0R0603-PAD
C486
SCD1U10V2KX-4GP
1D5V_S0
C490
1D8V_TXLVDS_S3
M_VCCA_DPLLA
F47
A LVDS
C474
SCD1U10V2KX-4GP
65mA
R358
1
2
0R0603-PAD
VCCA_DAC_BG
VSSA_DAC_BG
PLL
M_VCCA_DPLLA
1D05V_S0
M_VCCA_DAC_BG A25
B25
VCCA_CRT_DAC
VCCA_CRT_DAC
C257
A PEG
5mA
1
2
R342
0R0603-PAD
B27
A26
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
A SM
1
2
3D3V_S0_DAC
C479
SCD1U10V2KX-4GP
DY
SC1U16V3ZY-GP
EC154
74.09198.G7F
SC1U16V3ZY-GP
C476
SC22U16V0KX-1GP
-1
8 OF 10
U35H
SCD47U6D3V2KX-GP
EC153
3D3V_CRTDAC_S0
SC4D7U6D3V3KX-GP
C478
SC2D2U6D3V3MX-1-GP
NC#4
RT9198-33PBR-GP
73mA
1
2
R346
0R0603-PAD
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
VOUT
SCD01U16V2KX-3GP
VIN
GND
EN/EN#
3D3V_S0_DAC
3D3V_S0_DAC
U36
1
2
3
Imax = 300 mA
5V_S0
Sheet
1
10
of
43
10 OF 10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
VSS
VSS
VSS
VSS
U24
U28
U25
U29
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
NCTF_VSS_SCB#BH48
NCTF_VSS_SCB#BH1
NCTF_VSS_SCB#A48
NCTF_VSS_SCB#C1
NCTF_VSS_SCB#A3
BH48
BH1
A48
C1
A3
NC#E1
NC#D2
NC#C3
NC#B4
NC#A5
NC#A6
NC#A43
NC#A44
NC#B45
NC#C46
NC#D47
NC#B47
NC#A46
NC#F48
NC#E48
NC#C48
NC#B48
TP163
TP155
TP164
TP156
TP157
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
om
BA16
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
VSS
VSS NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ai
l.c
BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17
NCTF TEST PIN:

A3,C1,A48,BH1,BH48
VSS
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS SCB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Wistron Corporation
tm
U35J
9 OF 10
U35I
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36

ho
f@
Title
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
71.CNTIG.00U
Cantiga (6 of 6)
Size
xa
in
CANTIGA-GM-GP-U-NF
Document Number
Rev
SC
Date:
5
he
Cathedral Peak II
Sheet
1
11
of
43
DM1
Put decap near power(0.9V)

and pull-up resistor
DDR_VREF_S3
1
2
8 M_B_DQS#[7..0]
C172
SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
C220
SCD1U16V2ZY-2GP
C160
C217
SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
C221
SCD1U16V2ZY-2GP
C197
SCD1U16V2ZY-2GP
C215
C196
DY
SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C166
C180
C205
8 M_B_DQS[7..0]
-1
DDR_VREF_S3_1
1
2
M_ODT2
M_ODT3
C280
SCD1U16V2ZY-2GP
DY
7
7
C281
SC4D7U6D3V3KX-GP
202
MH1
VREF
VSS
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
GND
GND
201
MH1
MH2
MH2
1D8V_S3
Place these Caps near DM1
1D8V_S3
C449
C203
DY
C451
DY
C461
DY
C174
C456
C199
DY
Decoupling Capacitor
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DY
M_B_BS#0
M_B_CAS#
M_CS3#
M_CS2#
C117
SCD1U16V2ZY-2GP
C158
1
2
3
4
SRN56J-5-GP
3D3V_S0
8
7
6
5
81
82
87
88
95
96
103
104
111
112
117
118
2
R114
10KR2J-3-GP
OTD0
OTD1
1
2
RN12
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DDRB_SA0
C452
114
119
SRN56J-5-GP
50
69
83
120
163
3,13,20
3,13,20
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
M_B_A14
M_B_A11
M_B_A7
M_B_A6
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
SMBD_ICH
SMBC_ICH
1
2
3
4
SA0
SA1
198
200
13
31
51
70
131
148
169
188
RN27
8
7
6
5
199
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
SRN56J-5-GP
195
197
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
M_B_BS#1
M_B_A2
M_B_A0
M_B_A4
SDA
SCL
VDDSPD
M_CLK_DDR3 7
M_CLK_DDR#3 7
M_B_DM[7..0]
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
1
2
3
4
10
26
52
67
130
147
170
185
SCD1U16V2ZY-2GP
11
29
49
68
129
146
167
186
RN22
8
7
6
5
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SC2D2U6D3V3MX-1-GP
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SRN56J-5-GP
M_CLK_DDR2 7
M_CLK_DDR#2 7
164
166
SC2D2U6D3V3MX-1-GP
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
30
32
CK1
CK1#
SCD1U16V2ZY-2GP
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
8 M_B_DQ[63..0]
SRN56J-5-GP
RN15
1 M_B_A13
2 M_ODT2
3 M_ODT3
4 M_B_RAS#
CK0
CK0#
8
7
6
5
M_CKE2 7
M_CKE3 7
SC2D2U6D3V3MX-1-GP
BA0
BA1
79
80
SCD1U16V2ZY-2GP
107
106
M_CS2# 7
M_CS3# 7
CKE0
CKE1
SRN56J-5-GP
RN18
8
1 M_B_A3
7
2 M_B_A1
6
3 M_B_A10
5
4 M_B_WE#
M_B_RAS# 8
M_B_WE# 8
M_B_CAS# 8
110
115
TPAD30 TP111
108
109
113
CS0#
CS1#
SRN56J-5-GP
RN31
1 M_CKE3
2 M_B_A12
3 M_B_BS#2
4 M_CKE2
RAS#
WE#
CAS#
8
7
6
5
1
2
3
4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
8
7
6
5
M_B_A8
M_B_A9
M_B_A5
SC2D2U6D3V3MX-1-GP
M_B_BS#0
M_B_BS#1
Put decap near power(0.9V) and pull-up resistor
RN25
SCD1U16V2ZY-2GP
M_B_BS#2
8
8
SC2D2U6D3V3MX-1-GP
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A[14..0]
REVERSE TYPE
PARALLEL TERMINATION
DDR_VREF_S3
DDR2-200P-23-GP-U1
62.10017.A71
High 9.2mm
2nd: 62.10017.B51
1
Wistron Corporation
Title
DDR2 Socket 0 (DM1)

Size
Document Number
Rev
SC
Cathedral Peak II
Date:
A
Sheet

E
12
of
43
DM2
ODT0
ODT1
SRN56J-5-GP
RN28
8
7
6
5
1
2
3
4
M_A_A6
M_A_A7
M_A_A11
M_CKE1
SRN56J-5-GP
RN19
8
7
6
5
1
2
3
4
M_A_BS#0
M_A_A1
M_A_A10
M_A_WE#
SRN56J-5-GP
Decoupling Capacitor
SCD1U16V2ZY-2GP
C170
SCD1U16V2ZY-2GP
C173
SCD1U16V2ZY-2GP
DY
C201
SCD1U16V2ZY-2GP
C192
C223
DY
SCD1U16V2ZY-2GP
C218
DY
SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
C209
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C181
DY
C207
SCD1U16V2ZY-2GP
C189
SCD1U16V2ZY-2GP
C191
Put decap near power(0.9V)

and pull-up resistor
1
DDR_VREF_S3
8 M_A_DQS#[7..0]
8 M_A_DQS[7..0]
DDR_VREF_S3_1
M_ODT0
M_ODT1
1
2
C279
202
SCD1U16V2ZY-2GP
50
69
83
120
163
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
81
82
87
88
95
96
103
104
111
112
117
118
VREF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
GND
GND
201
3D3V_S0
C115
SCD1U16V2ZY-2GP
DY
1D8V_S3
Place these Caps near DM2
1D8V_S3
C200
DY
C454
C458
C457
DY
C169
C448
DY
C193
C179
DY
C216
SKT-SODIMM20022U2GP
62.10017.691
High 5.2mm
2nd: 62.10017.911
ai
l.c
om
DY
7
7
C278
SC4D7U6D3V3KX-GP
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
3,12,20
3,12,20
114
119
M_A_A9
M_A_A14
M_A_A5
M_A_A3
SMBD_ICH
SMBC_ICH
1
2
3
4
199
198
200
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
RN24
195
197
SA0
SA1
13
31
51
70
131
148
169
188
SRN56J-5-GP
8
7
6
5
SDA
SCL
VDDSPD
SC2D2U6D3V3MX-1-GP
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_ODT1
M_CS1#
SCD1U16V2ZY-2GP
/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7
M_A_CAS#
1
2
3
4
8
7
6
5
SCD1U16V2ZY-2GP
11
29
49
68
129
146
167
186
RN13
M_CLK_DDR1 7
M_CLK_DDR#1 7
M_A_DM[7..0]
SC2D2U6D3V3MX-1-GP
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
8 M_A_DQ[63..0]
SRN56J-5-GP
M_CLK_DDR0 7
M_CLK_DDR#0 7
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
SC2D2U6D3V3MX-1-GP
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
10
26
52
67
130
147
170
185
M_A_BS#1
M_A_A0
M_A_A2
M_A_A4
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
1
2
3
4
CK1
/CK1
164
166
8
8
RN23
30
32
SRN56J-5-GP
8
7
6
5
TP112
M_CKE0 7
M_CKE1 7
CK0
/CK0
TPAD30
CKE0
CKE1
M_A_A13
M_ODT0
M_CS0#
M_A_RAS#
M_CS0# 7
M_CS1# 7
79
80
1
2
3
4
M_A_RAS# 8
M_A_WE# 8
M_A_CAS# 8
110
115
SCD1U16V2ZY-2GP
BA0
BA1
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
RN16
108
109
113
/CS0
/CS1
SCD1U16V2ZY-2GP
M_A_BS#0
M_A_BS#1
107
106
SRN56J-5-GP
8
7
6
5
/RAS
/WE
/CAS
SC2D2U6D3V3MX-1-GP
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
M_A_A12
M_CKE0
M_A_BS#2
M_A_A8
1
2
3
4
8
7
6
5
SC2D2U6D3V3MX-1-GP
M_A_BS#2
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A[14..0]
Put decap near power(0.9V) and pull-up resistor
RN29
PARALLEL TERMINATION
DDR_VREF_S3
REVERSE TYPE
f@
ho
tm
Wistron Corporation
xa
in

Title
Size
he
DDR2 Socket 1 (DM2)
Document Number
Rev
Cathedral Peak II
Date:
A
Sheet

E
13
SC
of
43
LCD/INVERTER/CCD CONN
Inverter Pin
CLK_DDC_EDID
DAT_DDC_EDID
7 CLK_DDC_EDID
7 DAT_DDC_EDID
CCD_PWR
BRIGHTNESS_CN
2BLON_OUT_1
R457
1
BLON_OUT
33R2J-2-GP
DCBATOUT
F2
PWR_INVERTER
69.50007.A31
GMCH_TXBCLK+ 7
GMCH_TXBCLK- 7
GMCH_TXBOUT2+ 7
GMCH_TXBOUT2- 7
GMCH_TXBOUT1+ 7
GMCH_TXBOUT1- 7
GMCH_TXBOUT0+ 7
GMCH_TXBOUT0- 7
GMCH_TXACLK+ 7
GMCH_TXACLK- 7
GMCH_TXAOUT2+ 7
GMCH_TXAOUT2- 7
GMCH_TXAOUT1+ 7
GMCH_TXAOUT1- 7
GMCH_TXAOUT0+ 7
GMCH_TXAOUT0- 7
DY
BRIGHTNESS_CN
BRIGHTNESS 30
RN1
4
3
SRN2K2J-1-GP
GND
Cover Up Switch
3D3V_AUX_S5
CCD Pin
Pin
Symbol
CCD_PWR
USB-
USB+
GND
GND
R253
10KR2J-3-GP
DY
U4
OUT
VDD
LID_CLOSE#
LID_CLOSE# 30
GND
EC93
SCD1U16V2ZY-2GP
ME268-002-GP
DY
74.00268.07B
C305
74.00268.A7B
74.00268.C7B
SC100P50V2JN-3GP
SC100P50V2JN-3GP
1
2
BLON_OUT 16,30
DY
GND
L_BKLTCTL 7
R242 1
2
0R0402-PAD
C306
BLON
R241
1
0R2J-2-GP
BLON_OUT
3D3V_S0
Brightness
EC92
SCD1U16V2ZY-2GP
20.F0993.040
2nd: 20.F1048.040
3nd: 20.F1084.040
DY
Vin
3
4
ACES-CONN40A-2GP
SCD1U50V3ZY-GP
SC10U25V6KX-1GP
EC86
SC10U10V5ZY-1GP
GMCH_TXBCLK+
GMCH_TXBCLKGMCH_TXBOUT2+
GMCH_TXBOUT2GMCH_TXBOUT1+
GMCH_TXBOUT1GMCH_TXBOUT0+
GMCH_TXBOUT0GMCH_TXACLK+
GMCH_TXACLKGMCH_TXAOUT2+
GMCH_TXAOUT2GMCH_TXAOUT1+
GMCH_TXAOUT1GMCH_TXAOUT0+
GMCH_TXAOUT0-
POLYSW-1D1A24V-GP
C307
C5
3D3V_S0
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Vin
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
Symbol
USBPP8_R
DY
1
2
USBPN8_R
C3
DY SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
R7
2
1
0R0402-PAD
C4
USBPP8
Pin
1
18
LCD1
41
2
R6
2
1
0R0402-PAD
USBPN8
18
LCDVDD
DY
CLK_DDC_EDID
DAT_DDC_EDID
3D3V_S0
LCDVDD
U1
Layout 40 mil
GND
IN#8
IN#7
IN#6
IN#5
9
8
7
6
5
1
IN#1
OUT
EN
GND
G5281RC1U-GP
74.05281.093
SC4D7U6D3V3MX-2GP
1
2
3
4
C2
SCD1U16V2ZY-2GP
DY
C6
GMCH_LCDVDD_ON
7 GMCH_LCDVDD_ON
C7
SC4D7U6D3V3MX-2GP
-1
F3
3D3V_S0
FUSE-1D1A6V-8GP
69.41101.021
F4
1
2
SC4D7U10V5ZY-3GP
CCD_PWR
C309
1
C308
SCD1U16V2ZY-2GP
DY
DY
2
3D3V_S0
FUSE-4A32V-6-GP
69.44001.041
Wistron Corporation
Consumption stock

Title
LCD CONN
Size
Document Number
Rev
SC
Cathedral Peak II
Date:
Sheet
14
of
43
Layout Note:
Place these resistors
close to the CRT-out
connector
Hsync & Vsync level shift

5V_S0
Ferrite bead impedance: 10 ohm@100MHz

L7
GMCH_RED
CRT_R
2
FCB1608CF-GP
68.00230.021
L4
CRT_VSYNC1
U32B
TSAHCT125PW-GP
C341
CRT_HSYNC1
3
U32A
TSAHCT125PW-GP
DY
C342
CRT_R 3
Layout Note:
* Must be a ground return path between this ground and the ground on
the VGA connector.
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
DY
SC18P50V2JN-1-GP
5V_S0
D20
14
5
7 GMCH_VSYNC
1
2
1
2
1
2
1
2
1
8
7
6
5
7 GMCH_HSYNC
C321
SC18P50V2JN-1-GP
1
2
3
4
DY
C326
SC6D8P50V2DN-GP
DY
CRT_B
C336
SC6D8P50V2DN-GP
2
FCB1608CF-GP
68.00230.021
SC6D8P50V2DN-GP
DY
EC106
SC3P50V2CN-1-GP
SC3P50V2CN-1-GP
RN73
SRN150F-1-GP
EC109
SC3P50V2CN-1-GP
1
EC96
GMCH_BLUE
68.00230.021
7
C314
SCD1U16V2ZY-2GP
CRT_G
2
FCB1608CF-GP
14
7 GMCH_GREEN
L6
DY
1
BAV99PT-GP-U
3
D18
CRT_G 3
DY
1
BAV99PT-GP-U
D17
CRT_B 3
DY
1
BAV99PT-GP-U
DDC_CLK & DATA level shift
5V_S0
6
1
7
2
8
3
9
4
10
5
CRT_B
7
12
8
13
9
14
10
15
4
CRT_IN#_R
5V_CRT_S0
DAT_DDC1_5
CRT_HSYNC1
CRT_VSYNC1
C315
CLK_DDC1_5
SCD01U16V2KX-3GP
17
VIDEO-15-42-GP-U
CRT_G
F1
RN41
SRN2K2J-1-GP
5V_CRT_DDC
FUSE-1D1A6V-4GP-U
RN2
SRN10KJ-6-GP
69.50007.691
Q15
1
2
3
4
6
11
3
4
D2
BAS16PT-GP
2
1
16
CRT_R
5V_CRT_S0
8
7
6
5
CRT1
3D3V_S0
3D3V_S0
CRT I/F & CONNECTOR

2
CRT_IN#_R
DAT_DDC1_5
20.20378.015
6
7 GMCH_DDCDATA
CRT_VSYNC1
om
CLK_DDC1_5
ai
l.c
tm
Wistron Corporation
D16

DY
C313
SC100P50V2JN-3GP
ho
2
470R2J-2-GP
C578
SC220P50V2JN-3GP
DY
Title
BAV99PT-GP-U
1
DY
Size
CRT Connector
f@
CRT_DEC#
30
5V_S0
CRT_IN#_R
xa
in
R254
1
DY
Document Number
Rev
SC
Cathedral Peak II
Date:
A
he
CLK_DDC1_5
DAT_DDC1_5
C317
C19
SC100P50V2JN-3GP
2N7002DW-1-GP
1
2
DY
SC100P50V2JN-3GP
C323
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
C316
7 GMCH_DDCCLK
CRT_HSYNC1
Sheet
E
15
of
43
Q31
PWRLED#_DB
C
R1
E
R2
PDTC143ZU-GP-U
Q30
STDBY_LED#_BD
C
D
30
R1
STDBY_LED
Power Button
3D3V_S5
LED5
R451
1
2
56R2J-4-GP
R450
1
2
56R2J-4-GP
84.00143.E1K
FRONT_PWRLED#_R 3
1
SW1
STDBY_LED#_R
R8
KBC_PWRBTN#_1
3
5
LED-GY-14-GP
83.00195.I70
EC5
SC1KP50V2KX-1GP
Q28
CHARGE_LED#
C
R1
CHARGE_LED#_R
2
PWRLED#_DB
LED-GY-14-GP
83.00195.I70
STDBY_LED#_BD
WLAN_LED#_1
GND
R458
1
2
56R2J-4-GP
R465
1
2
56R2J-4-GP
FRONT_PWRLED#_PB
STDBY_LED#_PB
R34
1
2
LED-GY-14-GP
WLAN_LED#
1
2
33R2J-2-GP
IN
3D3V_S5
LED3
E
R2
PDTC143ZU-GP-U
83.00195.I70
C
Q4
CHDTA143ZUPT-GP
SB
DC_BATFULL#_R
84.00143.E1K
BLON_OUT 14,30
LED6
R449
1
2
56R2J-4-GP
R448
1
2
56R2J-4-GP
84.00143.E1K
27 WLAN_LED#_MC
KBC_PWRBTN#
4
3
SRN10KJ-5-GP
3D3V_AUX_S5
R2
PDTC143ZU-GP-U
1
2
2nd: 62.40009.671
E
30 CHARGE_LED
RN74
DY
SW-TACT-122-GP
DC_BATFULL#
R1
KBC_PWRBTN# 30
3D3V_AUX_S5
62.40009.681
Q29
30 DC_BATFULL
KBC_PWRBTN#
470R2J-2-GP
84.00143.E1K
E
R2
PDTC143ZU-GP-U
30 FRONT_PWRLED
R2
84.00143.J11
Q5
2N7002-11-GP
R1
30 WLAN_TEST_LED
OUT
Q18
30
BT_LED#
C
R1
E
R2
PDTC143ZU-GP-U
BT_LED
84.00143.E1K
E Power Button
SW2
B
R462
E-BUTTON#_CN_1 1
4
2
E-BUTTON#
E-BUTTON# 30
EC13
SC1KP50V2KX-1GP
DY
SW-TACT-122-GP
470R2J-2-GP
62.40009.681
3D3V_S0
C116 SC1U16V3ZY-GP
1
2
DY
2nd: 62.40009.671
EC22 SCD1U16V2ZY-2GP
1
2
WLAN_LED#
EC11
BT_LED#
EC182
Volume_Up#
EC141
BT_BTN#
EC142
WIRELESS_BTN#
EC143
Volume_Down#
EC144
MEDIA_LED#
EC123
CAP_LED#
EC122
NUM_LED#
EC121
INT_MIC
EC149
-1
DY
-1
LAUNCHCN1
EC180 SCD1U16V2ZY-2GP
1
2
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
5V_S0
DY
EC181
SCD1U16V2ZY-2GP
1
2
DY
WLAN_LED#
BT_LED#
Volume_Up#
BT_BTN#
WIRELESS_BTN#
Volume_Down#
MEDIA_LED#
CAP_LED#
NUM_LED#
INT_MIC
Volume_Up# 30
BT_BTN# 30
WIRELESS_BTN# 30
Volume_Down# 30
MEDIA_LED# 17
CAP_LED# 30
NUM_LED# 30
INT_MIC 28
3D3V_S0
5V_S0
WLAN_LED#
BT_LED#
Volume_Up#
BT_BTN#
WIRELESS_BTN#
Volume_Down#
MEDIA_LED#
CAP_LED#
NUM_LED#
INT_MIC
DY
1
2
SC220P50V2JN-3GP
DY
1
2
SC220P50V2JN-3GP
DY
1
2
SC220P50V2JN-3GP
DY
1
2
SC220P50V2JN-3GP
DY
1
2
SC220P50V2JN-3GP
DY
1
2
SC220P50V2JN-3GP
2
SC220P50V2JN-3GP
DY
1
2
SC220P50V2JN-3GP
DY
1
TP58
TP189
TP190
TP191
TP192
TP193
TP194
TP195
TP53
TP54
TP55
TP178
DY
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
SC220P50V2JN-3GP
DY
1
1
1
1
1
1
1
1
1
1
1
1
1
SC220P50V2JN-3GP
Wistron Corporation
EMI
Title
17
MLX-CON15-1-GP
Size
20.K0185.015
POWER /LAUNCH/LED BOARD
Document Number
Rev
SC
Cathedral Peak II
5
Sheet
1
16
of
43
C91
1
RTC_X1
D9
TPAD30
GLAN_COMP place within 500 mil of ICH9M

R453
1
2
R452
RN9
23 ACZ_BTCLK_MDC
28
ACZ_BITCLK
EC161
SC10P50V2JN-4GP
DY
B22
A22
INTVRMEN
LAN100_SLP
E25
GLAN_CLK
GLAN_DOCK#
1R284
2 22R2J-2-GP
1
0R0402-PAD
2 GLAN_COMP
24D9R2F-L-GP
ACZ_BIT_CLK_R
ACZ_SYNC_R
ACZ_RST#_R
ACZ_SDATAOUT_R
8
7
6
5
28 ACZ_SDATAIN0
23 ACZ_SDATAIN1
SRN33J-7-GP
3D3V_S0
ACZ_SDATAOUT_R
TPAD30
3D3V_S0
MEDIA_LED#
LAN_RXD0
LAN_RXD1
LAN_RXD2
D13
D12
E13
LAN_TXD0
LAN_TXD1
LAN_TXD2
B10
GLAN_DOCK#/GPIO56
B28
B27
GLAN_COMPI
GLAN_COMPO
AF6
AH4
HDA_BIT_CLK
HDA_SYNC
AE7
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
AG5
HDA_SDOUT
AG7
AE8
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
HDD
C146
C145
C147
C148
1
1
1
1
2
2
2
2
AJ16
AH16
AF17
AG17
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
ODD
22
22
22
22
SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1
C149
C150
C144
C143
1
1
1
1
2 SCD01U50V2KX-1GP SATA_RXN1_C AH13

2 SCD01U50V2KX-1GP SATA_RXP1_C AJ13
2 SCD01U50V2KX-1GP SATA_TXN1_C AG14
2 SCD01U50V2KX-1GP SATA_TXP1_C AF14
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C
ICH9M-GP-NF
FWH4/LFRAME#
K3
LDRQ0#
LDRQ1#/GPIO23
J3
J1
A20GATE
A20M#
AF4
AG4
AH3
AE5
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
MEDIA_LED#
R299
1
2
10KR2J-3-GP
HDA_DOCK_EN#
2
8K2R2J-3-GP
LAN_RSTSYNC
22
22
22
22
16
HDA_DOCK_RST#
TP148
DY
1
R302
C13
F14
G13
D14
K5
K4
L6
K2
AJ25
AE23
FERR#
AJ26
CPUPWRGD
AD22
LDRQ0#
3D3V_LDRQ1_S0
TP146 TPAD30
TP50 TPAD30
H_DPRSTP#
H_DPRSTP# 4,7,34
H_DPSLP# 4
RN8
H_THERMTRIP_R
AF25
AE22
AG25
L3
H_INIT# 4
H_INTR 4
KBRCIN# 30
NMI
SMI#
AF23
AF24
STPCLK#
AH27
AG26
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AH11
AJ11
AG12
AF12
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
AH9
AJ9
AE10
AF10
SATA_CLKN
SATA_CLKP
AH18
AJ18
SATARBIAS#
SATARBIAS
AJ7
AH7
1D05V_S0
H_FERR#_R
INIT#
INTR
RCIN#
AG27
H_DPSLP#
KA20GATE 30
H_A20M# 4
IGNNE#
PECI
R297
56R2J-4-GP
DY
H_PWRGD 4,32,41
4
H_IGNNE# 4
THRMTRIP#
30,31
LPC_LFRAME# 30,31
N7
AJ27
DPRSTP#
DPSLP#
LPC_LAD[0..3]
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
INTVRMEN
LAN100_SLP
RTC
LPC
RTCRST#
SRTCRST#
INTRUDER#
1D5V_S0
1
2
3
4
23,28 ACZ_SYNC
23,28 ACZ_RST#
23,28 ACZ_SDATAOUT
A25
F20
C22
LAN_RSTYNC
TP143
18 GLAN_DOCK#
ACZ_SYNC
RTC_RST#
SRTC_RST#
INTRUDER#
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
H_FERR#
1
2
3
4
8
7
6
5
H_FERR#_R
C
SRN56J-5-GP
H_NMI 4
H_SMI# 4
R296
200R2F-L-GP
1 DY
2
H_PWRGD
1D05V_S0
H_STPCLK# 4
H_THERMTRIP_R
ICH_TP8
DY R300
TP96 TPAD30
54D9R2F-L1-GP
Layout note: R373 needs to placed

within 2" of ICH9, R379 must be
placed within 2" of R373 w/o stub
CLK_PCIE_SATA# 3
CLK_PCIE_SATA 3
SATARBIAS
2
1
R301
24D9R2F-L-GP
1D05V_S0
Place within 500 mils of

ICH9 ball
3D3V_S0
2
1
C354
SC1U16V3ZY-GP
62.70001.011
RTCX1
RTCX2
LAN / GLAN
CPU
C73
SC1U16V3ZY-GP
3
4
2
1MR2J-1-GP
C23
C24
RTC_X2
1
R282
LPC_LAD[0..3]
1 OF 6
U16A
SC12P50V2JN-3GP
2
1
1D05V_S0
C92
1
RN75
SRN20KJ-GP-U
R265
1
2
1KR2J-1-GP
IHDA
83.R0304.B81
DY C353
SCD1U16V2ZY-2GP
BAT-CON2-1-GP-U
C74
SC1U16V3ZY-GP
SATA
CH715FPT-GP
RTC_BAT
1
2
NP1
NP2
R95
10MR2J-L-GP
82.30001.691
RTC_BAT_R
RTC1
PWR
GND
NP1
NP2
X2
X-32D768KHZ-38GPU
RTC_AUX_S5
-1
3D3V_AUX_S5
SC12P50V2JN-3GP
71.ICH9M.00U
RN14
SRN10KJ-5-GP
3
4
RTC_AUX_S5
RTC_AUX_S5
R90
330KR2F-L-GP
H_INIT#_G
R93
330KR2F-L-GP
DY
LAN100_SLP
R92
0R2J-2-GP
INTVRMEN
High=Enable
B
Q13
Low=Disable
H_INIT#
FWH_INIT#
FWH_INIT#
integrated VccLan1_05VccCL1_05
LAN100_SLP
High=Enable
ai
l.c
DY
tm

Title
EMI
Size
Document Number
ICH9-M (1 of 4)
f@
2
SC22P50V2JN-4GP
ho
DY
1
EC188
xa
in
ACZ_BITCLK
Wistron Corporation
2
SC22P50V2JN-4GP
Rev
SC
Cathedral Peak II
5
he
ACZ_BTCLK_MDC 1
EC187
31
MMBT3904-3-GP
Low=Disable
om
R91
0R2J-2-GP
DY
INTVRMEN
integrated VccSus1_05,VccSus1_5,VccCL1_5
Sheet
1
17
of
43
3 OF 6
U16C
2 OF 6
2
3D3V_S0
1
2
3
4
5
3D3V_S0
10
9
8
7
6
INT_PIRQD#
PCI_IRDY#
PCI_TRDY#
ECSCI#_1
28
ACZ_SPKR
7 MCH_ICH_SYNC#
TPAD30
10
9 INT_SERIRQ
8 PCI_DEVSEL#
7 PCI_STOP#
6 PCI_FRAME#
4 OF 6
R130
1
1
E29
E28
F27
F26
PERN5
PERP5
PETN5
PETP5
C29
C28
D27
D26
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
TXN5
TXP5
D23
D24
F23
N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3
USB_RBIAS_PN AG2
AG1
V27
V26
U29
U28
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
7
7
7
7
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y27
Y26
W29
W28
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
7
7
7
7
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB27
AB26
AA29
AA28
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
7
7
7
7
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD27
AD26
AC29
AC28
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
7
7
7
7
T26
T25
CLK_PCIE_ICH# 3
CLK_PCIE_ICH 3
AF29
AF28
DMI_IRCOMP_R
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
SPI_CLK
USBP2N
SPI_CS0#
USBP2P
SPI_CS1#/GPIO58/CLGPIO6 USBP3N
USBP3P
SPI_MOSI
USBP4N
SPI_MISO
USBP4P
USBP5N
OC0#/GPIO59
USBP5P
OC1#/GPIO40
USBP6N
OC2#/GPIO41
USBP6P
OC3#/GPIO42
USBP7N
OC4#/GPIO43
USBP7P
OC5#/GPIO29
USBP8N
OC6#/GPIO30
USBP8P
OC7#/GPIO31
USBP9N
OC8#/GPIO44
USBP9P
OC9#/GPIO45
USBP10N
OC10#/GPIO46
USBP10P
OC11#/GPIO47
USBP11N
USBP11P
USBRBIAS
USBRBIAS#
USB
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2
USBPN0 23
USBPP0 23
CL_VREF0
CL_VREF1
C25
A19
CL_RST0#
CL_RST1#
F21
D18
GPIO24/MEM_LED
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
GPIO9/WOL_EN
A16
C18
C11
C20
RN64
1
2
4
3
GPIO24
GPIO10
GPIO14
GPIO9
TP32
3D3V_S5
7
TPAD30
DY
USB_OC#2
USB_OC#7
PM_RI#
PCIE_WAKE#
3D3V_S0
10
9
8
7
6
RN49
Pair
PCB_VER0
PCB_VER1
2
10KR2J-3-GP
1
2
3
4
B
SRN10KJ-6-GP
RN45
R133
Device
USBPN2 23
USBPP2 23
USB1
NC
USBPN4 23
USBPP4 23
USBPN5 23
USBPP5 23
USB2
NC
BOOT BIOS Strap
USB3
PCI_GNT#0
R145
DY
1
2
SRN10KJ-5-GP
PlanarID
(1,0)
SA: 0,0
SB: 0,1
SC: 1,0
SD: 1,1
3D3V_S5
R74
1
2
0R2J-2-GP
D7
R73
10KR2J-3-GP
RSMRST#_SB
1
2
DY
R273
100KR2J-1-GP
SPI_CS#1
4
3
R144
30 RSMRST#_KBC
USBPN7 27
USBPP7 27
USBPN8 14
USBPP8 14
USBPN9 27
USBPP9 27
USBPN10 24
USBPP10 24
Bluetooth
NC
0
1
1
1
0
1
BOOT BIOS Location
A16 swap override strap
MINIC1
WEBCAM
NEW1
PCI_GNT#0
10
CardReader
SPI_CS#1
11
NC
PCI_GNT#3
BAT54-7-F-GP
SPI
PCI
LPC(Default)
low = A16 swap override enable

high = default
PCI_GNT#3
GNT0 and SPI_CS#1
have a weak internal pull up
ICH9M-GP-NF
1
R286
1
R287
1
R285
1KR2J-1-GP
2
DY
1KR2J-1-GP
2
DY
1KR2J-1-GP
2
DY
Wistron Corporation
Title
Size
Date:
Document Number
ICH9-M (2 of 4)
Rev
SC
Cathedral Peak II
71.ICH9M.00U
4
8
7
6
5
SB_GPIO13
GPIO14
R134
DY
R288
1
USB_OC#4
DBRESET#
USB_OC#3
USB_OC#6
3D3V_S0
SRN10KJ-5-GP
PWROK
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11
3D3V_S5
SRN10KJ-L3-GP
4
3
R298
24D9R2F-L-GP
USB
DY
RN47
1
2
3
4
5
3D3V_S5
1
2
R274
453R2F-1-GP
SRN10KJ-L3-GP
RP1
SDATAOUT1
SB_GPIO1
R283
453R2F-1-GP
3D3V_S5
GLAN_DOCK# 17
SRN10KJ-5-GP
1D5V_S0
C365
R275
3K24R2F-GP
TP139 TPAD30
3D3V_S5
10
9 USB_OC#5
8 SMB_LINK_ALERT#
7 GPIO10
SMB_ALERT#
6
1
2
3
4
5
3D3V_S5
GLAN_DOCK#
GPIO57
CL_VREF0_ICH
CL_VREF1_ICH
CL_RST#0
SMB
SATA
GPIO
CL_DATA0 7
3D3V_S5
3D3V_S0
R281
3K24R2F-GP
CL_CLK0 7
RP2
USB_OC#1
PM_BATLOW#_R
ECSWI#
USB_OC#0
7,32
TPAD30
TP31
F24
B19
PERN4
PERP4
PETN4
PETP4
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
22D6R2F-L1-GP
PWROK
F22
C19
G29
G28
H27
H26
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11
CLK_PWRGD
R6
B16 PM_SLP_M#
USB_OC#4
D21
3
BAS16PT-GP
2
RSMRST#_SB
R5
CL_CLK0
CL_CLK1
PERN3
PERP3
PETN3
PETP3
D25
E23
23
PM_PWRBTN# 30,41
DY
J29
J28
K27
K26
SPI_CS#1
D22
CL_DATA0
CL_DATA1
10KR2J-3-GP
PERN2
PERP2
PETN2
PETP2
NEW CARD
USB_OC#0
CK_PWRGD
SCD1U10V2KX-5GP 2
SCD1U10V2KX-5GP 2
23
D20
PM_DPRSLPVR 7,34
R289 1
DY 2
100KR2J-1-GP
71.ICH9M.00U
C372
C379
LAN_RST#
SLP_M#
1
1
PERN1
PERP1
PETN1
PETP1
SCD1U10V2KX-5GP 2
SCD1U10V2KX-5GP 2
MINICARD1
PCIE_RXN5
PCIE_RXP5
PCIE_TXN5
PCIE_TXP5
PWRBTN#_ICH
10KR2J-3-GP
TXN2
TXP2
L29
L28
M27
M26
27
27
27
27
R3
C360
C391
C395
PM_BATLOW#_R
PWRBTN#
RSMRST#
10KR2J-3-GP
N29
N28
P27
P26
LAN
PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2
PM_DPRSLPVR
B13
CLPWROK
10KR2J-3-GP
TXN1
TXP1
PCI-Express
1
1
Direct Media Interface
SCD1U10V2KX-5GP 2
SCD1U10V2KX-5GP 2
SPI
27
27
27
27
C399
C403
SPKR
MCH_SYNC#
TP3
PWM0
PWM1
PWM2
M2
BATLOW#
ICH9M-GP-NF
U16D
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
ENERGY_DETECT/GPIO13
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
No Reboot Strap
SPKR
LOW = Defaule
High=No Reboot
SRN8K2J-2-GP-U
25
25
25
25
SST
M7
AJ24
B21
AH20
AJ20
AJ21
ICH_TP3
TP138
GPIO49 should be pulled down to

GND only when using Teenah. When
using Cantiga, this ball should
be left as No Connect.
SRN8K2J-2-GP-U
3D3V_S0
VRMPWRGD
A20
AG19
CLK_SEL_1
AH21
AG21
30
ECSCI#_1
A21
30
ECSWI#
GPIO12
C12
SB_GPIO13
TPAD30 TP140
C21
PSW_CLR# AE18
GPIO18
K1
GPIO20
TPAD30 TP51
AF8
CLK_SEL_0
TPAD30 TP149
AJ22
A9
SEL
R306
D19
1KR2J-1-GP
L1
PCB_VER0 AE19
PCB_VER1 AG22
SDATAOUT1 AF21
GPIO49
AH24
GPIO57
TPAD30 TP152
A8
DPRSLPVR/GPIO16
7,32
SCD1U10V2KX-4GP
PM_CLKRUN#
3D3V_S0
1
2
3
4
5
PCI_REQ#3
INT_PIRQF#
INT_PIRQG#
PCI_SERR#
D21
SB_GPIO1
PCI_REQ#2
PCI_REQ#1
INT_PIRQH#
PCI_REQ#0
INT_PIRQC#
INT_PIRQB#
SRN8K2J-2-GP-U
RP3
GAP-OPEN
RP4
ICH_TP7
WAKE#
SERIRQ
THRM#
TP141 TPAD30
PWROK
R136
1KR2J-1-GP
DY 0R2J-2-GP
G20
G10
ICS
R305
1KR2J-1-GP
PWROK
PM_SLP_S3# 27,30,32,36,37,38
PM_SLP_S4# 27,30,36,37
TP144 TPAD30
TPAD30
1R89
ICS+RTL
S4_STATE#
R141
10KR2J-3-GP
R135
1KR2J-1-GP
C10
RTL+SEL
S4_STATE#/GPIO26
PM_SUS_CLK 21
PCLK_ICH
1
PLT_RST1# 7,25,27,30,31
SLPS5#
4
3
2
1
SRN10KJ-6-GP
7,21,34 VGATE_PWRGD
1
0R2J-2-GP
P1
C16
E16
G17
3
3
3D3V_S0 -1
SUSCLK
SMBALERT#/GPIO11
CLKRUN#
CLK_ICH14
CLK48_ICH
DY
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
3D3V_S0
L4
E20
M5
AJ23
25,27 PCIE_WAKE#
30 INT_SERIRQ
21
THRM#
H1
AF3
SLP_S3#
SLP_S4#
SLP_S5#
PMSYNC#/GPIO0
STP_PCI#
STP_CPU#
RN11
5
6
7
8
SCD1U10V2KX-4GP
3D3V_S0
10
9
8
7
6
A14
E19
PM_STPPCI#
PM_STPCPU#
30 PM_CLKRUN#
C357
SC100P50V2JN-3GP
R271
H4
K6
F2
G2
3
3
C14 PLT_RST#_R
D4
R2
PCI_DEVSEL#
PCI_PERR#
PCI_LOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
(0, 1)
(1, 1)
(1, 0)
PLTRST#
PCICLK
PME#
TP142 TPAD30
TP56
RP5
1
2
3
4
5
SUS_STAT#/LPCPD#
SYS_RESET#
M6
PM_SYNC#
SATA0GP
SATA1GP
GPIO36
GPIO37
PCI_IRDY#
PCI_PAR
71.ICH9M.00U
PCI_PERR#
INT_PIRQE#
PCI_LOCK#
INT_PIRQA#
RI#
R4
G19
AH23
AF19
AE21
AD20
ICS
Realtek
Seligo
ICH9M-GP-NF
C
F19
PM_SUS_STAT#
DBRESET#
SMB_ALERT# A17
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
(GPIO6,GPIO22)
TP147
CLK14
CLK48
Clocks
TPAD30
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
SYS GPIO
Power MGT
PCI_REQ#3
PCI_GNT#3
D8
B4
D6
A5
SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1
PM_RI#
SRN10KJ-5-GP
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
Interrupt I/F
3
4
G16
A13
SMB_LINK_ALERT# E17
SMLINK0 C17
SMLINK1 B18
MISC
GPIO
Controller Link
PCI_REQ#2
ICH_PME#
PIRQA#
PIRQB#
PIRQC#
PIRQD#
RN4
2
1
3D3V_S5
C/BE0#
C/BE1#
C/BE2#
C/BE3#
F1
G4
B6
A7
F13
F12
E6
F6
J5
E1
J6
C4
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
PCI
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
20,27 SMB_CLK
20,27 SMB_DATA
PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
U16B
Sheet
1
18
of
43
1mA
A27
VCCGLANPLL
D28
D29
E26
E27
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5
A26
VCCGLAN3_3
1
2
1
2
1
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
AD8
VCCSUS1_5
F18
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
A18
D16
D17
E22
VCCSUS3_3
AF1
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
11mA
3D3V_S0
C431
SCD1U10V2KX-4GP
DY
11mA
2
VCCSUS1_5
C387
C376
3D3V_S5
C432
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S5
3D3V_S5
VCCCL1_05
G22 VccSus1_05[3]
VCCCL1_5
G23 VccSus1_5[3]
VCCCL3_3
VCCCL3_3
A24
B24
C404
1
2
C371
SCD1U10V2KX-4GP
VCCSUS3_3=212mA
TP145 TPAD28
3D3V_S5
C369
C402
SCD1U10V2KX-4GP
C410
C366
DY
DY
DY
3D3V_S0
C386
SCD1U10V2KX-4GP
om
C385
SCD1U10V2KX-4GP
1D5V_S5
VCCPSUS
C393
SC4D7U6D3V3KX-GP
tm
ai
l.c
19mA in S0;73mA in S3/S4/S5
ho
VCCLAN3_3
VCCLAN3_3
C392
DY
f@
VCCLAN1_05
VCCLAN1_05
A12
B12
C406
Wistron Corporation
xa
in
A10
A11
1D05V_S0

he
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCCSUS1_05
VCCSUS1_05
C370
VCCUSBPLL
AA7
AB6
AB7
AC6
AC7
C425
SCD1U10V2KX-4GP
1D5V_S0
68.1R220.10D
1D05V_S0
C426
SCD1U10V2KX-4GP
C401
SC4D7U6D3V3MX-2GP
2mA
3D3V_S0
C377
1
2
2
1
2
1
2
3D3V_S0
C383
SCD1U10V2KX-4GP
VCC1_5_A
VCC1_5_A
VCC1_5_A
AJ5
AJ4
AJ3
AC8 VccSus1_05
F17
CORE
2
VCCHDA
VCCSUSHDA
DY
C373
1
2
1
2
1
2
C394
SC10U6D3V5MX-3GP
80mA
DY
VCC1_5_A
VCC1_5_A
AC12
AC13
AC14
VCCPUSB
1
1
2
1
2
C368
SC4D7U6D3V3KX-GP
DY
VCC1_5_A
G10
G9
23mA
C411
2
IND-1D2UH-10-GP
DY
48mA
1 R294
2
0R0603-PAD
C415
SC4D7U6D3V3KX-GP
DY
3D3V_S0
C378
SCD1U10V2KX-4GP
1D5V_S0
VCC1_5_A
VCC1_5_A
AC21
SCD1U10V2KX-4GP
23mA
1
C362
SCD1U10V2KX-4GP
2
AC18
AC19
DY
B9
F9
G3
G6
J2
J7
K7
C414
VCC3_3=308mA 3D3V_S0
SCD1U10V2KX-4GP
C363
VCC1_5_A
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
C430
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S0
VccLan1D05
AC9
L10
C382
GLAN POWER
SCD1U10V2KX-4GP
DY
DY
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
USB CORE
19mA in S0;78mA in S3/S4/S5
SCD1U10V2KX-4GP
3D3V_S0
C416
SCD1U10V2KX-4GP
AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10
AD19
AF20
AG24
AC20
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
AC10
1
2
AJ6
VCCP_CORE
PCI
AG29
VCC3_3
SCD1U10V2KX-4GP
C429
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
ATX
DY
DY
USBPLL=11mA
C418
SCD1U10V2KX-4GP
C384
C428
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S0
C388
SC1U16V3ZY-GP
SC1U16V3ZY-GP
C408
C420
VCCSATAPLL
AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15
ARX
C419
SC4D7U6D3V3MX-2GP
C134
SCD1U16V2ZY-2GP
C364
SCD1U10V2KX-4GP
AJ19
VCC3_3
1.34A
AB23
AC23
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
1D5V_S0
V_CPU_IO
V_CPU_IO
C413
DY
SCD1U10V2KX-4GP
R122
100R2J-2-GP
C367
SCD1U10V2KX-4GP
V5REF_S5
W23 1D05V_DMI_ICH_S0
Y23
SCD1U10V2KX-4GP
D13
CH751H-40PT
2mA
C398
SCD1U10V2KX-4GP
5V_S5
C409
C400
SCD01U16V2KX-3GP
SCD1U10V2KX-4GP
3D3V_S5
C396
1D5V_DMIPLL_ICH_S0
SCD1U10V2KX-4GP
Layout Note:
Place near ICH9
VCCDMI
VCCDMI
DY
SCD1U10V2KX-4GP
C152
SC10U6D3V5MX-3GP
C151
R29
1D05V_S0
Layout Note: Place near ICH9M
C407
SC10U6D3V5MX-3GP
C361
SCD1U16V2ZY-2GP
68.1R220.10D
VCCDMIPLL
DY
SCD1U10V2KX-4GP
V5REF_S0
2
IND-1D2UH-10-GP
R276
100R2J-2-GP
SC1U16V3ZY-GP
2mA
1D5V_APLL_S0
L1
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCCA3GP
D10
CH751H-40PT
1D5V_S0
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25
1.63A
-1
C405
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC4D7U6D3V3MX-2GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
47mA
5V_S0
V5REF_SUS
SCD1U10V2KX-4GP
C423
*Within a given well, 5VREF needs to be up before the

corresponding 3.3V rail
3D3V_S0
V5REF
SCD1U10V2KX-4GP
C417
DY
SCD1U10V2KX-4GP
C412
AE1
A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
SCD1U10V2KX-4GP
C390
DY
A6
V5REF_S5
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
SCD1U10V2KX-4GP
C422
DY
V5REF_S0
6 OF 6
VCCRTC
SCD1U10V2KX-4GP
C389
A23
SCD1U10V2KX-4GP
646mA
C359
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S0
6uA in G3
C358
U16F
RTC_AUX_S5
Title
ICH9-M (3 of 4)
ICH9M-GP-NF
Size
71.ICH9M.00U
Document Number
Rev
SC
Cathedral Peak II
Date:
5
Sheet
1
19
of
43
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25
NCTF_VSS#A1
NCTF_VSS#A2
NCTF_VSS#B1
NCTF_VSS#A29
NCTF_VSS#A28
NCTF_VSS#B29
NCTF_VSS#AJ1
NCTF_VSS#AJ2
NCTF_VSS#AH1
NCTF_VSS#AJ28
NCTF_VSS#AJ29
NCTF_VSS#AH29
A1
A2
B1
A29
A28
B29
AJ1
AJ2
AH1
AJ28
AJ29
AH29
3D3V_S5
3D3V_S0
8
7
6
5
RN43
SRN2K2J-2-GP
1
2
3
4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NCTF TEST PIN:

A1,A2,B1,A28,A29,B29
AH1,AJ1,AJ2,AH29,AJ28,AJ29
AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29
5 OF 6
U16E
5V_S0
Q6
18,27
SMB_CLK
6 2N7002DW-1-GP
SMBC_ICH 3,12,13
2
18,27 SMB_DATA
SMBD_ICH 3,12,13
SMBUS
TP33
TP35
TP46
TP43
TP38
TP45
TP98
TP101
TP99
TP102
TP100
TP97
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
Wistron Corporation
Title
ICH9-M (4 of 4)
Size
ICH9M-GP-NF
71.ICH9M.00U
Rev
SC
Cathedral Peak II
Date:
Document Number
Sheet
E
20
of
43
5V_S0
D11
SSM14PT-GP-U
RN7
1
2
4
3
EMC2102_FAN_TACH_1
EMC2102_FAN_TACH
-1
EMC2102_FAN_DRIVE
1
1
5
3
2
83.1R004.E8M
SRN10KJ-5-GP
DY
C332
SC22U6D3V5MX-2GP
C109
SCD1U16V2ZY-2GP
C107
SC4D7U10V5ZY-3GP
FAN1
EMC2102_FAN_TACH_1
*Layout* 15 mil
3D3V_S0
5V_S0
4
MLX-CON3-10-GP-U
D19
SSM14PT-GP-U
20.F1000.003
83.1R004.E8M
2nd: 20.F0714.003
3nd: 20.D0246.103
A
3D3V_S0
R115
Layout notice :
Both H_THERMDA and THERMDC routing
10 mil trace width and 10 mil spacing
DP1
SMCLK
22
24
23
25
FANb
VDD_5Vb
SMDATA
21
GND
20
19
ALERT#
CLK_IN
18
CLK_32K
DP2
CLK_SEL
17
EMC2102_DN3
DN3
RESET#
16
EMC2102_DP3
DP3
NC#15
15
AFTE14P-GP
TP187
EMC2102_FAN_DRIVE
AFTE14P-GP
TP188
R107 1
2
0R2J-2-GP DY
THRM# 18
EMC2102_CLK_SEL
GND = Internal Oscillator Selected

+3.3V = External 32.768kHz Clock Selected
EMC2102_PWROK 32
POWER_OK#
THERMTRIP#
SYS_SHDN#
TRIP_SET
EMC2102_FAN_TACH_1
14
13
EMC2102-DZK-GP
12
GND = Channel 1
OPEN = Channel 3
+3.3V = Disabled
11
EMC2102_DP2
EMC2102
C373 must be near EMC2102
C375 must be near Q8
NC#21
DN2
C125
SC470P50V3JN-2GP
2.System Sensor, Put between CPU and NB.
27
28
3
EMC2102_DN2
FAN_MODE
DY
C140
SC470P50V3JN-2GP
84.03904.L06
DN1
NC#8
Q12
MMBT3904-3-GP
C374 must be near Q7
VDD_3V
ALERT#
1.For CPU Sensor

Layout notice : Both DN2 and DP2 routing
SHDN_SEL
C119
SC470P50V3JN-2GP
H_THERMDA
H_THERMDC
FANa
SCD1U16V2KX-3GP
TACH
U15
GND
C118
VDD_5Va
29
49D9R2F-GP
26
EMC2102_VDD_3D3
10
SMBC_Therm 30
SMBD_Therm 30
74.02102.A73
3D3V_S0
EMC2102_SHDN
RN6
EMC2102_CLK_SEL 5
THRM#
6
7
8
10KR2J-3-GP
C372 must be near EMC2102
3D3V_S0
R291
3.HW T8 sensor
DY
EMC2102_FAN_mode
4
3
2
1
3D3V_S0
SRN10KJ-6-GP
VGATE_PWRGD
C397
PURE_HW_SHUTDOWN#
1
S
R106
240KR3-GP
2N7002-11-GP
C111
3D3V_S0
RN65
CLK_32K
5
6
7
8
3D3V_AUX_S5
R108
10R2F-L-GP
1
2
CLK_32K_R
4
3
2
1
PURE_HW_SHUTDOWN#
RSMRST#
EMC2102_FAN_mode
R290
10KR2F-2-GP
TRIP_SET Pin Voltage

V_DEGREE
=(((Degree-75)/21)
R110
3KR2F-GP
T8 90 degree
84.27002.N31
SRN10KJ-6-GP
3D3V_AUX_S5
32K suspend clock output
ai
l.c
83.R2003.F81
tm
Wistron Corporation
ho
RSMRST# 30,32
Q11

2N7002-11-GP
84.27002.N31
f@
C113 DY
SCD1U16V2ZY-2GP
Title
Size
xa
in
(dummy, KBC already delay)

RSMRST#
Thermal/Fan Controllor
Document Number
he
1
S
BAT54-7-F-GP
PURE_HW_SHUTDOWN#
om
D12
DY
7,18,34 VGATE_PWRGD
PM_SUS_CLK
Q10
18
V_DEGREE
SCD1U16V2ZY-2GP
GND = Fan is OFF

OPEN = Fan is at 60% full-scale
+3.3V = Fan is at 75% full-scale
RUN_POWER_ON
SCD1U16V2ZY-2GP
10KR2J-3-GP
C121
SC470P50V3JN-2GP
DY
C83
SC470P50V3JN-2GP
DY
C
84.03904.L06
R113
Q7
MMBT3904-3-GP
Layout notice : Both DN3 and DP3 routing

Rev
SC
Cathedral Peak II
Sheet
21
of
43
SATA ODD Connector
SATA Connector
ODD1
P3
P2
+5V
+5V
P1
P4
ODD_DP
ODD_MD
TP161 TPAD30
1
2
R199
10KR2J-3-GP
DY
TC23
16
17
18
19
20
21
22
NP2
24
SATA_RXP0 17
SATA_RXN0 17
C499
SCD1U16V2ZY-2GP
62.10065.541
5V_S0
SC10U10V5ZY-1GP
SKT-SATA7P+6P-39-GP-U
TC10
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
C229
DP
MD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A+
A-
23
NP1
1
D23
SSM24PT-GP
S2
S3
9
8
P6
P5
S7
S4
S1
17 SATA_TXP1
17 SATA_TXN1
5V_S0
GND
GND
GND
GND
GND
GND
GND
B+
B-
S6
S5
17 SATA_RXP1
17 SATA_RXN1
SATA1
SATA_TXN0 17
SATA_TXP0 17
SKT-SATA22P-27-GP
62.10065.471
Wistron Corporation
Title
Size
HDD & CDROM
Document Number
Rev
Cathedral Peak II
Date:
5
Sheet
1
22
SC
of
43
5V_USB1_S0
USB1
USB1
5V_USB1_S0
5
5V_S5
5V_USB1_S0
U34
G545A2P8U-GP
74.00545.A79
2nd: 22.10218.T51
3nd: 22.10218.P01
2nd source 74.09711.079

18
5V_USB1_S0
USB_OC#0
1
USB2
USB2
1
2
EC124
SCD1U16V2ZY-2GP
2
3
4
5V_USB2_S0
6
5V_S5
U57
5V_USB2_S0
SKT-USB-198-GP
RT9711BPF-GP
5V_USB2_S0
DY
2
74.09711.079
USB3
30 USB_PWR_EN#
EC14
SCD1U16V2ZY-2GP
USB3
5
R464
0R0402-PAD
2
1
2
1
DY
EC183
TC28
DY
2
USB_OC#4 18
1
USB_OC#4
1
60mil
8
7
6
5
VOUT
VOUT
VOUT
FLG#
EC184
SC1000P50V3JN-GP
USB_PWR_EN#
GND
VIN
VIN
EN/EN#
SCD1U16V2ZY-2GP
C45
SC4D7U10V3KX-GP
2nd: 22.10218.T51
3nd: 22.10218.P01
1
2
3
4
ST100U6D3VBM-5GP
22.10218.W51
USBPN4
USBPP4
1
USB_2USB_2+
R293
0R0402-PAD
18
18
EC115
DY
R292
0R0402-PAD
2
1
2
1
USBPN2
USBPP2
EC114
DY
DY
18
18
DY
GND
OC#
EN/EN#
TC14
SC1000P50V3JN-GP
5
4
USB_PWR_EN#
100 mil
TC15
SCD1U16V2ZY-2GP
22.10218.W51
8
7
6
ST150U6D3VDM-18GP
SKT-USB-198-GP
OUT#8
OUT#7
OUT#6
ST150U6D3VBM-2-GP
C424
SC4D7U10V3KX-GP
IN#3
IN#2
3
2
R279
0R0402-PAD
2
3
4
USBPN0
USBPP0
1
USB_0USB_0+
18
18
R278
0R0402-PAD
2
1
2
1
1
USB_4USB_4+
2nd source 74.00545.A79
2
3
4
R463
0R0402-PAD
6
SKT-USB-198-GP
22.10218.W51
BLUETOOTH MODULE
MDC 1.5 CONN
1.5A / High Active Voltage 2V
MDC1
BLUETOOTH_EN 30
4
6
8
10
12
17
18
R398
0R0402-PAD
C542
SC22P50V2JN-4GP
BLUE1
20.F0917.012
C531
SC100P50V2JN-3GP
DY
2nd: 20.F0604.012
4
3
2
USB_5USB_5+
3D3V_BT_S0
USBPN5
USBPP5
3D3V_S5
3D3V_S5
ACZ_BTCLK_MDC 17
TYCO-CONN12A-2-GP-U1
DY
15
14
2
3
5
ACZ_SYNC_A
7
ACZ_SDATAIN1_A
9
11
1ACZ_RST#_MDC
NP2
16
18
18
C296
1
R222
100KR2J-1-GP
EC21 put near

BLUE1 / all
USB put one
choke near
connector by
EMI request
17,28 ACZ_RST#
R232
0R0402-PAD
2
1
13
NP1
1
RN76
SRN39J-GP
8
7
6
5
SC4D7U10V5ZY-3GP
2nd:74.05240.A7F
(G5240B1T1U-GP)
1
2
3
4
17,28
ACZ_SYNC
17 ACZ_SDATAIN1
RT9711-APBG-GP
74.09711.A7F
ACZ_SDATAOUT
17,28 ACZ_SDATAOUT
C573
SC4D7U10V5ZY-3GP
2
DY
C295
DUMMY-C2
2
EC80 DY
SCD1U16V2ZY-2GP
VOUT
VIN
GND
NC#3 EN/EN#
1
2
3
3D3V_S0
U26
3D3V_BT_S0
3D3V_BT_S0
13
14
15
11
12
16
17
18
Wistron Corporation
5
USB_51
USB_5+ 1
3D3V_BT_S0 1
ETY-CON4-21-GP-U
20.F0984.004
2nd: 20.D0197.104
3nd: 20.F0689.004
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
TP134
TP136
TP133
Title
USB/BLUETOOTH/MDC
Size
R233
0R0402-PAD
Document Number
Rev
Cathedral Peak II
Sheet
SC
23
of
43
ai
l.c
om
tm
ho
f@
xa
in
he
C297
SC4D7U10V5ZY-3GP
3D3V_S0
3D3V_D_S0
3D3V_A_S0
XD_CD#
SD_WP
SD_CD#
XD_D4
XD_D5/MS_BS
SD_DAT1/XD_D3/MS_D1_1
SD_DAT0/XD_D6/MS_D0
SD_DAT7/XD_D2/MS_D2
MS_INS#
SD_DAT6/XD_D7/MS_D3
SD_CLK/XD_D1/MS_CLK
SD_DAT5/XD_D0
SD_DAT4/XD_WP#
XD_R/B#
SD_DAT3/XD_WE#
SD_DAT2/XD_RE#
XD_ALE
XD_CE#
XD_CLE
R428
0R0603-PAD
1
2
R418
0R0603-PAD
1
2
CARD_3D3V_S0
C539
SC1U10V3KX-3GP
R400
0R2J-2-GP
1 SD_DAT1/XD_D3/MS_D1
DY
XD_D4
R410
0R0402-PAD
D
DY
3D3V_D_S0
AV_PLL
45
36
14
2
44
MODE_SEL
SD_CMD
GPIO0
RREF
RST#
EECS
EESK
EEDO
EEDI
30
7
3
DP
DM
5
4
DY VCC
DU
ORG
GND
8
7
6
5
C565
SCD1U16V2ZY-2GP
DY
M93C46-WMN6TP-GP
6
12
32
46
-4
DY C516
RTS5158E-GR-GP
71.05158.A0G
SC5D6P50V2CN-1GP
1
12M_XI
R416
0R0402-PAD
2
1
3D3V_D_S0
DY
DY
1
DY
2
USBPN10
R388
270KR2F-GP
EEDO
EEDI
18
2
1 USB_10+
R396 0R0402-PAD
2
1USB_10R395 0R0402-PAD
12M_XI
12M_XO
USBPP10
18
EESK
EECS
1
1
R387
10KR2J-3-GP
DY
DY
S
C
D
Q
C527
SCD1U16V2ZY-2GP
RST#
GND
GND
GND
GND
1
2
3
4
3D3V_A_S0
DY
XDAL_CTR
1
2
C511
SC47P50V2JN-3GP
C510
SC1U10V3KX-3GP
24
22
EEDO
EEDI
RREF
MODE_SEL
R386
100KR2J-1-GP
RST#
MODE_SEL
SD_CMD
6K19R2F-GP
3D3V_D_S0
D3V3
D3V3
C529
SCD1U16V2ZY-2GP
K VBUS_LED
R394
1
LED-W-23-GP
33
11
EESK
EECS
68R2-GP
VBUS_R
NC#30
NC#7
NC#3
15
18
3V3_IN
17
16
DY
DY
XTLI
XTLO
3D3V_S0
LED7
ADY
VREG
XTAL_CTR
R429
2
C548
SCD1U16V2ZY-2GP
DY
-1
3D3V_D_S0
C534
SCD1U16V2ZY-2GP
1
2
C554
SC4D7U6D3V5KX-3GP
3V_VBUS_S0
3D3V_S0
10
47
48
VREG
R423
0R0603-PAD
1
2
U52
MS_D5
MS_D4
CARD_3V3
AV_PLL
13
C524
SCD1U16V2ZY-2GP
R409
0R0603-PAD
1
2
VREG
19
20
21
23
25
26
27
28
29
31
34
35
37
38
39
40
41
42
43
U43
SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
SP15
SP16
SP17
SP18
SP19
C544
SC1U10V3KX-3GP
X4
XTAL-12MHZ-11GP
82.30006.191
12M_XO
C515
SC5D6P50V2CN-1GP
R393
0R0402-PAD
2
1
CLK48_5158E
12M_XO
5 IN1 CARD-READER (SD/MMC/MS/MS PRO/XD)

CARD1
1
2
C519
SC4D7U10V5ZY-3GP
CARD_3D3V_S0
33
23
14
XD_VCC
SD_VCC
MS_VCC
XD_R/B#
SD_DAT2/XD_RE#
XD_CE#
XD_CLE
XD_ALE
SD_DAT3/XD_WE#
SD_DAT4/XD_WP#
XD_CD#
1
2
3
4
5
6
7
34
XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP
XD_CD_SW
SD_DAT5/XD_D0
SD_CLK/XD_D1/MS_CLK
SD_DAT7/XD_D2/MS_D2
XD_D4
XD_D5/MS_BS
SD_DAT0/XD_D6/MS_D0
SD_DAT6/XD_D7/MS_D3
8
9
26
27
28
30
31
32
XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7
CARD_3D3V_S0
C505
SCD1U16V2ZY-2GP
DY
Pin27 change to
for XD fail
A
NP1
NP2
NP1
NP2
SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3
25
29
10
11
SD_DAT0/XD_D6/MS_D0
SD_DAT1/XD_D3/MS_D1
SD_DAT2/XD_RE#
SD_DAT3/XD_WE#
SD_WP_SW
SD_CD_SW
SD_CMD
SD_CLK
35
36
12
24
SD_WP
SD_CD#
SD_CMD
SD_CLK/XD_D1/MS_CLK
MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3
19
20
18
16
SD_DAT0/XD_D6/MS_D0
SD_DAT7/XD_D2/MS_D2
SD_DAT6/XD_D7/MS_D3
MS_SCLK
MS_INS
MS_BS
15
17
21
SD_CLK/XD_D1/MS_CLK
MS_INS#
XD_D5/MS_BS
GROUND
GROUND
4IN1_GND
4IN1_GND
37
38
13
22
Wistron Corporation
Title
CARDBUS38P-GP-U
20.I0079.001
CARDREADER- RTS5158E
Size
2nd: 20.I0081.001
3rd: 20.I0067.001
4
Rev
Cathedral Peak II
Date:
Document Number
Sheet
24
1
SC
of
43
3D3V_LAN_S5
3D3V_S0
3D3V_LAN_S5
1
2
3
4
8Kbit
LANPWR
2 R49
1
4K7R2J-2-GP
VPD_DATA
VPD_CLK
1D8V_LAN_S5
RN3
SRN4K7J-10-GP
U13
1
2
3
4
1D8V_LAN_S5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8
7
6
5
8
7
6
5
2
0R2J-2-GP
R66
1 0R0603-PAD
2
LAN_CLKREQ#
3D3V_LAN_S5
3D3V_LAN_S5
DY
R61
VPD_CLK
VPD_DATA
LANLOM
AT24C08BN-SH-T-GP
NC#51
52
NC#52
18 PCIE_TXN1
53
RX_N
18 PCIE_TXP1
33
VDD
SPI_DO
36
34
37
39
35
SPI_DI
SPI_CS
SPI_CLK
40
41
43
42
44
45
48
47
38
VPD_CLK
26
MDI3+
26
MDIP3
RESERVED#29
29
AVDD
28
RX_P
MDIN2
27
MDI2-
26
REFCLKP
MDIP2
26
MDI2+
26
REFCLKN
RESERVED#25
25
57
SMALERT#
RESERVED#24
24
58
VDD
AVDD
59
LED_ACT#
AVDD
22
MDI1-
26
MDI1+
26
MDIN1
61
VDDO_TTL
MDIP1
20
62
LED_LINK1000#
63
LED_DUPLEX#
19
MDIN0
18
MDI0-
26
MDIP0
17
MDI0+
26
RSET
XTALO
XTALI
16
15
14
VDD
13
VAUX_AVLBL
SWITCH_VCC
12
LOM_DISABLE#
SWITCH_VAUX
9
11
10
AVDDH/3_3V
8
WAKE#
VDD
7
PLACE PNP TO CHIP ACAP

CTRL12 PIN TRACE IS 25MIL
PERST#/TSTPT
GND
CTRL18
SMCLK
65
AVDD
CTRL12
64
SC1KP50V2KX-1GP
LED_LINK10/100#
21
C59
DY
23
60
VDD
LAN_LED_10/100/1G
2
0R2J-2-GP
VDDO_TTL
26 10M/100M/1G_LED#
88E8071-B0-GP
71.88071.A03
E
B
4
2
1D2V_LAN_S5
R55
1
100R2J-2-GP
C44
SC100P50V2JN-3GP
CTRL12
CTRL18
PLT_RST1#_LAN
LANRSET
R36
1
2
4K99R2F-L-GP
LANLOM
Q8
DCP69A-13-GP
1D2V_LAN_S5
C356
SC4D7U6D3V3KX-GP
SCD1U10V2KX-4GP
7,18,27,30,31 PLT_RST1#
C
C
C72
DY
3D3V_LAN_S5_2
R79
4K7R2J-2-GP
MDI3-
56
CTRL12
31
30
55
SMB_ALERT#_LAN
3D3V_LAN_S5
MDIN3
54
DY
R70
Main source:72.24C08.J01
2nd source:72.24C08.I01
32
3 CLK_PCIE_LAN#
26 LAN_ACT_LED#
R270
1
2
0R0603-PAD
Pull up for AT24C08 another pull low

NC#32
3 CLK_PCIE_LAN
10KR2J-3-GP
R71
DY
1
2
VDD
TX_N
51
VDDO_TTL
50
VPD_DATA
CLKREQ#
TX_P
SMDATA
49
PCIE_RXN1_LAN
VDD
PCIE_RXP1_LAN
3D3V_S5
VDDO_TTL
18 PCIE_RXN1
SCD1U10V2KX-5GP 2
TESTMODE
SCD1U10V2KX-5GP 2
C56
VDD
C55
VMAIN_AVLBL
U8
18 PCIE_RXP1
46
72.24C08.J01
R41
18,27 PCIE_WAKE#
1
2
10MR2J-L-GP
LANX1
LANX2
1
2
1D8V_LAN_S5
C30
SC12P50V2JN-3GP
C23
SC15P50V2JN-2-GP
1D2V_LAN_S5
DY
2
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
1
2
C330
SCD1U10V2KX-4GP
1
2
C327
SCD1U10V2KX-4GP
1
2
C328
SC1KP50V2KX-1GP
1
2
C57 DY
SC1KP50V2KX-1GP
1
2
C329
SC1U6D3V2KX-GP
1
2
C347
SC1U6D3V2KX-GP
1
C343
1
C333
1
C25
1
C339DY
1
C35
1
C346
1
C344
1
C334
2
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
SC1KP50V2KX-1GP
2
SC1KP50V2KX-1GP
2
SC1U6D3V2KX-GP
2
SC1KP50V2KX-1GP
2
SC1U6D3V2KX-GP
2
SC1KP50V2KX-1GP
om
DY
1D8V_LAN_S5
C69
SCD1U10V2KX-4GP
2
SC1KP50V2KX-1GP
2
DY SC1KP50V2KX-1GP
ai
l.c
84.00069.A1B
1
C345
1
C338
1
C337
1
C340
1
C335
Wistron Corporation
tm
-1

ho
4
2
Title
f@
1
Q9
DCP69A-13-GP
3D3V_LAN_S5
CTRL18
C77
SC10U6D3V5KX-1GP
SB
R80
4K7R2J-2-GP
2
1
1
2
Document Number
Rev
SC
Cathedral Peak II

5
xa
in
88E8071
Size
A3
he
1
2
DY
SC4D7U6D3V3KX-GP
DY
C67
C
C
C64
SCD1U10V2KX-4GP
C76
SC10U6D3V5KX-2GP
R68
1
2
0R0603-PAD
1
C60
SC10U6D3V5KX-2GP
SCD1U10V2KX-4GP
DY
C53
2 LANX1
XTAL-25MHZ-67GP
PLACE PNP TO CHIP ACAP

CTRL25 PIN TRACE IS 25MIL
3D3V_LAN_S5
82.30020.571
X1
LANX2 1
3D3V_S5
DY
DY
C75
SC10U6D3V5KX-1GP
C68
SCD1U10V2KX-4GP
-1
84.00069.A1B
Sheet
1
25
of
43
LAN Connector
1.route on bottom as differential pairs.

2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except
RJ-45 moat.
LAN_ACT_LED#
10M/100M/1G_LED#
DY
SB
DY
C311
C310
SC1KP50V2KX-1GP SC1KP50V2KX-1GP
XF1
25
MDI0+
23
RJ45_1
25
MDI0-
3
1
22
24
RJ45_2
MCT1
4
5
21
20
MCT2
RJ45_3
1D8V_LAN_S5
DY
25
MDI1+
LAN Connector
RJ1
25 10M/100M/1G_LED#
C10
SCD1U10V2KX-4GP
C9
SCD1U10V2KX-4GP
R31
1
2 V_DAC
0R0603-PAD
14
9
10
11
1
CONN_PWR
RJ45_1
25
MDI1-
19
RJ45_6
25
MDI2+
17
RJ45_4
RJ45_2
RJ45_3
RJ45_4
RJ45_5
RJ45_6
RJ45_7
RJ45_8
CONN_PWR2
25 LAN_ACT_LED#
25
16
18
RJ45_5
MCT3
MDI3+
15
14
MCT4
RJ45_7
MDI3-
12
13
RJ45_8
RJ45-92-GP
22.10245.E91
DY
C12
SCD1U10V2KX-4GP
C11
SCD1U10V2KX-4GP
25
9
7
10
11
MDI2-
9:GREEN
13:Orange
2
3
4
5
6
7
8
12
13
15
LAN Link: Green(9), behavior is the

same for 10/100/1000 bits
25
LAN Data: Yellow(13), when LAN is

transfering data.
XFORM-275-GP
68.89240.30A
DOC_TIP,DOC_RING,TIP,RING:
W/S : 10/100 @ Surface layers
10/20 @ Inner layers
2
CONN_PWR2
470R2J-2-GP
CONN_PWR
470R2J-2-GP
EC87
DY
8
7
6
5
DY
1
2
3
4
RN40
SRN75J-1-GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
EC90
MCT1
MCT2
MCT3
MCT4
1
R243
1
R252
3D3V_LAN_S5
MCT_R
C312
SC1KP2KV8KX-GP
Wistron Corporation
Title
LAN CONN
Size
A3
Date:
A
Document Number
Rev
SC
Cathedral Peak II
Sheet
E
26
of
43
NEWCARD Connector
NEW2
Mini Card Connector(WLAN)
CARDBUS-SKT107-GP
21.H0168.001
1D5V_S0
2nd: 21.H0182.001
3D3V_MINI
NEW1
MINI_WAKE#
TP12
3 CLK_PCIE_MINI1#
3 CLK_PCIE_MINI1
18 PCIE_TXN2
18 PCIE_TXP2
3D3V_MINI
5V_S5
3D3V_S5
NC#16
NC#14
NC#13
NC#5
NC#4
TPS2231RGP-GP-U
74.02231.073
TPAD28 TP36
WLAN_LED#_MC 16
TPAD28 TP42
3D3V_S0
R454 0R2J-2-GP
1
2
3D3V_S5
R455 0R2J-2-GP
1
DY 2
3D3V_MINI
3D3V_S5
C96
DY
C27
C87
C97
1
2
DY
GND
16
14
13
5
4
TC8
ST330U6D3VDM-17GP
1D5V_S0
SCD1U16V2ZY-2GP
C576
SCD1U16V2ZY-2GP
3D3V_S0
3D3V_NEW_S0
Place them Near to Connector
1D5V_NEW_S0
om
ai
l.c
1
C513
SCD1U16V2ZY-2GP
tm
Wistron Corporation
ho

f@
Title
NEW CARD/MINI CARD

Size
xa
in
C283
DY
C282
SC1U10V3ZY-6GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C493
3D3V_NEW_LAN_S5
-1
C496
DY
SC1U10V3ZY-6GP
Document Number
Rev
Cathedral Peak II
A
he
SC1U6D3V2KX-GP
3D3V_S0
3D3V_NEW_S0
1D5V_S0
1D5V_NEW_S0
3D3V_S5
3D3V_NEW_LAN_S5
3D3V_NEW_S0
LED_WPAN#
Place near MINIC1
SCD1U16V2ZY-2GP
2
3
12
11
17
15
-1
C509
SCD1U16V2ZY-2GP
LED_WWAN#
3D3V_S0
3.3VIN
3.3VOUT
1.5VIN
1.5VOUT
AUXIN
AUXOUT
SMB_CLK 18,20
SMB_DATA 18,20
USBPN7 18
USBPP7 18
C502
SC100P50V2JN-3GP
STBY#
RCLKEN
OC#
THERMAL_PAD
3D3V_S0
4
3
SRN33J-5-GP-U
20
8
9
10
6
1D5V_S0
1D5V_NEW_S0
Place them Near to Chip
DY
PLT_RST1# 7,18,25,30,31
SC1U6D3V2KX-GP
R369
1
100R2J-2-GP
WIRELESS_EN 30
PLT_RST1# 7,18,25,30,31
R85
300R2F-GP
62.10043.461
SHDN#
PERST#
CPUSB#
CPPE#
SYSRST#
2
RN5
SMB_CLK_WLAN 1
SMB_DATA_WLAN2
DY 2
10KR2J-3-GP
PLT_RST1#_WLAN
3
4
DY
PLT_RST1#_NEWCARD
1
18
19
21
R78
C80
SC100P50V2JN-3GP
SRN100KJ-6-GP
18,30,36,37 PM_SLP_S4#
PM_SLP_S3#
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
SKT-MINI52P-13-GP
RN54
CPUTSB# 2
CPPE#
1
18,30,32,36,37,38
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NP2
54
E51_RxD
E51_TxD
18 PCIE_RXN2
18 PCIE_RXP2
20.F1336.026
U38
4
6
8
10
12
14
16
DY
30
30
FCI-CON26-7-GP
TPS2231_PERST#
3
5
7
9
11
13
15
TPAD30
53
NP1
1
3D3V_MINI
MINIC1
NP2
26
25
18 PCIE_TXP5
24
18 PCIE_TXN5
23
22
18 PCIE_RXP5
21
18 PCIE_RXN5
20
19
3 CLK_PCIE_NEW
3D3V_NEW_S0
18
3 CLK_PCIE_NEW#
CPPE#
17
NEW_PIN16
TP127
16
15
14
3D3V_NEW_LAN_S5
TPS2231_PERST#
13
12
PCIE_WAKE#_NEW
1
2
11
DY
18,25 PCIE_WAKE#
R219 0R2J-2-GP
10
1D5V_NEW_S0
RN34
9
1
4 SMB_DATA_NEW 8
DY
18,20 SMB_DATA
2
3 SMB_CLK_NEW
7
18,20 SMB_CLK
CONN_TP1 6
SRN33J-5-GP-U
CONN_TP2 5
TP123
CPUTSB#
TP122
4
3
18 USBPP9
2
18 USBPN9
1
NP1
Sheet
E
27
SC
of
43
5V_S0
4.75V / 300mA
U21
1
2
3
EN
GND
VIN
NC#5
VOUT
5VA_S0
D
RT9198-4GPBG-GP
"VAUX" Pull high to enable standby mode

AMP_BEEP_1
2
SCD47U16V3ZY-3GP
2AUDIP_PC_BEEP
RESET#
BCLK
2 SEL_MIC
1KR2F-3-GP
1 C232
1 C238
2 C226
2 C228
MIC1-L_PORT-B
MIC1-R_PORT-B
IMT_MIC1-L
IMT_MIC1-R
LINE1-VREFO
GPIO1
21
22
16
17
MIC1-L_PORT-B
MIC1-R_PORT-B
MIC2-L_PORT-F
MIC2-R_PORT-F
32
28
30
MIC1-VREFO-R
MIC1-VREFO-L
MIC2-VREFO
DMIC-12/GPIO0
DMIC-34/GPIO3
2
3
VREF
JDREF
MONO-OUT
40
37
27
34
13
5
8
AC97_DATIN
1
R163
2
39R2J-L-GP
ACZ_SDATAOUT 17,23
ACZ_SDATAIN0 17
SPDIFO
EAPD
48
47
NC#45
DMIC-CLK
45
46
HP-OUT-L_PORT-A
HP-OUT-R_PORT-A
39
41
FRONTL 29
FRONTR 29
LINE-OUT-L_PORT-D
LINE-OUT-R_PORT-D
35
36
SOUNDL 29
SOUNDR 29
AMP_SHUTDOWN# 29,30
ALC_EAPD
D14
BAW56-7-F-GP
DY
R187
0R0402-PAD
2ND = 83.00056.G11
R170
2 3D3V_S0
DY
10KR2J-3-GP
ALC268-GR-GP
71.00268.00G
2
JDREF
1
1
C269
SCD47U16V3ZY-3GP
R165
10KR2F-2-GP
MONO-OUT
TP116
TPAD30
R198
20KR2F-L-GP
DY
1
2
DY
MIC_JD# 29
Change to 71.00268.A0G
VREF
C268
SC10U10V5ZY-1GP
R175
1
2
20KR2F-L-GP
Sense resistors need close codec
29 ALC268_EAPD
AVSS1
AVSS2
DVSS
DVSS
26
42
4
7
C577
SC4D7U10V5ZY-3GP
C264
SC4D7U10V5ZY-3GP
C265
SC4D7U10V5ZY-3GP
SRN2K2J-2-GP
MIC1V_R
MIC1V_L
MIC2-VREFO
8
7
6
5
2
1
2
3
4
SENSE_B
SENSE_A
44
43
NC#44
NC#43
RN46
SC22P50V2JN-4GP
SDATA-OUT
SDATA-IN
ALC268
29
1
SC4D7U10V3KX-GP 2
SC4D7U10V3KX-GP 2
SC1U16V3ZY-GP 1
SC1U16V3ZY-GP 1
29
31
LINEOUT_JD#
ALC268_SENSE
CD-L
CD-R
CD-G
R340
LINE1-L_PORT-C
LINE1-R_PORT-C
NC#14
NC#15
R178
1
2
39K2R2F-L-GP
C211
1
2DY
18
20
19
23
24
14
15
PCBEEP
RESET#
SYNC
BCLK
NC#33
DVDD
DVDD-IO
AVDD1
AVDD2
U20
12
11
10
6
33
1
9
25
38
ACZ_RST# 17,23
ACZ_SYNC 17,23
ACZ_BITCLK 17
2 R164
1
0R0402-PAD
1
2
C212
DY
SC22P50V2JN-4GP
C204
SC100P50V2JN-3GP
SPKR_SB_1
SCD47U16V3ZY-3GP
29 AUD_MICIN_L
29 AUD_MICIN_R
16
INT_MIC
C210 SC100P50V2JN-3GP
2
R162
2
1
100R2J-2-GP
1
R159
10KR2J-3-GP
C240
SCD1U10V2KX-4GP
ACZ_SPKR
2
SCD47U16V3ZY-3GP
C194
1
C206
DY
SC10U10V5ZY-1GP
18
KBC_BEEP
30
SRN47KJ-1-GP
C247
SC10U10V5ZY-1GP
C208
1
AUDIO_BEEP
SC1U10V3KX-3GP
C188
1
C213
SCD1U10V2KX-4GP
5
6
7
8
4
3
KBC_BEEP_1 2
1
DY
RN21
C182
1
AMP_BEEP
C267
SC10U10V5ZY-1GP
5VA_S0
3D3V_S0
29
74.09198.A7F
74.09091.F3F
G9091-475T12U-GP
C272
SC1U10V3KX-3GP
Wistron Corporation
Title
Size
A3
Azalia codec ALC268

Document Number
Rev
SC
Cathedral Peak II
Sheet
1
28
of
43
FRONTL
C163
SCD1U16V2ZY-2GP
SPK_EN#
SET
BIAS
HP_EN
SPK_EN#
C153
SC1U10V3KX-3GP
U55
SD05C-1-GP
om
ai
l.c
tm
ho

f@
Title
AUDIO AMP AND JACK

Size
xa
in
DY
Wistron Corporation
R335
1KR2J-1-GP
DY
2
SPKR_L+1
DY
4
3
SRN51J-GP
C473
R329
SC680P50V2KX-2GP
DY
1
2
2
1
C466
28
SPKR_R+1
RN68
1
2
SPKR_L_A1
DY
22.10133.B21
LINEOUT_JD#
SPKR_R_A1
EC152
PHONE-JK235-GP-U2
1
B
U56 DY
SD05C-1-GP
-1
LINEOUT_JD#
1KR2J-1-GP
TP117
TP114
TP113
TP109
TP160
TP159
NP2
NP1
5
4
3
6
2
1
SC680P50V2KX-2GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
1
SPKR_R_A1
DY
SC1KP50V2KX-1GP
1
1
1
1
1
1
2
SPKR_L_A1
2nd: 22.10251.491
3nd: 22.10147.131
LINE OUT
LINEOUT_JD#
SPKR_R_A1
SPKR_L_A1
MIC_JD#
AUD_MICIN_R
AUD_MICIN_L
D27
1SS400PT
DY
1
2
22.10133.B01
For ESD
5V_S0
D28
1SS400PT
DY
PHONE-JK233-GP-U3
LOUT1
2nd: 22.10251.511
3nd: 22.10147.151
DY
5V_S0
Document Number
Rev
SC
Cathedral Peak II
D
he
1
2
1
2
1
2
2nd: 20.F0984.002
SHIELDING
SC100P50V2JN-3GP
20.D0197.102
DY
EC145
DY
ACES-CON2-1-GP-U2
EC4
DY
EC140
SC1KP50V2KX-1GP
EC3
SC100P50V2JN-3GP
TP1
TP2
TP3
TP4
DY
SC100P50V2JN-3GP
SC100P50V2JN-3GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
EC2
SRN1KJ-7-GP
R326
SC1KP50V2KX-1GP
DY
AUD_MIC_L
DY 10KR2J-3-GP
DY
2
4
EC1
1
1
1
1
R321
10KR2J-3-GP
AUD_MIC_R
3
4
28 AUD_MICIN_L
INTSPK_L
3
1
SPKR_L-
RN66
2
1
28 AUD_MICIN_R
20.D0197.102
ACES-CON2-1-GP-U2
MIC_JD#
28
remove to LED Board
NP2
NP1
5
4
3
6
2
1
SC1KP50V2KX-1GP
2
4
SPKR_L+
MICIN1
2
DY
SPKR_R-
AMP_SHUTDOWN# 28,30
Analog Int. Mic
MIC IN
EC60
INTSPK_R
3
1
Q14
2N7002-11-GP
SHIELDING
Internal Speaker
R147
10KR2J-3-GP
5V_S0
3D3V_S0
SPKR_L+1
SPKR_R+1
APA2057ARI-TRL-GP
SPKR_R+
SPKR_LSPKR_L+
SPKR_RSPKR_R+
5V_S0
DY
ALC268_EAPD 28
SPKR_R+
SPKR_R-
74.02057.01G
AMP_SHUTDOWN# 28,30
1
2
R142
0R0402-PAD
C139
SC1U10V3KX-3GP
C162
SCD1U16V2ZY-2GP
DY
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DY 0R2J-2-GP
HP_EN
AMP_BEEP 28
SPKR_L+
SPKR_L-
GND
BEEP
AMP_EN#
SET
BIAS
HP_EN
PGND
ROUT+
ROUTPVDD
HVDD
HP_L
HP_R
HVSS
CVSS
R139
0R2J-2-GP
1
VDD
GND
INR_A
INR_H
INL_A
INL_H
PGND
LOUT+
LOUTPVDD
CVDD
CP+
CGND
CP-
U18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
INR_A
INR_H
INL_A
INL_H
BIAS
C161
SC1U10V3KX-3GP
R143
C168
SC2D2U6D3V3MX-1-GP
C137
INL_H
5V_S0
2
R138
30KR2F-GP
INR_H
2
R126
40K2R2F-GP
28
C138
SC10U6D3V5MX-3GP
-1
R128
40K2R2F-GP
C129
SC3D3U10V5KX-2GP
3D3V_S0
SET
6DB
SCD1U16V2ZY-2GP
FRONTR
INL_A
C128
SC3D3U10V5KX-2GP
28
5V_S0
R127
6K8R2F-2-GP
SOUNDL
Layout Note
C218,C219,C220 near U110
R137
13KR2F-GP
C133
SC1U10V3KX-3GP
4
SB
INR_A
28
SOUNDR
5V_S0
R129
2KR2F-3-GP
28
C132
SC1U10V3KX-3GP
AUDIO OP AMPLIFIER
-1
Sheet
E
29
of
43
D24
17
KBRCIN#
17
KA20GATE
18
ECSCI#_1
KBRCIN#_KBC
KA20GATE_KBC
ECSCI#_KBC
31
2 R376
1
0R0402-PAD
SPI_WP#
7,18,25,27,31
SPI_WP_R#
2 R392
1
0R0402-PAD
PLT_RST1#
28
37
2
20
1
13
ECRST#
KBRST#
SCI#
GA20
PCIRST#
KBC_BEEP
CHG_I_PWM
KBC_GPIO12
SPI_WP_R#
21
23
26
27
28
29
PWM0
PWM1
FANPWM1
FANPWM2
FANFB1
FANFB2
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
55
56
57
58
59
60
61
62
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
87
88
85
86
83
84
PSCLK3
PSDAT3
PSCLK2
PSDAT2
PSCLK1
PSDAT1
PLT_RST1#_1
KBC_BEEP
TP172
TP171
FOR KBC DEBUG
KBC_GPIO15
R360
DY
ECRST#
KBRCIN#_KBC
ECSCI#_KBC
KA20GATE_KBC
KCOL2
KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
0R2J-2-GP
R359
DY
1
RSMRST#_R
KA20GATE
KBRCIN#
C494
SC1U6D3V2KX-GP
3D3V_S0
4
3
2
1
Q19
MMBT3906-3-GP
RN53
0R2J-2-GP
5
6
7
8
RSMRST#
KCOL3
ECRST#
3D3V_AUX_S5
21,32
DY:
ISP Mode disable
TP125
TP130
TP166
TP167
TP165
TP169
SRN10KJ-6-GP
KCOL15
KROW0
E51_RxD
E51_TxD
3D3V_AUX_S5
TP129
TP124
TP126
TP128
KCOL8
KCOL9
KCOL10
KCOL11
TPCLK
TPDATA
KBC_GPIO0C
18,27,32,36,37,38
16
18,27,36,37
KBC_PWRBTN#
PM_SLP_S4#
40
7
14
3D3V_AUX_S5
PM_SLP_S3#
PM_SLP_S3#
BAT_IN#
GMCH_BL_ON
BRIGHTNESS
4
3
SRN100KJ-6-GP
16
STDBY_LED
27 WIRELESS_EN
23 BLUETOOTH_EN
31
SPICLK
39
CHG_ON#
14
18
LID_CLOSE#
ECSWI#
113
94
77
78
80
79
GPO3C
GPO3D
GPO3E
GPO3F
AD0
AD1
AD2
AD3
68
70
71
72
63
64
65
66
CCD_ON
USB_PWR_EN#
KBC_GPIO3E
CHG_BCTL1
AD_IA
97
98
99
100
101
102
103
104
105
106
107
108
FLASH_SEL
TP176
WIRELESS_BTN#
WIRELESS_BTN# 16
BT_BTN#
BT_BTN# 16
AMP_SHUTDOWN#
AMP_SHUTDOWN# 28,29
PM_PWRBTN#
PM_PWRBTN# 18,41
S5_ENABLE_KBC
RSMRST#_KBC
RSMRST#_KBC 18
AD_OFF
AD_OFF
40
WLAN_TEST_LED
WLAN_TEST_LED 16
BT_LED
BT_LED
16
DC_BATFULL
DC_BATFULL 16
GPXIOA11
TP177
AD_IA
GPXIOD0
GPXIOD1
GPXIOD2
GPXIOD3
GPXIOD4
GPXIOD5
GPXIOD6
GPXIOD7
SPICS#
WR#
RD#
GPIO50
AD5
GPIO52
128
120
119
89
76
90
AC_IN#
KBC_MATRIX0#
CHARGE_LED
GPIO0B
GPIO0C
GPIO0D
GPIO11
GPIO16
GPIO17
30
31
E51_TxD
E51_RxD
34
GPIO19
GPIO1A
GPIO53
GPIO55
36
91
93
NUM_LED#
CAP_LED#
FRONT_PWRLED
122
123
KBC_XI
KBC_XO
GPIO0A
GPIO18
8
7
6
5
RN30
1
2
3
4
WIRELESS_BTN#
BT_BTN#
8
7
6
5
S5_ENABLE_KBC
SRN10KJ-6-GP
R461
S5_ENABLE_KBC
S5_ENABLE
S5_ENABLE 32,35,41
2K2R2J-2-GP
Volume_Up#
Volume_Up# 16
Volume_Down#
Volume_Down# 16
BLON_OUT
BLON_OUT 14,16
SYS_PWR_ACK
TP132
E-BUTTON#
E-BUTTON# 16
KBC_THERMALTRIP#
KBC_THERMALTRIP#
KBC_GPXD6
TP131
CRT_DEC#
CRT_DEC# 15
109
110
112
114
115
116
117
118
GPIO7
GPIO8
16
32
23
39
3D3V_S0
17
18
19
25
LID_CLOSE#
ECSWI#
-1
USB_PWR_EN#
TP170
TP173
BAT_IN#
KBC_GPIO0C
GMCH_BL_ON
BRIGHTNESS
AD4
GPIO54
GPIO56
GPIO57
SPICLK
GPIO59
SMBC_Therm 21
SMBD_Therm 21
BAT_SCL 39,40
BAT_SDA 39,40
TP168
GPIO4
75
92
95
121
126
127
BAT_SCL
BAT_SDA
SMBD_Therm
SMBC_Therm
STDBY_LED
WIRELESS_EN
BLUETOOTH_EN
SPICLK
CHG_ON#
GND
GND
14
15
LID_CLOSE#
BAT_IN#
RN55
SRN4K7J-12-GP
SCD1U16V2ZY-2GP
2
R375
0R0603-PAD
KBC_PWRBTN#
PM_SLP_S4#
RN56
1
2
R3
1
2
1KR2J-1-GP
3
R381
1KR2J-1-GP
3D3V_S0
AGND
AD_OFF
SB
2
C498
1
2
AVCC
SCL1
SDA1
SDA2
SCL2
GPXIOA0
GPXIOA1
GPXIOA2
GPXIOA3
GPXIOA4
GPXIOA5
GPXIOA6
GPXIOA7
GPXIOA8
GPXIOA9
GPXIOA10
GPXIOA11
3D3V_AUX_S5
C528
C535
C533
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
L16
BLM11P600S
XCLKI
XCLKO
V18R
GPIO41
GPIO40
124
SPICS#
SPIDO
SPIDI
AC_IN#
31
31
31
39
3D3V_AUX_S5
R380
DY
CHARGE_LED
E51_TxD
E51_RxD
32
3D3V_S0
10KR2J-3-GP
27
27
RN57
8
7
6
5
3D3V_AUX_S5
16
NUM_LED# 16
CAP_LED# 16
FRONT_PWRLED
DY
C545
SC100P50V2JN-3GP
DY
C546
SC100P50V2JN-3GP
5V_AUX_S5
E51_RxD
TP174
R364
1
2
10KR2J-3-GP
C537
SC27P50V2JN-2-GP
KBC_XI
KB3310QF-GP
KBC_THERMALTRIP#
E-BUTTON#
Volume_Down#
Volume_Up#
16
C543
2 SC3D3U10V5KX-2GP
SEL_CP
KBC_GPIO40
74
73
1
2
3
4
SRN10KJ-6-GP
C514
SC100P50V2JN-3GP
22
33
125
111
96
9
67
69
11
24
35
10KR2J-3-GP
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
AGND
GND
GND
GND
1
2
3
4
DY
SERIRQ
LFRAME#
PCICLK
CLKRUN#
LAD0
LAD1
LAD2
LAD3
DY 1
KBC_GPIO15
5V_S5
R372
3
4
12
38
10
8
7
5
INT_SERIRQ
LPC_LFRAME#
PCLK_KBC
PM_CLKRUN#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
18
INT_SERIRQ
17,31 LPC_LFRAME#
3
PCLK_KBC
18
PM_CLKRUN#
PCLK_KBC
SC4D7P50V2CN-1GP
DY C520
17,31 LPC_LAD[0..3]
3D3V_AUX_S5
U39
CH731UPT-GP
2
2
71.03310.00G
X5
X-32D768KHZ-38GPU
change to 71.03310.A0G
SB
SEL_CP
82.30001.691
R379
1
1KR2J-1-GP
KBC_XO
2nd: 20.K0317.026
C538
SC22P50V2JN-4GP
Internal KeyBoard Connector
EC27
EC26
EC25
EC24
SRN10KJ-5-GP
TP_RIGHT
RN50
1
AFTE14P-GP
TP67
1KCOL17 EC40 1DY
2SC220P50V2JN-3GP
AFTE14P-GP
TP73
1KCOL0
2SC220P50V2JN-3GP
EC23 1DY
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
TP74
TP71
TP85
TP70
1
1
1
1
KROW0 EC41
KROW7 EC48
KROW6 EC47
KROW5 EC46
1
DY
1
DY
1
DY
1
DY
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
TPDATA
TPCLK
1
2
4
3
TP_DATA
TP_CLK
SRN33J-5-GP-U
TP_LEFT
EC131
EC130
12
11
10
9
8
7
6
5
4
3
2
DY
EC135
DY
14
TP_DATA
TP_CLK
TPAD1
DY
EC134
KCOL4
KCOL3
KCOL2
KCOL1
TP_DATA
TP_CLK
TP_LEFT
TP_RIGHT
DY
1
1
1
1
DY
1
2
TP77
TP61
TP76
TP60
12
T/P
EC132
4
3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
RN52
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
KCOL0
5V_S0
SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
1
SCD1U10V2KX-4GP
EC31
EC30
EC29
EC28
SC220P50V2JN-3GP
1
DY
1
DY
1
DY
1
DY
5V_S0
EC129
KB1
SC100P50V2JN-3GP
1
DY
1
DY
1
DY
1
DY
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
TOUCH PAD
SC100P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
1
1
1
1
KCOL8
KCOL7
KCOL6
KCOL5
1
DY
1
DY
1
DY
1
DY
TP80
TP62
TP75
TP59
KCOL16 EC39
KCOL15 EC38
KCOL14 EC37
KCOL13 EC36
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
1
1
1
1
SCD1U10V2KX-4GP
TP84
TP66
TP82
TP65
28
27
EMI Bypass cap.

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
20.K0204.026
ACES-CON26-GP-U
CP Pull Low
DY
1
13
Internal KeyBoard CONN

25
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
TP79
TP69
TP78
TP68
1
1
1
1
KROW4 EC45
KROW3 EC44
KROW2 EC43
KROW1 EC42
1
........
CHECK KB SPEC. AND PIN DEFINE
1
DY
1
DY
1
DY
1
DY
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
LEFT1
RIGHT1
TP_LEFT
4
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
TP83
TP64
TP81
TP63
1
1
1
1
KCOL12 EC35
KCOL11 EC34
KCOL10 EC33
KCOL9 EC32
1
DY
1
DY
1
DY
1
DY
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
2SC220P50V2JN-3GP
ACES-CON12-4-GP-U
TP_RIGHT
4
20.K0228.012
2nd: 20.K0359.012
5
1
1
1
1
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
TP108
TP104
TP107
TP103
TP106
Wistron Corporation
SW-TACT-122-GP
SW-TACT-122-GP
62.40009.681
62.40009.681
2nd: 62.40009.671
5V_S0
TP_DATA
TP_CLK
TP_RIGHT
TP_LEFT
Title
Size
A2
Date:
KBC ENE3926
Document Number
Rev
SC
Cathedral Peak II
Sheet
30
of
43
3D3V_AUX_S5
ERN1
SPICLK_ROM 1
SPIDO_ROM 2
SPIDI_ROM
3
4
5
6
7
8
RN58
3D3V_AUX_S5
SRN10KJ-6-GP
8
7
6
5
SPICLK 30
SPIDO
30
SPIDI
ER2
0R0603-PAD
SPIDI_ROM
SPI_WP#
CS#
DO
WP#
GND
VCC
HOLD#
CLK
DIO
8
7
6
5
3D3V_AUX_S5_SPI_ROM
SPI_HOLD#
SPICLK_ROM
SPIDO_ROM
SC4D7P50V2CN-1GP
MXIC: 72.25165.A01
WinBond: 72.25X16.001
EC167
16M Bits
SPI FLASH ROM
W25X16VSSIG-GP
72.25X16.001
EC160
SC4D7P50V2CN-1GP
SPI_WP#
1
2
3
4
U50
SPICS#
30
EC159
SC4D7P50V2CN-1GP
4
3
2
1
SRN150F-1-GP
SPI_HOLD#
30
30
EC166
SC4D7P50V2CN-1GP
TOP VIEW
A15
(B1)
A14
(B2)
17,30 LPC_LAD[0..3]
LPC_LAD[0..3]
GOLDEN FINGER FOR DEBUG BOARD
....
....
5V_S0
A2
(B14)
A1
(B15)
5V_S0
U27
7,18,25,27,30 PLT_RST1#
17,30 LPC_LFRAME#
PCLK_FWH
PCLK_FWH
R444 DY
100R2J-2-GP
17
(BOTTOM VIEW)
PLT_RST1#
LPC_LFRAME#
PCLKFWH
C575 DY
SC10P50V2JN-4GP
FWH_INIT#
FWH_INIT#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
EXT_FWH#
3D3V_S0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
PLT_RST1#
LPC_LFRAME#
PCLK_FWH
FWH_INIT#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
EXT_FWH#
TP135 TPAD28
3D3V_S0
FOX-GF30
ZZ.GF030.XXX
ai
l.c
om
PCLK_FWH
EC171
SC5P50V2CN-2GP
DY
tm
Wistron Corporation
f@
ho

Title
xa
in
Size
BIOS/GOLDEN FINGER
Document Number
Rev
SC
he
Cathedral Peak II
Date:
A
Sheet
E
31
of
43
Aux Power
3D3V_AUX_S5
Run Power
5V_AUX_S5
I min = 300 mA
3D3V_AUX_S5
5V_S5
5V_S0
DY U40
R439
330KR2J-L1-GP
DY
R445
100KR2J-1-GP
Z_12V_D4
3D3V_runpwr 2
C572
R438
D26
PDZ9D1B-GP
3D3V_S0
83.9R103.C3F
3D3V_S5
U53
1 S
2 S
3 S
G
4
D
D
D
D
8
7
6
5
AO4468-GP
84.04468.037
Q32
Z_12V_D3
DY
DY
Z_12V_G3
AO4468-GP
R442
1
R430
100R5J-3-GP
8
7
6
5
D
1
R383
0R0402-PAD
2
1
D
D
D
D
84.04468.037
Z_12V
330KR2J-L1-GP
C508
SCD1U10V2KX-4GP
10KR2J-3-GP
3D3V_S0
R435
1
DY
U22
S
S
S
G
SCD1U25V3KX-GP
SCD22U25V3KX-GP
5V_AUX_S5
C522
1
2
3
4
RUN_POWER_ON
10KR2J-3-GP
3D3V_AUX_S5_EN
74.09198.G7F
Q26
NDS0610-NL-GP
DCBATOUT
NC#4
RT9198-33PBR-GP
DY
C273
1
VOUT
C517
VIN
GND
EN/EN#
SC1U16V3ZY-GP
SC1U16V3ZY-GP
Q27
2N7002-11-GP
Z_12V_D3
2N7002DW-1-GP
R103
EMC2102_PWROK 2
DY
84.27002.D3F
1
PWROK
PM_SLP_S3# 18,27,30,36,37,38
0R2J-2-GP
3D3V_S5
SCD1U16V2KX-3GP
C579
1
U14
GND
VCC
DY
PWROK 7,18
74LVC1G08GW-1-GP
1D05V_S0
1D05V_S0
R426
2K2R2J-2-GP
DY
R425
56R2J-4-GP
C561
1
DY
B
R440
1KR2J-1-GP
4,17,41 H_PWRGD
DY
H_PWRGD#
-1
C574
SC2D2U16V3KX-GP
2
D25
BAS16PT-GP
30,35,41 S5_ENABLE
PM_SLP_S3#
18,27,30,36,37,38
21 EMC2102_PWROK
EMC2102_PWROK
2
SCD1U16V2ZY-2GP
KBC_THERMALTRIP# 30
Q25
Q24
MMBT2222A-3-GP
MMBT3904-3-GP
DY
1
2
3
RSMRST# 21,30
Wistron Corporation
Title
Size
RUN POWER and 3D3V_AUX_S5

Document Number
Rev
SC
Cathedral Peak II
Sheet
32
of
43
CPU_CORE
ISL6266A
VID0
D
VID1
VID2
VID3
VID4
VID5
VID6
Output Signal
VID Setting
VID0(I / 3.3V)
PGOOD
DCBATOUT_51125
VGATE_PWRGD
1D5V_S0
Output Power
Input Power
VIN
1D8V_S3
5V_S5 (6A)
5V(O)
Input Signal
S5_ENABLE
VID3(I / 3.3V)
VID4(I / 3.3V)
VCC_CORE_PWR(O)
3D3V(O)
EN0
Output Power
VCC_CORE(Imax=38A) ALW_PWRGD_3V_5V
3D3V_S5 (6A)
PM_SLP_S3#
RT9026
PGOOD
3D3V(O)
3D3V_AUX_S5
5V_S5
VID0
EN (I / 3.3V)
VID0(I / 3.3V)
0D9V_S3_1
VTTREF
S5
VID1(I / 3.3V)
VID2
VID2(I / 3.3V)
VID3
RGND(I / Vcore)
S3
CPUCORE_ON
PGOOD
0D9V_S3 (1A)
VTT
VID1
VSEN(I / Vcore)
VLDOIN
PM_SLP_S4#
Output Signal
VID Setting
0D9V_S0
VIN
1D8V_S3
GFX_CORE
ISL6263A
VID6(I / 3.3V)
CPUCORE_ON
PGOOD
EN
5V_AUX_S5
5V(O)
Output Signal
VID5(I / 3.3V)
Voltage Sense
VSS_SENSE
1D5V_S0 (2.5A)
1D5V(O)
VID2(I / 3.3V)
VCC_SENSE
VIN
VID1(I / 3.3V)
Input Signal
CPUCORE_ON
RT9018A
TPS51125
5V/3D3V
VID3(I / 3.3V)
VID4
VID4(I / 3.3V)
Input Power
DCBATOUT_6266A
5V_S0
3D3V_S0
VDD
DCBATOUT
VCC(I)
VCC(I)
PM_SLP_S3#
DCBATOUT_51124
PM_SLP_S4#
PM_SLP_S3#
A
VCC
Input Signal
VCC_AXG_SENSE
Output Power
VDD
1D8V (O)
1D05V(O)
1D8V_S3 (10A)
VSS_AXG_SENSE
Input Signal
CHG_ON#
Input Signal
VR_ON
24750_CELLS
Output Signal
AC_IN#
ACGOOD#
CHGEN#
AD_IA
SRSET
CELLS
Voltage Sense
Input Power
VSEN(I / Vcore)
RGND(I / Vcore)
AD+
Output Power
ACN
Input Signal
AD_OFF
VOUT (O)
Output Signal
(O)
(I)
BT+
VOUT (O)
Adapter
1D05V_S0 (15A)
EN1
EN2
Charger BQ24745
VCC_GFXCORE(5.5A)
GFXVR_EN
TPS51124
1D8V/1D05V
Input Power
VGFXCORE (O)
VIN
5V_S5
Output Power
Input Power
5V_S0
VCC(I)
DCBATOUT
AD_IN#
Wistron Corporation
Title
AD+
Power Sequence Logic

Size
B
VCC(I)
Date:
5
Document Number
om
VCC(O)
ai
l.c
VCC(I)
Rev
Cathedral Peak II
Sheet
33
of
tm
AD_JK
5V_AUX_S5
ho
PGOOD1
PGOOD2

Output Power
f@
Input Power
xa
in
Output Signal
he
CPUCORE_ON
SC
43
2
1
5
6
7
8
2
1
4
3
2
1
VCC_CORE
1
2
1
2
one phase
2
1
5
6
7
8
G3
GAP-CLOSE
TC4
CAP
G39
GAP-CLOSE
6266A_LGATE2
R64
1
2
0R0402-PAD
6266A_VSUM
C42
SCD01U25V2KX-3GP
6266A_ISEN2
6266A_ISEN1
Single Phase
R47=1.2K, R63=5.6K,R460=0R
C33=47p, C49=0.033u, C52=0.1u
R62
1
R56
1
R45
1
R42
1
one phase
2 3K65R2F-1-GP
6266A_ISEN2_P2_VCORE
2 10KR2F-2-GP
one phase
one phase
1R2F-GP
A
2 10KR2F-2-GP
one phase
Wistron Corporation
Title
ISL6266A_CPU_CORE
DY=U7,U28,U29,L9,R62,R56,R42,
R45,R37,R39,R48,C20
4
TC6
CAP
Size
A3
Document Number
Rev
SC
Cathedral Peak II

5
1
2
1
one phase
2
10R2F-L-GP
C40
SC1U25V0KX-GP
R50
1
one phase
4
3
2
1
BSC057N03MSG-GP
-1
U28
BSC057N03MSG-GP
U7
one phase
5
6
7
8
5V_S0
R260
NTC-10K-9-GP
6266A_VSUM_R_VO
DY
DY
C322
SCD1U50V3KX-GP
1
2
IND-D36UH-9-GP
one phase
5V_S0
C14
L9
6266A_PHASE2
4
3
2
1
1
2
0R2J-2-GP
C319
Cyntec 10*10*4
DCR=1.05+-5%mohm, Irating=30A
Isat=60A
SCD22U10V2KX-1GP
1
1
SCD022U25V3JX-U-GP
2
one phase
DY
6266A_UGATE2
R460
-1
-1
C36
4
3
2
1
26266A_VO
6266A_VO
one phase
BSC057N03MSG-GP
5
6
7
8
-1
5
6
7
8
ISEN1
R69
2K61R2F-1-GP
R63
11KR2F-L-GP
SB
one phase
2008/05/06
20080605
C49
DCBATOUT_6266A
one phase
SCD22U10V2KX-1GP
1
2
C20
SCD22U25V3KX-GP
24
ISEN2
6266A_ISEN2
23
VDD
6266A_VDD
22
VIN
21
6266A_VIN 20
DFB
VO
1
2
2
1
2
2 10KR2F-2-GP
one phase
SE330U2VDM-L-GP
2 1R2F-GP
1 R48
SE330U2VDM-L-GP
1 R46
6266A_ISEN2
SC2D2U16V3KX-GP
S
S
S
G
6266A_VO
D
D
D
D
2 10KR2F-2-GP
S
S
S
G
SCD01U25V2KX-3GP
2 3K65R2F-1-GP
1 R39
C29
6266A_ISEN1
C31
C39
SCD33U10V3KX-3GP
6266A_VO
1 R67
U29
BSC120N03MS-G-GP
one phase
R53
10R3F-GP
C47
6266A_VSUM
6266A_ISEN1
one phase
DCBATOUT_6266A
C43
D
D
D
D
RTN
R47
POWER SB
18
1
6266A_VO
6266A_VSUM 19
6266A_DFB 17
6266A_RTN 15
16
16266A_DROOP
R59
GND
25
VSUM
26
NC#25
DROOP
BOOT2
FB2
SC180P50V2JN-1GP
one phase
4
3
2
1
VID1
VID2
VID0
FB
20080605
one
phase
4
3
2
1
2
6266A_D0
37
2
6266A_D1
38
2
6266A_D2
VID3
VID4
R37
6266A_BOOT2 1
26266A_BOOT2_R
2D2R2J-GP
C52
SCD22U50V3ZY-1GP
5
6
7
8
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
39
2
6266A_D3
40
2
6266A_D4
41
2
6266A_D5
42
2
6266A_D6
43
6266A_UGATE2
2
1
R58
0R0402-PAD
6266A_VSUM
VID5
27
74.06266.073
2
R459
1KR2J-1-GP
VID6
UGATE2
R57
0R0402-PAD
2
1
VSS_SENSE
VR_ON
COMP
C34
SC330P50V2KX-3GP
5
H_VID6
0R0402-PAD
499R2F-2-GP
6266A_PHASE2
C41
SC330P50V2KX-3GP
VCC_SENSE
6266A_VR_ON 2
R17
6266A_DPRSLPVR2
28
DY
R18 1
0R0402-PAD
R19
1
0R0402-PAD
R20
1
0R0402-PAD
R21
1
0R0402-PAD
R22
1
0R0402-PAD
R23
1
0R0402-PAD
R24
1
0R0402-PAD
R25
1
0R0402-PAD
R16
6266A_DPRSTP# 2
45
DPRSTP#
PHASE2
2
1KR2F-3-GP
DPRSLPVR
VW
1KR2F-3-GP
6266A_SOFT
R60
1
47
6266A_LGATE2
29
6266A_VDIFF
B
CLK_EN#
30
PGND2
R52
1KR2F-3-GP
ISL6266AHRZ-GP
C46
2 6266A_FB2_R 1
2
100R2F-L1-GP-U
SC2200P50V2KX-2GP
46
6266A_3V3
LGATE2
OCSET
TC3
CAP
C18
SC10U25V6KX-1GP
2
SC270P50V2KX-1GP
48
49
5V_S0
SOFT
G4
GAP-CLOSE
SC10U25V6KX-1GP
C32
1
6266A_ LGATE1
31
NTC
G40
GAP-CLOSE
SC10U25V6KX-1GP
2 6266A_COMP_R
97K6R2F-GP
11
6266A_FB2 12
32
PVCC
VR_TT#
S
S
S
G
R65
1
2
SC100P50V2JN-3GP
PGND1
LGATE1
RBIAS
TC16
CAP
6266A_ LGATE1
C17
SCD22U25V3KX-GP
D
D
D
D
R54
1
6266A_FB
one phase
2
10K5R2F-GP
6266A_PHASE1
1K74R2F-GP
1
2
1
R44
34
33
VDIFF
6266A_COMP
10
POWER SA
C33
1
35
PHASE1
6266A_VDIFF
13
6266A_NTC
6
1 R259
26266A_NTC_R1 R35
2
NTC-470K-1-GP
4K02R2F-GP
C26
6266A_SOFT
C21
7
1
2
SCD015U50V3KX-GP
1
2
6266A_VO 1
SCD01U25V2KX-3GP
8
26266A_OCSET
R38
12KR3F-GP
6266A_VW 9
C28 1
2 SC1000P50V3JN-GP
3V3
GND
2
1
2
4 CPU_PROCHOT#_R
UGATE1
PMON
36
TC2
CAP
SE330U2VDM-L-GP
PSI#
BOOT1
VCC_CORE
SE330U2VDM-L-GP
C331
SCD1U50V3KX-GP
Vcc_core
Iomax=38A
SE330U2VDM-L-GP
2
16266A_PSI# 2
R28
0R0402-PAD
6266A_PMON_R 1
3
2 6266A_PMON
R30
4K99R2F-L-GP
1
26266A_RBIAS4
R32
147KR2F-GP
5
PSI#
C16
1
POWER SB
U31
S
S
S
G
SCD1U25V3KX-GP
DY
D
D
D
D
R33
68R2-GP
U11
BSC057N03MSG-GP
Id=19.5A
Qg=21.5~33nC,
Rdson=5.5~6.7mohm
R29
6266A_BOOT1 1
2
6266A_BOOT1_R
2D2R2J-GP
1
6266A_UGATE1
PGOOD
DY
C38
L8
1
2
IND-D36UH-9-GP
6266A_PHASE1
S
S
S
G
7,18,21 VGATE_PWRGD
C37
Cyntec 10*10*4
DCR=1.05+-5%mohm, Irating=30A
Isat=60A
6266A_UGATE1
U5
R27
1K91R2F-1-GP
DY
D
D
D
D
3D3V_S0
5
U30
BSC120N03MS-G-GP
44
1
2
R456
R456
2
SCD1U10V2KX-4GP
DY
GAP-CLOSE-PWR
-1
1D05V_S0
1 0R2J-2-GP
1
C13
GAP-CLOSE-PWR
VSEN
2
1
2
GAP-CLOSE-PWR
G29
1
2
H_VID[6..0]
-1
-1
C15
SC10U25V6KX-1GP
TC1
SE100U25VM-L1-GP
-1
SC10U25V6KX-1GP
R26
10R3F-GP
GAP-CLOSE-PWR
G36
1
2
GAP-CLOSE-PWR
G30
1
2
2008/05/06
36,37,38
S
S
S
G
GAP-CLOSE-PWR
G31
1
2
CPUCORE_ON
D
D
D
D
TC13
ST15U25VDM-1-GP
DY
3D3V_S0
GAP-CLOSE-PWR
G37
1
2
SC10U25V6KX-1GP
DCBATOUT_6266A
SB
G32
PM_DPRSLPVR 7,18
6266A_VSEN14
G35
GAP-CLOSE-PWR
G38
1
2
4,7,17 H_DPRSTP#
DCBATOUT_6266A
DCBATOUT
DCBATOUT_6266A
DCBATOUT
Sheet
1
34
of
43
POWER SA
DCBATOUT
DCBATOUT_51125
G79
2
3D3V_PWR
3D3V_S5
G98
5V_PWR
5V_AUX_S5
5V_S5
G12
GAP-CLOSE-PWR
G25
1
2
GAP-CLOSE-PWR
G97
1
2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
3
4
51125_ENTIP2
2N7002DW-1-GP
R361
110KR3F-GP
GAP-CLOSE-PWR
G15
1
2
DY
GAP-CLOSE-PWR
G18
1
2
GAP-CLOSE-PWR
G17
1
2
TC27
ST15U25VDM-1-GP
GAP-CLOSE-PWR
DCBATOUT_51125
51125_FB1
PGOOD
23
51125_PGOOD
ENTRIP1
51125_ENTIP1
GND
SKIPSEL
VCLK
18
1
DY
0R2J-2-GP
51125_VREF
1
DY
0R2J-2-GP
3D3V_AUX_S5
C506
SC10U10V5KX-2GP
5
6
7
8
D
D
D
D
G
S
S
S
D
D
D
D
VREG5
DY
3D3V_S5
R370
30KR2F-GP
51125_FB1_R
DY
2
R377
100KR2J-1-GP
GAP-CLOSE-PWR-3-GP
R363
20KR2F-L-GP
DY
Close to VFB Pin (pin2)
C512
SC10U10V5KX-2GP
R389
tm
Wistron Corporation
1
0R2J-2-GP

ho
Close to VFB Pin (pin5)
Title
1
0R2J-2-GP
Document Number
Rev
SC
Cathedral Peak II

5
xa
in
DCDC 5V/3D3V (TPS51125)

Size
A3
he
DY
f@
R391
1 2
C500
SC18P50V2JN-1-GP
5V_AUX_S5
G78
TC11
ai
l.c
R390
R373
0R2J-2-GP
TPAD28
C481
om
3D3V_AUX_S5
Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm
51125_VCLK
17
VREG3
GAP-CLOSE-PWR-3-GP
R362
3D3V_AUX_S5_5_51125 8
R365
0R0402-PAD
2
1
15V_AUX_S5_51125
G77
DY
74.51125.073
2
1
TONSEL
14
TPS51125RGER-GP
3D3V_AUX_S5
15
25
51125_SKIPSEL
51125_VREF
GND
51125_FB2_R
C501
DYSC18P50V2JN-1-GP
51125_TONSEL
VREF
1 2
Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm
C497
ENTRIP2
EN0
G74
VFB1
VFB2
51125_FB2
IND-3D3UH-57GP
D
1
51125_VO1
24
VO1
2 51125_EN 13
820KR2F-GP
51125_ENTIP2 6
1
2
51125_DRVL1
VO2
1
2
3
4
1
2
19
ST220U6D3VDM-15GP
DRVL1
51125_VO2
SCD1U10V2KX-4GP
R374
0R2J-2-GP
51125_VREF
5V_PWR
DRVL2
Iomax=5A
L3
5
6
7
8
12
Cyntec 7*7*3
DCR=30mohm, Irating=6A
Isat=13.5A
G
S
S
S
51125_DRVL2
4
3
2
1
LL2
DY
GAP-CLOSE-PWR-3-GP
51125_LL1
DRVH2
11
SI4812BDY-T1-E3-GP
51125_DRVH1
20
10
51125_LL2
8
7
6
5
21
LL1
51125_DRVH2
1
R384
SCD22U6D3V2KX-1GP
R366
10KR2F-2-GP
DRVH1
VBST1
U25
G
S
S
S
SI4812BDY-T1-E3-GP
DY
R371
6K65R2F-GP
51125_VBST1
VBST2
D
D
D
D
GAP-CLOSE-PWR-3-GP
G75
22
DY
4
3
2
1
1
2
51125_VBST2
D
U49
16
VIN
C293
1
SCD1U25V3KX-GP
L20
ST220U6D3VDM-20GP
SCD1U10V2KX-4GP
1
2
8
7
6
5
1
2
1
2
3
4
U24
SI4800BDY-T1
C507
SCD1U25V3KX-GP
G
S
S
S
1
2
IND-3D3UH-57GP
TC12
U37
C532
SCD01U50V2KX-1GP
Id=7A
Qg=8.7~13nC
Rdson=23~30mohm
Id=7A
Qg=8.7~13nC
Rdson=23~30mohm
C292
SC10U25V6KX-1GP
U48
SI4800BDY-T1
C294
SC10U25V6KX-1GP
3D3V_PWR
DY
C521
DY
DY
D
D
D
D
Iomax=5A
C570
C518
SCD01U50V2KX-1GP
C523
SC10U25V6KX-1GP
DY
SC10U25V6KX-1GP
SCD01U50V2KX-1GP
Cyntec 7*7*3
Isat=13.5A
C526
DCBATOUT_51125
-1
-1
SC10U25V6KX-1GP
C290
DCBATOUT_51125
C291
R221
100KR3F-GP
C495
GAP-CLOSE-PWR
G13
1
2
51125_ENTIP1
2N7002DW-1-GP
DY
GAP-CLOSE-PWR
G16
1
2
S5_ENABLE 30,32,41
GAP-CLOSE-PWR
G95
1
2
51125_ENTIP1
GAP-CLOSE-PWR
G26
1
2
2
1
GAP-CLOSE-PWR
G91
1
2
GAP-CLOSE-PWR
G81
1
2
30,32,41 S5_ENABLE
GAP-CLOSE-PWR
G101
1
2
GAP-CLOSE-PWR
G14
1
2
Q21
RN60
SRN100KJ-6-GP
GAP-CLOSE-PWR
G83
1
2
Q20
51125_ENTIP2
SC18P50V2JN-1-GP
GAP-CLOSE-PWR
G93
1
2
SC18P50V2JN-1-GP
DY
GAP-CLOSE-PWR
G28
1
2
TC25
SE68U25VM-3-GP
-1
GAP-CLOSE-PWR
G99
1
2
GAP-CLOSE-PWR
G27
1
2
Sheet
1
35
of
43
1D5V_S0
Iomax=2.5A
D
1D8V_S3
5V_S5
G7
DY
C131
SC1U16V3ZY-GP
C127
SC10U10V5ZY-1GP
1
C126
SC10U10V5ZY-1GP
GAP-CLOSE-PWR
G9
2
GAP-CLOSE-PWR
G8
2
GAP-CLOSE-PWR
G6
2
Vo(cal.)=1.5024V
1D5V_LDO
R117
2
15912_EN_U111
0R0402-PAD
U17
RT9018A-25PSP-GP
R119
2K2R2J-2-GP
R131
20K5R2F-GP
R120
2
1
0R0402-PAD
34,37,38 CPUCORE_ON
1
C155
74.09018.A3D
DY
5912_FB_U111
C156
C154
R132
18KR2J-GP
NC#5
VOUT
ADJ
GND
1D5V_S0
GAP-CLOSE-PWR
SC10U10V5ZY-1GP
VDD
VIN
EN
PGOOD
SC10U10V5ZY-1GP
3D3V_S0
5
6
7
8
SC100P50V2JN-3GP
4
3
2
1
PM_SLP_S3#
PM_SLP_S3#
GND
18,27,30,32,37,38
5912_POK_U111
Vo=0.8*(1+(R1/R2))
G19
74.09026.079
11
RT9026PFP-GP
C285
SC10U10V5ZY-1GP
GAP-CLOSE-PWR
C284
SC1U10V2ZY-GP
GAP-CLOSE-PWR
G21
1
2
1
2
3
4
5
VIN
VDDQSNS
S5
VLDOIN
GND
VTT
S3
PGND
VTTREF VTTSNS
GND
9026_S3
10
9
8
7
6
9026_S5
DDR_VREF_S3_1
R220
2
1
0R0402-PAD
R218
2
1
0R0402-PAD
GAP-CLOSE-PWR
G20
1
2
U23
18,27,30,37 PM_SLP_S4#
DDR_VREF_S3
DDR_VREF_PWR
C288
SCD1U10V2KX-4GP
C289
SC10U10V5ZY-1GP
C287
SC1U10V3ZY-6GP
1D8V_S3
5V_S5
Iomax=1A
OCP>2A
C286
SC10U10V5ZY-1GP
Wistron Corporation
Title
Size
A3
Document Number

5
1D5V & 0D9V
Rev
SC
Cathedral Peak II
Sheet
1
36
of
43
1D8V_PWR
Vtrip(mV)=Rtrip(Kohm)*10(uA)
Iocp=(Vtrip/Rdson)+((1/(2*L*f))*((Vin-Vout)*Vout)/Vin))
GAP-CLOSE-PWR
G57
1
2
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

-1
1
DCBATOUT_51124
TC30
SE68U25VM-3-GP
2
C553
SC10U25V6KX-1GP
D
D
D
D
DY
U45
SI4800BDY-T1
2
2
1
G
S
S
S
4
3
2
1
24
7
2
5
1
6
Id=7A
Qg=8.7~13nC
Rdson=23~30mohm
2
2
D
D
D
D
DY
51124_VFB2
OPEN
V5FILT
300k/CH1
360k/CH2
360k/CH1
420k/CH2
C303
DY
C503
GAP-CLOSE-PWR
G65
1
2
TC21
GAP-CLOSE-PWR
G63
1
2
GAP-CLOSE-PWR
G46
1
2
GAP-CLOSE-PWR
G60
1
2
GAP-CLOSE-PWR
G61
1
2
GAP-CLOSE-PWR
G72
1
2
GAP-CLOSE-PWR
om
GND
240k/CH1
300k/CH2
GAP-CLOSE-PWR
G67
1
2
1D05V Iomax=10.5A
OCP>20A
51124_V5FILT
R236
30KR2F-GP
G
S
S
S
Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm
U46
SI4812BDY-T1-E3-GP
SCD1U16V2KX-3GP
TONSEL
R237
10K7R2F-GP
5
6
7
8
2
R238
0R2J-2-GP
51124_VBST2
DY
4
3
2
1
10KR2J-3-GP
51124_LL2
DY R234
GAP-CLOSE-PWR
G69
1
2
1D05V_PWR
L19
1
2
IND-D56UH-12-GP
GAP-CLOSE-PWR
G70
1
2
ST330U2D5VDM-9GP
51124_VBST1
SCD1U16V2KX-3GP
C567
1
1
1
Cyntec 10*10*4
DCR=4.2mohm, Irating=16A
Isat=33A
SCD1U10V2KX-4GP
C571
1
2
1
5
6
7
8
D
D
D
D
SC10U25V6KX-1GPDY
C556
SC10U25V6KX-1GP
DY
U47
SI4800BDY-T1
1D05V_S0
G71
1
C550
1
2
R424
20KR3F-GP
GAP-CLOSE-PWR
G59
1
2
1D05V_PWR
C563
SC18P50V2JN-1-GP
51124_LL1
GAP-CLOSE-PWR
G48
1
2
GAP-CLOSE-PWR
TPS51124RGER-GPU1
74.51124.073
51124_TRIP1
51124_TRIP2
R420
17K8R3F-1-GP
Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm
-1
51124_TONSEL
GAP-CLOSE-PWR
G51
1
2
DY
BC1
SCD47U6D3V2KX-GP
51124_DRVH2
51124_LL2
51124_DRVL2
GAP-CLOSE-PWR
G53
1
2
1D8V Iomax=10A
OCP>15A
DRVH2
LL2
DRVL2
10
11
12
DY
GAP-CLOSE-PWR
G50
1
2
TC22
DCBATOUT_51124
17
14
R441
2
1
0R0402-PAD
51124_DRVH1
51124_LL1
51124_DRVL1
G
S
S
S
GND
GND
PGND2
PGND1
R235
21K5R3F-GP
4
3
2
1
EN1
EN2
3
25
13
18
PGOOD1
PGOOD2
23
8
21
20
19
TONSEL
51124_EN1
51124_EN2
DRVH1
LL1
DRVL1
V5FILT
V5IN
VO1
VO2
VFB1
VFB2
15
16
C582
SC1000P50V3JN-GP
GAP-CLOSE-PWR
G54
1
2
SCD1U50V3KX-GP
PM_SLP_S3#
51124_V5FILT
VBST1
VBST2
18,27,30,32,36,38
SC1U10V3KX-3GPU54
TRIP1
TRIP2
BC2
SCD47U6D3V2KX-GP
R447
0R0402-PAD
22
9
DY1
C559
R443
2
1
0R0402-PAD
51124_VFB1
U44
SI4812BDY-T1-E3-GP
C504
DY
D
D
D
D
51124RGER_PG1
51124RGER_PG2
1
1
18,27,30,36 PM_SLP_S4#
1D05V_PWR
1D8V_PWR
51124_VFB2
51124_VFB1
1
2
C557
SC4D7U10V5KX-1GP
GAP-CLOSE-PWR
G56
1
2
SE330U2D5VDM-LGP
R230
3D3R3J-L-GP
C304
SCD1U10V2KX-4GP
R239
30KR2F-GP
1
2
IND-1D5UH-34-GP
DY
C581
SC1000P50V3JN-GP
SC18P50V2JN-1-GP
5V_S5
GAP-CLOSE-PWR
G55
1
2
1D8V_PWR
L18
34,36,38
CPUCORE_ON
Cyntec 10*10*4
DCR=4.2mohm, Irating=16A
Isat=33A
R446
0R0402-PAD
2
1
GAP-CLOSE-PWR
Id=7A
Qg=8.7~13nC
Rdson=23~30mohm
G
S
S
S
2008/06/16
4
3
2
1
-1
5
6
7
8
GAP-CLOSE-PWR
G96
1
2
DY
5
6
7
8
C560
SC10U25V6KX-1GP
C549
SCD1U50V3KX-GP
GAP-CLOSE-PWR
G92
1
2
GAP-CLOSE-PWR
G58
1
2
-1
GAP-CLOSE-PWR
G88
1
2
GAP-CLOSE-PWR
G89
1
2
TC26
ST15U25VDM-3-GP
DY
GAP-CLOSE-PWR
G90
1
2
GAP-CLOSE-PWR
G49
1
2
1D8V_S3
G52
DCBATOUT_51124
G94
DCBATOUT
ai
l.c
Wistron Corporation
tm
Vout=0.758V*(R1+R2)/R2 --> PWM mode

Vout=0.764V*(R1+R2)/R2 --> Skip Mode
ho

f@
Title
Document Number
Rev
SC
Cathedral Peak II
he
Date:
xa
in
TPS51124_1D8V_1D05V
Size
A3
Sheet
1
37
of
43
POWER_MONITOR
1
GFX
G64
1
PL on P.7
R415
6236A_VID4
R413
6236A_VID3
R411
6236A_VID2
R408
6236A_VID1
R404
6236A_VID0
R421
1
18,27,30,32,36,37 PM_SLP_S3#
2
0R2J-2-GP
DY
R224
1
DY
0R3-0-U-GP
2
2
0R2J-2-GP
2
2
2
2
1D05V_S0
G66
1
GAP-CLOSE-PWR
G87
1
2
0R3-0-U-GP
2
NO GFX
GAP-CLOSE-PWR
G85
1
2
2
10KR2F-2-GP
GFX
6236A_PMON
G
S
S
S
4
3
2
1
2
1
1
D
D
D
D
5
6
7
8
GFX CORE
Iomax=8.7A
OCP>15A
GAP-CLOSE-PWR
G42
1
2
VGFXCORE
GAP-CLOSE-PWR
Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm
GFX
G76
GAP-CLOSE-PWR
2
G73
GAP-CLOSE-PWR
2
U41
SI4812BDY-T1-E3-GP
GFX
G
S
S
S
2
GFX 10R2F-L-GP
GAP-CLOSE-PWR
G41
1
2
5
6
7
8
C540
SCD22U16V3KX-2-GP
4
3
2
1
R405
1
GAP-CLOSE-PWR
G43
1
2
POWER SB
6236A_VDD
GAP-CLOSE-PWR
G44
1
2
Cyntec 7*7*3
Isat=24A
D
D
D
D
VDD
VSS
16
15
VSUM
VIN
14
6236A_VIN
5V_S0
GFX
GFX
2
10R2F-L-GP
DCBATOUT
B
R229
1
C298
SCD01U25V2KX-3GP
2
0R0402-PAD
GFX
R223
1
GFX
1
2
GFX
GAP-CLOSE-PWR
G45
1
2
GFX
GFX
1
GFX
1
2
G102 GAP-CLOSE-PWR
1
2
C562
Id=7A
Qg=8.7~13nC
Rdson=23~30mohm
G47
1
C525
SCD1U50V3KX-GP
L17
ISL6263ACRZ-T-GP
SC1U16V3KX-2GP
R422
GFX
2K55R2F-GP
C299
GFX
GFX
C536
1
2
COIL-D82UH-2-GP
74.06263.073
C547
1
2
SC330P50V2KX-3GP
9 VCC_AXG_SENSE
BOOT
6236A_BOOT
1
2
R401
3D3R3J-L-GP
2
SC1KP50V2JN-2GP
GFX
25
6236A_UGATE
C564
SC1KP50V2JN-2GP
VID2
18
17
6236A_RTN
GFX
26
6236A_AF_EN
UGATE
R26 for Intel GPU/With Load line

R27 for ATI GPU/Without Load
line
C300
SC1KP50V2JN-2GP
VID3
VID4
27
28
PMON
VR_ON
6236A_GOOD
31
29
32
30
33
PHASE
VDIFF
VSEN
5V_S0
SC2D2U10V3KX-1GP
FB
GFX
6236A_LGATE
6236A_PHASE
SC560P50V2KX-2GP
4K99R2F-L-GP
C541
19
6236A_VSEN
1
6236A_FB_R
22
21
C568
2
GFX
1
GFX R436
23
20
6236A_VDIFF
2
2K21R3F-L-GP
VID0
PVCC
VCC_GFXCORE
DCBATOUT_6263A
U42
SI4800BDY-T1
6236A_BOOT_R
R432
1
24
PGND
RTN
VID1
LGATE
COMP
13
6236A_FB
SC180P50V2JN-1GP
GFX
VW
6236A_VSUM
2GFX
VO
12
6236A_COMP 5
1 R437
6263A_VCC_PRM
6236A_VW 4
2
SC1KP50V2JN-2GP
GFX 6K98R3F-GP
FDE
OCSET
DFB
GFX
GND_T
SOFT
PGOOD
DROOP
GFX
C302
6236A_COMP_R
1
GFX
6236A_SOFT
11
C569 1
6236A_OCSET
SC68P-GP
374KR3-GP
RBIAS
GFX SCD01U50V2KX-1GP
C566 1
6236A_DROOP 10
C301
1
R231
1
6236A_RBIAS
6236A_DFB
R227
GFX
9K1R3F-1-GP
1
2
6263A_VCC_PRM
R434 GFX
150KR2F-L-GP
1
2
VGFXCORE
DY
C530
SC10U25V6KX-1GP
SB
GFX
R403
0R0402-PAD
2
1
SC10U25V6KX-1GP
U51
AF_EN
2
0R2J-2-GP
6236A_VR_ON
GFX
R433
1 DY
34,36,37 CPUCORE_ON
GAP-CLOSE-PWR
R431
1
2
1K91R2F-1-GP
3D3V_S0
-1
GFX
TC24
SE68U25VM-3-GP
GAP-CLOSE-PWR
G84
1
2
R225
1
3D3V_S0
GAP-CLOSE-PWR
G80
1
2
VCC_GFXCORE
0R3-0-U-GP
2
NO GFX
G68
1
GAP-CLOSE-PWR
G82
1
2
0R3-0-U-GP
2
NO GFX
0R0402-PAD
GFX_VID4
1
0R0402-PAD
GFX_VID3
1
0R0402-PAD
GFX_VID2
1
0R0402-PAD
GFX_VID1
1
0R0402-PAD
GFX_VID0
1
DCBATOUT
G86
NO GFX
GFXVR_EN
DCBATOUT_6263A
G62
1
GFX_VID[4..0] 7
R417
10KR2J-3-GP
R427
2
1
0R0402-PAD
GFX
C555
1
SCD01U50V2KX-1GP
TC20
SE330U2VDM-L-GP
GFX
R419
1KR3F-GP
C552
1
GFX
Panasonic
ERT-J1VR103J
R378
1
NTC-10K-9-GP
6236A_VSUM_R
7K68R2F-GP
1
SCD033U25V3KX-GP
GFX
G22
GAP-OPEN-PWR
2
G23
GAP-OPEN-PWR
2
4K53R2F-1-GP
R407
1
GFX
R414
1
DY
SCD033U25V3KX-GP
2
GFX
R226
10R3F-GP
DY
R412
1
GFX
GFX
1
R228
10R3F-GP
2
C558
SCD1U25V3KX-GP
C551
1
G100 GAP-CLOSE-PWR
1
2
9 VSS_AXG_SENSE
GFX
2
3K57R2F-GP
GFX
VSS_AXG_SENSE_OUTCAP
VCC_AXG_SENSE_OUTCAP
Cathedral Peak II
Wistron Corporation
Title
ISL6263A_GFX CORE
Size
C
Document Number
Rev
SC
Cathedral Peak II

5
Sheet
1
38
of
43
DCBATOUT
-1
EC108
SCD1U50V3KX-GP
U3
NEAR
AD+
1
2
3
4
DCBATOUT
R12
100KR2J-1-GP
AD+
AD+_G_2
1
2
R43
470KR2J-2-GP
GAP-CLOSE-PWR
27
26
BQ24745_CSSN
TP137
BOOT
VDDP
25
21
BQ24745_BST
BQ24745_VDDP
C48
1
CH520S-30PT-GP SC1U10V3KX-3GP
SI4800BDY-T1
4
3
2
1
1
SCD1U50V3KX-GP
NC#16
16
BQ24745RHDR-GP
VFB
15
BATT_SENSE
BATT_SENSE 40
1
2
C318
C325
C324
C22
C24
MAX8731A_CSIP
MAX8731A_CSIN
C82
SC1U10V3KX-3GP
FBO
EAI
EAO
VREF
CE
GND
GND
6
5
4
3
7
12
G33
om
G
S
S
S
C50
29
74.24745.073
C51
SCD1U25V2ZY-1GP
1
2
C78
SC56P50V2JN-2GP
17
VICM
2BQ24745_FBO
4K7R2J-2-GP
BQ24745_EAI
BQ24745_EAO
BQ24745_VREF
BQ24745_CHG_ON
C84
R86
SC2200P50V2KX-2GP
7K5R2F-1-GP
2
1BQ24745_EAO_RC2
1
C65
SC220P50V2KX-3GP
BQ24745_FBO_RC
R87
1
2
200KR2F-L-GP
CSON
G34
SCD1U50V3KX-GP
18
SC10U25V6KX-1GP
R82
1
19
CSOP
SC10U25V6KX-1GP
CHG_AGND
BQ24745_IINP
SC150P50V2JN-3GP
C85
PGND
SC10U25V6KX-1GP
R76
1
2
0R0402-PAD
NC#14
GAP-CLOSE-PWR
AD_IA
D01R2512F-4-GP
IND-5D6UH-32-GP
U10
D
D
D
D
24745_LOW_G
20
R256
1
BT+_R
LGATE
L5
PHASE
SDA
BT+
24745_HIGH_G
1
2
C62
SCD1U50V3KX-GP
BQ24745_LX1
24
23
UGATE
SCL
GAP-CLOSE-PWR
30
-1
SI4800BDY-T1
SC10U25V6KX-1GP
14
DY
ACOK
CHG_AGND
CHG_AGND
DY
C58
SCD1U25V2ZY-1GP
30,40 BAT_SDA
D8
DY
C349
10
CSSN
ICOUT
C61
C63
SC1U10V3KX-3GP
30,40 BAT_SCL
VDDSMB
1
2
R75
1
2BQ24745_ACOK 13
0R0402-PAD
U9
C350
ACIN
CHG_AGND
28
CSSP
5
6
7
8
BQ24745_ACIN
SCD1U25V3KX-GP
D
D
D
D
DCIN
11
AC_OK
DCBATOUT
4
3
2
1
22
2
BQ24745_DCIN
C66
SCD1U50V3KX-GP
SC10U25V6KX-1GP
U12
SC10U25V6KX-1GP
CHG_AGND
3D3V_AUX_S5
C81
SCD01U50V2KX-1GP
1 BQ24745_CSSP
SCD1U50V3KX-GP
SC10U25V6KX-1GP
AC_OK
C
C79
2
R267
309KR3F-GP
C580
ICREF
POWER SB
C54
SC1U25V5KX-1GP
G2
AD+
GAP-CLOSE-PWR
G1
C320
SCD1U25V2ZY-1GP
D6
1SS4000GPT-GP
Q3
2N7002DW-1-GP
P2003EVG-GP
AD+
20080605
DC_IN_D
R84
49K9R2F-L-GP
D 8
D 7
D 6
D 5
SB
R11
49K9R2F-L-GP
AD+_G_1
1 S
2 S
3 S
4 G
D01R2512F-4-GP
P2003EVG-GP
R10
10KR2F-2-GP
BT+
U6
R13
1
AD+_TO_SYS
G
S
S
S
S
S
S
G
5
6
7
8
D
D
D
D
8
7
6
5
R83
1
2
0R0402-PAD
CHG_AGND
CHG_AGND
CHG_AGND
BQ24745_VREF
RN61
AC_OK
CHG_ON#
AC_IN#
BQ24745_CHG_ON
Q16
AC_OK
Cathedral Peak II
CHG_ON#
CHG_ON#
AC_IN#
DY
C355
SCD1U10V2KX-4GP
C348
SC1U10V3KX-3GP
30
30
Wistron Corporation
AC_IN# to KBC
Title
2N7002DW-1-GP
AC_IN#
ai
l.c
SRN100KJ-8-GP-U
BQ24745_CHG_ON
tm
ho
8
7
6
5
f@
3D3V_AUX_S5
1
2
3
4
Document Number
Rev
SC
Cathedral Peak II
he
Date:
5
xa
in
BQ24745 Charger
Size
A3
Sheet
1
39
of
43
AD_JK_IN
DC1
Adaptor in to generate DCBATOUT
AD+
Q2
R2
E
C
R15
100KR2J-1-GP
Q1
30
TP6
TP5
R1
E
R2
PDTC124EU-1-GP
AD_OFF
AFTE14P-GP
AFTE14P-GP
C8
SC1U50V5ZY-1-GP
PDTA124EU-1-GP
1
1
8
7
6
5
R1
AD_OFF#_JK
D
D
D
D
P2003EVG-GP
R14
200KR2F-L-GP
U2
S
S
S
G
K
P6SBMJ24APT-GP
2nd: 20.F1170.005
AD_JK_IN
AD_JK_IN
1
2
3
4
AD+_2
-1
D1
20.F1002.005
C1
SCD1U50V3ZY-GP
6
ACES-CON5-7-GP-U1
2
1
AD_JK
D30
S10P40PT-GP-U
3
EC6
SCD1U50V3KX-GP
5
4
3
2
4
BATTERY CONNECTOR
BATA_SDA_1
BATA_SCL_1
BAT_IN#_1
BT+
BT+
D3
BAV99PT-GP-U
D4
BAV99PT-GP-U
DY
DY
3D3V_AUX_S5
D5
BAV99PT-GP-U
1
1
1
1
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
TP11
TP10
TP9
TP8
TP7
BAT1
DY
9
8
7
6
5
4
3
2
1
RN42
1
2
3
4
30,39 BAT_SDA
30,39 BAT_SCL
BATA_SDA_1
BATA_SCL_1
BAT_IN#_1
EC102
-1
DY
EC98
DY
1
2
1
2
K
A
SB
EC101
SC10P50V2JN-4GP
DY
1
DY
SC1000P50V3JN-GP
EC103
SCD1U50V3ZY-GP
SC1000P50V3JN-GP
EC104
SCD1U50V3ZY-GP
D29
MMPZ5232BPT-GP
SC10P50V2JN-4GP
EC99
-1
BAT_IN#
SRN33J-7-GP
BT+
30
8
7
6
5
GND
GND
GND
GND
DAT
CLK
BAT_IN
BT+2
BT+1
ALP-CON7-9-GP
20.81094.007
Wistron Corporation
39 BATT_SENSE
R257
1
2
0R0402-PAD
Title
AD/BATT CONN
Size
Document Number
Rev
SC
Cathedral Peak II
A
Sheet
40
of
E
43
11
U32D
U32C
H22
HOLE
12
1
8
13
14
H2
H3
H4
H5
H6
H7
H8
H10
H11
H12
H13
H14
H15
PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP
5V_S0
10
14
5V_S0
TSAHCT125PW-GP
TSAHCT125PW-GP
-1
D
EC100
EC111
DY
EC116
DY
DY
EC91
1
2
1
2
1
2
1
2
1
2
EC176
DY
EC174
DY
DY
EC173
1
2
1
2
1
2
2
1
2
1
2
1
2
2
1
2
2
EC95
DY
DY
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
DY
EC179
SCD1U25V2ZY-1GP
EC88
DY
EC97
SCD1U25V2ZY-1GP
DY
SCD1U25V2ZY-1GP
EC138
SCD1U25V2ZY-1GP
DY
SCD1U25V2ZY-1GP
BOTTOM
GND12
SPRING-7
GND14
SPRING-12-GP-U
34.49U26.001
34.49U26.001
34.41Y19.001
DY
DY
DY
DY
DY
DY
DY
GND11
SPRING-7
34.39S07.001
GND10
SPRING-23-GP
34.41Y19.001
GND8
SPRING-12-GP-U
34.49U26.001
GND7
SPRING-7
34.43G01.002
GND4
SPRING-48-GP
34.41Y19.001
GND3
SPRING-12-GP-U
34.4B542.001
GND2
SPRING-36-GP
EC156
DY
SCD1U25V2ZY-1GP
EC70
SCD1U25V2ZY-1GP
DY
EC117
DY
-1
EC105
SCD1U25V2ZY-1GP
DY
EC125
SCD1U25V2ZY-1GP
DY
EC67
SCD1U25V2ZY-1GP
DY
SCD1U25V2ZY-1GP
DY
EC139
EC165
EC112
DY
-1
SCD1U25V2ZY-1GP
EC83
SCD1U25V2ZY-1GP
DY
EC81
SCD1U25V2ZY-1GP
DY
SCD1U25V2ZY-1GP
DY
EC85
DY
SCD1U25V2ZY-1GP
EC82
SCD1U25V2ZY-1GP
DY
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
DY
EC72
EC136
DY
SCD1U25V2ZY-1GP
DY
SCD1U25V2ZY-1GP
EC66
EC147
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
EC62
DY
EC71
SCD1U25V2ZY-1GP
EC77
SCD1U25V2ZY-1GP
DY
DY
SCD1U25V2ZY-1GP
EC65
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
DY
EC69
DY
SCD1U25V2ZY-1GP
EC118
DY
EC53
SCD1U25V2ZY-1GP
EC73
SCD1U25V2ZY-1GP
DY
DY
SCD1U25V2ZY-1GP
EC61
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
DY
EC50
DY
-1
BT+
EC49
SCD1U25V2ZY-1GP
EC20
3D3V_LAN_S5
SCD1U25V2ZY-1GP
DY
SCD1U25V2ZY-1GP
EC74
DY
TOP
EC119
SCD1U25V2ZY-1GP
EC163
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
DY
TC34
SCD1U25V2ZY-1GP
EC68
DY
TC33
SCD1U25V2ZY-1GP
EC151
SCD1U25V2ZY-1GP
EC126
DY
1D8V_S3
5V_S5
DY
EC54
DY
SCD1U25V2ZY-1GP
5V_S0
DY
EC148
DY
SCD1U25V2ZY-1GP
EC158
TC32
1D2V_LAN_S5
SCD1U25V2ZY-1GP
DY
SCD1U25V2ZY-1GP
EC169
SCD1U25V2ZY-1GP
DY
TC31
-1
SCD1U25V2ZY-1GP
EC168
DY
SCD1U25V2ZY-1GP
EC170
SCD1U25V2ZY-1GP
DY
SCD1U25V2ZY-1GP
EC172
SCD1U25V2ZY-1GP
DY
EC155
DY
SCD1U25V2ZY-1GP
EC150
SCD1U25V2ZY-1GP
DY
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
EC18
DY
EC9
DY
1D05V_S0
3D3V_S0
EC133
GFX
1
2
-1
EC192
SE100U25VM-L1-GP
DY
SE100U25VM-L1-GP
EC191
SE100U25VM-L1-GP
DY
SE100U25VM-L1-GP
EC190
DCBATOUT
SCD1U25V2ZY-1GP
DY
SCD1U25V2ZY-1GP
EC7
DY
SCD1U25V2ZY-1GP
EC10
SCD1U25V2ZY-1GP
DY
SCD1U25V2ZY-1GP
EC94
SCD1U25V2ZY-1GP
DY
EC63
DY
SCD1U25V2ZY-1GP
EC75
SCD1U25V2ZY-1GP
DY
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
EC76
DY
EC89
-1
VCC_GFXCORE
DCBATOUT
DY
Check test point

-1
34.4G502.021
34.4G502.021
34.42Y01.031
34.42Y01.031
34.42Y01.031
34.42Y01.031
34.42Y01.031
NB
MDC
AFTE14P-GP
TP179
AFTE14P-GP
TP180
3D3V_S5
AFTE14P-GP
TP181
5V_S5
AFTE14P-GP
TP182
AFTE14P-GP
TP183
AFTE14P-GP
TP184
AFTE14P-GP
TP185
AFTE14P-GP
TP186 Title
18,30 PM_PWRBTN#
4,17,32
H_PWRGD
30,32,35 S5_ENABLE
4,6
CPU
3D3V_S0
3D3V_AUX_S5
MINIC1
H_CPURST#
Test PointDimm Door
om
SB
H17
HOLE
ai
l.c
H16
HOLE
Wistron Corporation
tm
H1
HOLE

ho
H21
HOLE
Size
f@
H20
HOLE
EMI/Spring/Boss
Document Number
Rev
SC
Cathedral Peak II
xa
in
H19
HOLE
he
SA
H18
HOLE
Sheet
1
41
of
43
SA to SB
1.No Power.
change KBC to BO (71.03310.A0G)
2.XD Card function fail
Cut CARD1 pin27. connect to R400 pin2
3.leakage
GFX power VDD connect to S0
4.Gain=8db.1.83W R137=16K.R138=30K
5.Int_MIC voice to small
add VREF C577=4.7U
6.Realtek Audio report
change R327=68 ohm.R333=68 ohm.merge to RN68
7.SIV reset
R140=300,R55=100.C44=100p,R398=0,R369=100.C502=100p,R85=300,R162=100.C210=100p,R392=0,
8.SIV Azalia
DY C542
BITCLK rise and fall time fail RN10 change to R453=22ohm(MDC).R452=0ohm(codec)
9.add MINICard power option for customer ask
R454.R455
10.interfere HDD
C390.C401.C419. change 0603 4.7U
11.power team
R38=12K.R47=2.74K .R361=110K.R221=100K.R237=10.7K .R424=20K.R420=17.8K .R227=10.5K
R48=10K.R29=2.2 .R37=2.2 .R401=3.3 .C49=0.1u.add R456.add C580.D8=83.R0203.08F .
TC11 change to 77.C2271.00L
TC9 change to 77.E9071.001 (power ripple)
add R458=1K.R459=1k.R460
12.Oscillation
C30=15p.C23=15P.C537=27p.C538=22p
13.audio S3.S4 resume bobo sound
R143 DY. R187 0ohm pad
14.AC mode have hight frequency noise
R390 DY.R389 0ohm pad
15.ESD issue
BAT_IN# series 33 ohm
RN42 change to 8p4r
add R457.D27.D28.D29.U55.U56.C578.R457.
16.noise
DY C523.TC25 change to 77.C1561.01L
20.LED brightness
R2.R1.R4.R5.R451.R450.R449.R448=56
EMI
1.EC23 ~~EC48.EC134.EC135.EC167.EC121.EC122.EC123.
2.EC89.EC12.EC8.EC119.EC156.EC173.
3.EC174~~~EC179.
4.GND13.GND14.
05/05
Page16: merge LAUNCHCN1 LEDCN1 to LAUNCHCN1 15pins
Page15: change CRT1 from 20.20717.015 to 20.20378.015
Page26: change RJ1 from 22.10277.011 to 22.10245.E91
D
Page23: change BLUE1 from 20.D0197.004 to 20.F0984.004

Page24: change CARD1 from 20.I0081.001 to 20.I0067.001
Page21: change FAN1 from 20.F0714.003 to 20.F1000.003
Page27: change MINIC1 from 20.F1049.052 to 62.10043.331
Page30: change TPAD1 from 20.K0286.012 to 20.K0174.012
Page34: change U29 U30 from 84.07686.037 to 84.12003.A37 and change U7 U11 U28
U31 from 84.04634.037 to 84.57N03.A37
Page16: delete LED1 LED2 R1 R2 R4 R5
05/07
Page17: change RTC1 from 62.70001.011 to 20.F0700.003
Page41: delete EC51
Page10: delete C159
Page25: change U13 from 72.24256.R01 to 72.24C08.J01
Merge
1.R313.R314.R315.R319.R320.R149. change to RN59
2.RN6.RN46. change to RN6
3.R341.R343.R344 change to RN46
4.R385 change to 100K merge R382 to RN56
5.RN53.RN56. change to RN53
6.Q20.Q21 change to Q21. Q21.Q23 change to Q21.
7.R367.R368 change to RN60
8.Q16.Q17 change to Q16
9.R262.R264.R268.R277 change to RN61
11.RN33.R215 change to RN33
13.R280=10K.merge R269 to RN64
14.R109.R112.R111.R290 change to RN65
17.U14 change to 73.01G08.L04 .add C579
18.R51.R399 vhange to RN69.
05/08
Page30: change KB1 from 20.K0127.026 to 20.K0204.026
B
Page26: delete RN36 RN37 RN38 RN39

Page23: change TC28 from 80.15715.34L to 77.C1071.081
Page26: change TC15 from 80.15715.34L to 80.15715.12L
Page23: delete R244 R245 R246 R247 R248 R249 R250 R251
0 Ohm change to PAD

R427.R403.R415.R413.R411.R408.R404.R146.R197.R157.R153.R353.R352.R358.R357.R310.R196.R346.R342.R351.
R191.R203.L14.R212.R350.R179.R217.R6.R7.R242.R294.R278.R279.R292.R293.R232.R233.R410.R393.
R416.R250.R251.R248.R249.R246.R247.R244.R245.R129.R127.R376.ER2.R383.R28.R16.R19.R20.R21.
R22.R23.R24.R25.R57.R58.R365.R164.
Page24: change CARD1 from 20.0067.001 to 20.I0079.001

05/09
Page41: delete GND13
05/12
Page24: add EC127 EC128 EC185 EC186
Wistron Corporation
Page35: change TC27 from 77.C1561.01L to

77.C1561.03L
Title
Size
Page40: change BAT1 from 20.80697.007 to

20.80906.007
5
Change List
Document Number
Rev
SC
Cathedral Peak II
Sheet
1
42
of
43
05/13
Page16: change pin1 pin2 of LED6 from 3D3V_S5 to 3D3V_AUX_S5
06/13
Page37: change R446 R447 from 0ohm pad to 0ohm resistor
Page26: change XF1 from 68.69241.301 to 68.89240.30A
05/14
Page17: add EC187 EC188
06/17
Page39: C320 mount
Page16: add EC189 TP189~TP195

Page30: change TPAD1 from 20.K0174.012 to 20.K0228.012
Page40: EC104 mount

Page41: EC95 mount
Page41: add EC190~EC195
Page39: change R11 from 10K to 49K9
05/15
Page17: change U15 pin13 pin14 from pull high 3D3V_S0 to VGATE_PWRGD
Page34: change C49 from 47nF to 22nF and change R47 from 2.74K to 1.74K
Page17: change Q11 G from 3D3V_S0 to VGATE_PWRGD
Page37: add C581 C582
Page40: change D1 from 83.P4SSM.BAM to 83.P6SBM.AAG
Page41: delete GND6
SB
05/15
Page30: change KBC_GPIO0C from pull-high 3D3V_AUX_S5 with 10K to
pull-low GND with 1K
06/20
Page25: change C30 from 15p to 12p
06/06
Page3: change C176 C177 from 78.27034.1FL (27p) to 78.33034.1FL (33p)
SC
06/30
Page37: change R446 R447 from 0ohm resistor to 0ohm pad
07/07
Page3: change C462 to DY
Page22: delete D15

Page29: change R127 R129 from 0ohm pad to 12K 1K5 and change R137
R138 from 16K 30K to 13K 20K
Page16: change EC22 to DY

Page34: change TC1 from 77.C1561.01L (15u) to 79.10712.L02 (100u) and

C14 C37 C38 C319 dummy
Page40: change D29 to DY
Page35: change TC25 from 77.C1561.01L (15u) to 79.68612.30L (68u)

and change C292 to dummy
Page10: change C187 C175 C263 to DY

Page37: add TC30 79.68612.30L (68u) and change C553 C563 to dummy
Page19: change C396 C407 to DY
Page39: change C61 to dummy
Page41: add TC31 TC32 TC33 TC34 and delete GND9
Page41: change EC89 EC119 EC156 EC173 to DY
06/09
Page16: add LED3 R458 R465
ai
l.c
om
tm
Wistron Corporation
Size
06/13
Page3: add EC59 DY
5
Change List
Document Number
f@
Title
xa
in
Page30: delete R397, S5_ENABLE_KBC connect

to RN30 PIN5, RN30 PIN4 connect to GND
ho

06/11
Page30: change R379 from 10K to 1K
Rev
SC
Cathedral Peak II
4
he
Page38: change C536 to dummy and change TC24 from 77.C1561.01L (15u)
to 79.68612.30L (68u)
Sheet
1
43
of
43
07/07
Page14: add F3, DY F4
06/13
Page34: DY C15 C36, add C319 C38

D

Page34: change TC1 to mount
Page38: change TC24 to GFX
Page41: change TC31 TC32 TC33 TC34 to mount
C
07/09
Page34: change C322 C331 from DY to mount
Page39: change EC108 from DY to mount
Page40: change EC6 from DY to mount
07/10
Page18: DY R136 R305 for ICS, DY R135 R305 for RTL
Page16: change LAUNCHCN1 to 2nd source
Page3: change EC59 from 5p DY to 22p mount
B
07/10
Page17: change RTC1 from 20.F0700.003 to 62.70001.011
Page32: change C574 from 1u to 2.2u
07/16
Page40: change EC102 to mount
Page41: change EC89 EC119 EC173 to mount
A
Wistron Corporation
Page41: change EC133 to mount on GM45

Title
Page29: change R127 from 12K to 6.8K, change R129 from 1.5K to 2K,
change R138 from 20K to 30K
Size
Change List
Document Number
Rev
SC
Cathedral Peak II
5
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Acer Aspire 5235 5535 5735 - Wistron Cathedral Peak II

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Acer Aspire 5235 5535 5735 - Wistron Cathedral Peak II

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5

Cathedral Peak II Block Diagram

Project code: 91.4K801.001

ICS 9LPRS365BKLFT (71.09365.A03)

LVDS, CRT I/F

12 USB 2.0/1.1 ports

Matrix Storage Technology(DO)

Date: Wednesday, July 16, 2008

Active Managemnet Technology(DO)

Serial Peripheral I/F

High Definition Audio

DDR Memory I/F

AGTL+ CPU I/F

ICH9M Functional Strap Definitions

ICH9M Integrated Pull-up

ICH9 EDS 642879

XOR Chain Entrance/

PCIE config1 bit0,

This signal has a weak internal pull-down.

PCIE config2 bit2,

This signal has a weak internal pull-up.

Integrated TPM Enable,

Sample low: the Integrated TPM will be disabled.

Signal has weak internal pull-up. Sets bit 27

If sampled high, the system is strapped to the

This signal should not be pull low unless using

PCIE Loopback enable

FSB Dynamic ODT

0 = Dynamic ODT Disabled

DMI Lane Reversal

Digital Display Port 0 = Only Digital Display Port

Local Flat Panel

1= LFP Card Present; PCIE disabled

PCI Express Lane

XOR Chain Entrance.

0 = Reverse Lanes,15->0,14->1 ect..

PCIE Graphics Lane

Controllable via Boot BIOS Destination bit

The pull-up or pull-down active when configured for native CFG9

Boot BIOS Destination

0 = Transport Layer Security (TLS) cipher

DMI Termination Voltage, The signal is required to be low for desktop

Sampled low:Top-Block Swap mode(inverts A16 for

Montevina Platform Design guide 22339

LAN MARVELL 88E8071

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

ICS9LPRS365BKLFT setting table

0 = Overclocking of CPU and SRC Allowed

3.3V PCI clock output

0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96#

SEL2 SEL1 SEL0

Date: Wednesday, July 16, 2008

Follow Demo Circuit

Net "TEST4" as short as possible,

All place within 2" to CPU

Wednesday, July 16, 2008

layout note: "1D5V_VCCA_S0"

VCCSENSE and VSSSENSE lines

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Wednesday, July 16, 2008

H_SWING routing Trace width and

H_SWING Resistors and

H_RCOMP routing Trace width and