ECE 2222- Digital Design Lab

Course Instructor: Ms. Saba Zia Lab 2: Gate Level Modeling

20-Feb-13

Multiplexer Implementation (Gate level)- 2X1 MUX

A 0 X X0 A 0 X1 0 X0 0 X 0 X = A . X0 + A . X1

X1

0
0 0 1 1 1 1 w1 w2

0
1 1 0 0 1 1

1
0 1 0 1 0 1

1
0 1 0 0 1 1

not ins1 (w1,A); not ins2 (w2,w1); and ins3 (w3,w2,X1); and ins4 (w4,w1,X0); or ins5 (X,w3,w4);
20-Feb-13 2

w3

w4

Task 1
Design 4X1 MUX using 2X1 MUX and write its Verilog HDL code using gate level modeling. Show its RTL Schematic

Show its Simulation (Waveform)

20-Feb-13

Half adder

20-Feb-13

Full Adder from half adder

20-Feb-13

4-bit Full Adder using 1-bit Full Adder

20-Feb-13

Task 2 (Home Assignment # 1)

Design half adder, then design full adder using half adders and OR gate. Design 4-bit Adder using full adders Show its RTL Schematic Show its Simulation (Timing Waveform) Viva would be at the start of next lab

20-Feb-13