Digital Circuits II

DAPA E.T.S.I. Informtica Universidad de Sevilla 10/2012

Jorge Juan <jjchico@dte.us.es> 2010, 2012 You are free to copy, distribute and communicate this work publicly and make derivative work provided you cite the source and respect the conditions of the Attribution-Share alike license from Creative Commons. You can read the complete license at: http://creativecommons.org/licenses/by-sa/3.0

Departamento de Tecnologa Electrnica Universidad de Sevilla

Contents

System perspective: blocks Subsystem general characteristics Decoders Multiplexers Demultiplexers Priority encoders Code converters Comparators

Departamento de Tecnologa Electrnica Universidad de Sevilla

Subsystem perspective

Blocks make digital systems easier to design

Divide and conker!

Combinational subsystems are combinational blocks that make general purpose useful combinational functions Many practical problems are solved more easily by splitting and mapping to subsystems Specially interesting when problems have many inputs or outputs

General purpose boolean minimization is not feasible

Departamento de Tecnologa Electrnica Universidad de Sevilla

General characteristic

Many binary inputs and/or outputs

Many inputs/outputs work together: multi-bit signals Similar functionality, number of inputs/outputs may change Modular design: subsystems are designed by thinking on one bit and extending to n bits. multiplexing, decoding, encoding, Data Control

Modularity

Functionality expressed in terms of data processing:

Two types of ports:

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Control signals

Put a condition on the overall operation of the subsystems

E1

E2

E3

Enable Output enable Select signal is active when low (0) signal is active when high (1)

Active low

Active high

Enabled if E1=1 & E2=0 & E3=0

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Multi-bit (vector) signals

a1

z1 a

E n p m Z

an c1 zp cm c

Departamento de Tecnologa Electrnica Universidad de Sevilla

Decoder
0 a1 a0 1
DEC 2:4

d0 d1 d2 d3

a1 a0 d0 d1 d2 d3 0 0 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1

1 2 3

Only one active output for each input vector n inputs 2n outputs Implement all the minterms of the input variables d0 = m0 = a1 a0 d1 = m1 = a1 a0 d2 = m2 = a1 a0 d3 = m3 = a1 a0 Natural binary to one-hot code converter

module module dec4 dec4 ( ( input input wire wire [1:0] [1:0] a, a, output output reg reg [3:0] [3:0] d d ); ); always always @(a) @(a) case case (a) (a) 2'h0: 2'h0: d d= = 4'b0001; 4'b0001; 2'h1: 2'h1: d d= = 4'b0010; 4'b0010; 2'h2: 2'h2: d d= = 4'b0100; 4'b0100; 2'h3: 2'h3: d d= = 4'b1000; 4'b1000; endcase endcase endmodule endmodule // // dec4 dec4

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Decoder with enable

E a1 a0 1
DEC 2:4

E 0 1 2 3 d0 d1 d2 d3 0 1 1 1 1

a1 a0 d0 d1 d2 d3 x 0 0 1 1 x 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1

If E (enable) is not active, none of the outputs is active.

module module dec4 dec4 ( ( input input wire wire [1:0] [1:0] a, a, input input wire wire e, e, output output reg reg [3:0] [3:0] d d ); ); always always @(a, @(a, E) E) if if (E (E == == 0) 0) d d = = 4'b0000; 4'b0000; else else case case (a) (a) 2'h0: 2'h0: d d= = 4'b0001; 4'b0001; 2'h1: 2'h1: d d= = 4'b0010; 4'b0010; 2'h2: 2'h2: d d= = 4'b0100; 4'b0100; 2'h3: 2'h3: d d= = 4'b1000; 4'b1000; endcase endcase endmodule endmodule // // dec4 dec4
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Decoder with enable. Active low

E a1 a0 1
DEC 2:4

E 0 1 2 3 d0 d1 d2 d3 0 1 1 1 1

a1 a0 d0 d1 d2 d3 x 0 0 1 1 x 0 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0

Implement all the maxterms of the input variables d0 = M0 = a1 + a0 d1 = M1 = a1 + a0 d2 = M2 = a1 + a0 d3 = M3 = a1 + a0 Natural binary to one-cold code converter

module module dec4 dec4 ( ( input input wire wire [1:0] [1:0] a, a, input input wire wire e, e, output output reg reg [3:0] [3:0] d d ); ); always always @(a, @(a, E) E) if if (E (E == == 0) 0) d d = = 4'b0000; 4'b0000; else else case case (a) (a) 2'h0: 2'h0: d d= = 4'b1110; 4'b1110; 2'h1: 2'h1: d d= = 4'b1101; 4'b1101; 2'h2: 2'h2: d d= = 4'b1011; 4'b1011; 2'h3: 2'h3: d d= = 4'b0111; 4'b0111; endcase endcase endmodule endmodule // // dec4 dec4
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Multiplexer
d0 0 s1 s0 0 0 d1 1 z d2 2 1 1 0 1 0 1 z d0 d1 d2 d3 module module mux4 mux4 ( ( input input wire wire [3:0] [3:0] d, d, input input wire wire [1:0] [1:0] s, s, output output reg reg z z ); ); always always @(d, @(d, s) s) case case (s) (s) 2'h0: 2'h0: z z= = d[0]; d[0]; 2'h1: 2'h1: z z= = d[1]; d[1]; 2'h2: 2'h2: z z= = d[2]; d[2]; 2'h3: 2'h3: z z= = d[3]; d[3]; endcase endcase endmodule endmodule // // mux4 mux4

Output z is equal to the data input (dx) selected by the selection inputs (sx)

d3

s1

s0

z = s1 s0 d0 + s1 s0 d1 + s1 s0 d2 + s1 s0 d3

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Multiplexer with enable

e d0 0 e 0 1 1 d1 1 z d2 2 1 1 s1 s0 x 0 0 1 1 x 0 1 0 1 z 0 d0 d1 d2 d3 module module mux4 mux4 ( ( input input wire wire [3:0] [3:0] d, d, input input wire wire [1:0] [1:0] s, s, input input wire wire e, e, output output reg reg z z ); ); always always @(d, @(d, s) s) if if (e (e == == 0) 0) z z= = 1'b0; 1'b0; else else case case (s) (s) 2'h0: 2'h0: z z= = d[0]; d[0]; 2'h1: 2'h1: z z= = d[1]; d[1]; 2'h2: 2'h2: z z= = d[2]; d[2]; 2'h3: 2'h3: z z= = d[3]; d[3]; endcase endcase endmodule endmodule // // mux4 mux4

d3

s1

s0

z = e s1 s0 d0 + e s1 s0 d1 + e s1 s0 d2 + e s1 s0 d3

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Demultiplexer
E a1 a0 1
DEC 2:4

0 0 1 2 3 d0 d1 d2 d3 1 0 E 1 2 3

d0 d1 d2 d3

a1 a0 E 0 1 1 1 1 a1 a0 d0 d1 d2 d3 x 0 0 1 1 x 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 a1 a0 d0 d1 d2 d3 0 0 1 1 0 1 0 1 E 0 0 0 0 E 0 0 0 0 E 0 0 0 0 E

The decoder (with enable) and the demultiplexer are the same circuit

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Encoders
d0 d1 d2 d3 0 1 2 3
ENC 2:4

d0 d1 d2 d3 a1 a0 1 0 a1 a0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 1

Other values are don't cares

Encoders output the number of the input that is active. Inputs can be active low or high. Output value can be encoded in different forms: Natural binary Gray Etc.

module module enc enc ( ( input input wire wire [3:0] [3:0] d, d, output output reg reg [1:0] [1:0] a a ); ); always always @(d) @(d) case case (d) (d) 4'b0001: 4'b0001: a a = = 2'b00; 2'b00; 4'b0010: 4'b0010: a a = = 2'b01; 2'b01; 4'b0100: 4'b0100: a a = = 2'b10; 2'b10; 4'b1000: 4'b1000: a a = = 2'b11; 2'b11; default: default: a a = = 2'bxx; 2'bxx; end end endmodule endmodule // // enc enc

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Priority encoders
d0 d1 d2 d3 a1 a0 d0 d1 d2 d3 0 1 2 3
ENC 2:4

e 1 0 0 0 0

0 1 0 a1 a0 e 1 x x x

0 0 1 x x

0 0 0 1 x

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

module module pri_enc pri_enc ( ( input input wire wire [3:0] [3:0] d, d, output output reg reg [1:0] [1:0] a a ); );

Priority encoders solve the problem of having don't cares by using different priorities for the inputs Output e activates when no input is active: there is nothing to encode.

always always @(d) @(d) if if else else if if else else if if else else

(d[3]) (d[3]) (d[2]) (d[2]) (d[1]) (d[1])

a a a a a a a a

= = = = = = = =

2'b11; 2'b11; 2'b10; 2'b10; 2'b01; 2'b01; 2'b00; 2'b00;

assign assign e e= = ~|d; ~|d; endmodule endmodule // // pri_enc pri_enc

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Code converters

Convert information from one encoding to another

(Natural) binary to Gray Gray to binary BCD/7-segment ...

DATA (code A)

A/B code conv

DATA (code B)

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Example 2-bit Bin/Gray converter

b1 b0 1 0
BIN/ GRAY CONV

1 0

g1 g0

module module bin_gray_conv bin_gray_conv ( ( input input wire wire [1:0] [1:0] b, b, output output reg reg [1:0] [1:0] g g ); ); always always @(b) @(b) case case (b): (b): 2'b00: 2'b00: g g= = 2'b00; 2'b00; 2'b01: 2'b01: g g= = 2'b01; 2'b01; 2'b10: 2'b10: g g= = 2'b11; 2'b11; default: default: g g= = 2'10; 2'10; end end endmodule endmodule // // bin_gray_conv bin_gray_conv

b1 b0 g1 g0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0

g1 = b1 g0 = b1 b0
module module bin_gray_conv bin_gray_conv ( ( input input wire wire [1:0] [1:0] b, b, output output reg reg [1:0] [1:0] g g ); ); g1 g0 assign assign g[1] g[1] = = b[1]; b[1]; assign assign g[0] g[0] = = b[1] b[1] ^ ^ b[0]; b[0]; endmodule endmodule // // bin_gray_conv bin_gray_conv

b1 b0

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BCD/7-segment converter
an A d[3:0] D0 D1 D2 D3 BCD/7S A B C D E F G seg[0:6]

F G

d3d2d1d0
0000

d
0 1 2 3 4 5 6 7 8 9

seg[0:6] ABCDEFG
0000001 1001111 0010010 0000110 1001100 0100100 0100000 0001111 0000000 0001100

D A B C D E F G

0001 0011 0010 0110 0111 0101 0100 1100 1101

an should be '0' for the device to work.

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BCD/7-segment converter
d0 d[3:0] d1 d2 d3 BCD/7S A B C D E F G seg[0:6] module module bcd_7s bcd_7s ( ( input input wire wire [3:0] [3:0] d, d, output output reg reg [0:6] [0:6] seg seg ); ); always always @(b) @(b) case case (d): (d): 4'h0: seg 4'h0: seg 4'h1: seg 4'h1: seg 4'h2: seg 4'h2: seg 4'h3: seg 4'h3: seg 4'h4: seg 4'h4: seg 4'h5: seg 4'h5: seg 4'h6: seg 4'h6: seg 4'h7: seg 4'h7: seg 4'h8: seg 4'h8: seg 4'h9: seg 4'h9: seg default: default: seg seg end end endmodule endmodule // // bcd_7s bcd_7s

d3d2d1d0
0000 0001 0011 0010 0110 0111 0101 0100 1100 1101

d
0 1 2 3 4 5 6 7 8 9

seg[0:6] ABCDEFG
0000001 1001111 0010010 0000110 1001100 0100100 0100000 0001111 0000000 0001100

= = = = = = = = = = = = = = = = = = = = = =

7'b0000001; 7'b0000001; 7'b1001111; 7'b1001111; 7'b0010010; 7'b0010010; 7'b0000110; 7'b0000110; 7'b1001100; 7'b1001100; 7'b0100100; 7'b0100100; 7'b0100000; 7'b0100000; 7'b0001111; 7'b0001111; 7'b0000000; 7'b0000000; 7'b0001100; 7'b0001100; 7'b1111110; 7'b1111110;

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Comparators
a3 a2 a1 a0 A G0 E0 L0 b3 b2 b1 b0 B A>B G module module comp4( comp4( input input [3:0] [3:0] a, a, input input [3:0] [3:0] b, b, input input g0, g0, e0, e0, l0, l0, output output reg reg g, g, e, e, l l ); ); always always @(*) @(*) begin begin if if (a (a > > b) b) {g,e,l} {g,e,l} = = 3'b100; 3'b100; else else if if (a (a < < b) b) {g,e,l} {g,e,l} = = 3'b001; 3'b001; else else {g,e,l} {g,e,l} = = {g0,e0,l0}; {g0,e0,l0}; end end endmodule endmodule

A=B

A<B

AB A>B A<B

L 0 L0 1

1 0 A=B G0 E0 0 0

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Comparators
12-bit comparator out of 4-bit comparators

a3 a2 a1 a0 0 1 0 b3 b2 b1 b0

A G0 E0 L0 B

A>B

a7 a6 a5 a4

A G0 E0 L0

A>B

a11 a10 a9 a8

A G0 E0 L0

A>B

A=B b7 b6 b5 b4

A=B b11 b10 b9 b8

A=B

A<B

A<B

A<B

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