A

A6A

A6

A5

A4

6/28/2012

5/10/2012

2/3/2012

THERE IS NO WARRANTY FOR THIS DESIGN , TO THE EXTENT

PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED
IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
PROVIDE THE DESIGN AS IS WITHOUT WARRANTY OF ANY KIND,
EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE
QUALITY AND PERFORMANCE OF THE DESIGN IS WITH YOU. SHOULD
THE DESIGN PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL
NECESSARY SERVICING, REPAIR OR CORRECTION.

This schematic is *NOT SUPPORTED* and DOES NOT constitute

a reference design. Only community support is allowed
via resources at BeagleBoard.org/discuss.

1. Corrected typo on page 8 for correct pin on LAN8710A for MODE2 function.

1. Changed R219 to installed.

2. Added R220 , a 10K pulldown to pin 18 of the SMSC PHY to allow R219 addition to work as
expected..
3. Removed the connection to the VPP pin on the processor.
4. Added R221, R218, R217, R202 to facilitate the addition of two signals, GPIO3_18 and
GPIO3_19 to the expansion bus header to provide two more signals for the PRU access..
5. Changed R210 to installed and added test point to allow the EEPROM to be programmed
but with added protection to prevent corruption. Added Test Point to enable programming.
6. Moved Resistors R189 and R150 to provide more clearence around mounting hole.
7. PCB revision was changed to C2.
8. Change pullups on the boot pins to 42.2K per AM335x design team.
9. Rewired the JTAG reset signal from the optional JTAG connector.
10. R122 was removed becasue it was connectd to the wrong pin on the SMSC LAN8710.
11. R172 was removed due to a spurious reset generated by the FT2232 when under CCS, the
target was connected.

2. Removed the connection of the VPP to VDD_CORE as suggested by TI.

1. Changed R219 to DNI. It was causing issues with Ethernet DHCP IP address
aquisition. Will be added back in on revision A6.

5. Changed C7 to a 0805 package in PCB layout.

4. Added 10K pulldown to fix link speed LED.

12/1/2011

11/5/2011

Updated in conjunction with the release of the SRM. Typos and naming changes. No change
in design.

A3A

1. Changed supplier for the SD card connector due to availability issue. Created a dual footprint
for two differrent parts. SD connector is now reversed, so label down is the new orientation.
2. Changed R76 from a 50 ohm to 49.9 ohm. Smaller package and lower cost. Changed
footprint to 0402.
3. Changed C99 termination to DGND.

10/21/2011

GC

GC

GC

GC

GC

GC

DATE BY

Production release.

Description

A3

REV

BeagleBone Cover Page

Document Number
B

450-5500-001
Date: Thursday, June 28, 2012

Size

Title

Sheet

of

11

Rev
A6A

NOTE: PCB Revision for this board is Rev C2.

SERIAL AND JTAG

USB CONCENTRATOR

EXP CONN, uSD, AND LDO

ETHERNET AND USB HOST

10

MEMORY

11

LED, CONFIGURATION AND BUTTON

PROCESSOR 3 OF 3

PROCESSOR 2 OF 3

PROCESSOR 1 OF 3

POWER MANAGEMENT

2
3

COVER PAGE

SCHEMATIC PAGE

PAGE NO.

4,7
4,7

11

7
1

EN

IN0
IN1

BAT
BAT_TEMP
BL_ISET1
BL_IN
BL_SINK2

2
4
6
8
10

HDR5x2

P6

DGND

1
3
5
7
9

5
4

USB_DC

BAT
BAT_SENSE
BL_ISET2
BL_OUT
BL_SINK1

NCP349

FLAG

OUT1
OUT0

MHOLE

MTG4

MHOLE

MTG3

MHOLE

MTG2

MHOLE

MTG1

DGND

TESTPT1

TP1

C2

DGND

R1

DGND

C5

C4

DGND

DGND

4.7uF,6.3V 4.7uF,6.3V

C1

DGND

DC_IN

EXPANSION HEADER

PWR_BUT
I2C0_SCL
I2C0_SDA

VDD_3V3A

DGND

4 PMIC_POWR_EN

PJ-200A

P5

U1

R7

1.5K,5%

GND

5V DC POWER

R4

1.5K,5%

10uF,10V

C17

AGND

R15

10uF,10V

C19

10uF,10V

10uF,10V

C10

C18

10uF,10V

10uF,10V

R2
12.1K,1%

C9

C8

10uF,10V

10uF,10V

4.75K,1%

0,1%

14

P_MUXIN

DGND

42

39

32

22

21

BL_ISET1 35

BL_ISET2 36

9
44
25
28
27

47

48

17
15

12

10

P_BYPASS

P_INT_LDO

SYS_VOLT

TPS65217b

VINLDO

LDO4_IN

LDO3_IN

VIN_DCDC3

VIN_DCDC2

VIN_DCDC1

ISET1

ISET2

PWR_EN
RESET
PB_IN
SCL
SDA

MUX_IN

BYPASS

INT_LDO

NC1
NC

USB

AC

U2

R3

AGND

VLDO2

VLDO1

LDO4

LDO3

VDCDC3

L3

VDCDC2

L2

VDCDC1

L1

L4

FB_WLED

ISINK1
ISINK2

VIO
PGOOD
LDO_PGOOD
WAKEUP
INT

MUX_OUT

BAT1
BAT2
BAT_SENSE
TS

SYS1
SYS2

.1,0805

DGND

AGND

41

VDD_5V

PGND
30

PPAD
49

BAT

VDCDC1
P_L2
VDCDC2

23
24

LDO3
LDO4

1.8V@100mA

40
43
3
1

VDCDC3

DGND

L2

2
2.2uH,2.6A

DGND

2.2uF,6.3V

C20

VRTC

470,5%

R6

C165
10uF,10V

0,1%
VDD_3V3A

PWR_LEDR

TP14
TESTPT1

Document Number
B

C16

R14

VDD_1V8

3
3

D1

Sheet

598-8170-107F

GRN

PMIC_INT

TP18
TESTPT1

0,1%

VDDS_DDR

10uF,10V 22uF,6.3V

C15

PMIC_PGOOD
LDO_PGOOD
WAKEUP

0,1%

of

11

DGND

POWER LED

DGND

10uF,10V

C14

DGND

AIN7

VDD_MPU

0,DNI

BeagleBone Power Management

PWR_LED

DGND

100K,1%

TESTPT1
TP15

R9

R10

PMIC_INT_PU
R28

TP17TESTPT1
VDD_CORE

0,1%

C135
10uF,10V DGND

3.25V
VDD_3V3B

R13

R204

7
SN74LVC2G00DCU

U14A

DGND

0,1%

VDD_3V3B

450-5500-001
Date: Thursday, June 28, 2012

Size

Title

0,1%

0,1%

0,1%

R12

100K,1%

C7
4.7uF,50V

2
2.2uH,2.6A

L1

2
2.2uH,2.6A

L3

R121

R19

P_L3

31
29

P_L1

BL_IN

37

20

BL_OUT

38

19

BL_SINK1
BL_SINK2

R8

DGND

R203

VDD_3V3B

100K,1%

C3
10uF,10V

P_W AKEUP
R11
PMIC_INT_SRC

P_MUXOUT

VDD_3V3A

BAT_SENSE
BAT_TEMP

34
33

18
26
46
13
45

16

4
5
6
11

7
8

SYS_5V

8
4

Rev
A6A

GND_OSC0

18pF,50V

C26

DDR_BA[2..0]

DDR_D[15..0]

DDR_A[13..0]

C27
18pF,50V

7
7

7
7

OSC0_OUT1

24MHz,DNI
Y3

Y2

DDR_A[13..0]

0,1%

DDR_ODT

DDR_DQM0
DDR_DQS0
DDR_DQSN0
DDR_DQM1
DDR_DQS1
DDR_DQSN1

DDR_D[15..0]

DDR_CLK
DDR_CLKn
DDR_CKE
DDR_CSn
DDR_CASn
DDR_RASn
DDR_WEn

R24

R21
1M,1%

DDR_BA[2..0]

24MHz

7
7
7
7
7
7
7

33,0402

R67
R68
R69
R70
R71
R72
R73

DDR_VREF

OSC1_OUT
GND_OSC1

OSC1_IN

OSC0_OUT
GND_OSC0

OSC0_IN

DGND

R75
2.2K,1%

PDDR_ODT
DDR_RESETN

PDDR_DQM0
PDDR_DQS0
PDDR_DQSN0
PDDR_DQM1
PDDR_DQS1
PDDR_DQSN1

PDDR_CLK
PDDR_CLKn
PDDR_CKE
PDDR_CSn
PDDR_CASn
PDDR_RASn
PDDR_WEn

PDDR_D0
PDDR_D1
PDDR_D2
PDDR_D3
PDDR_D4
PDDR_D5
PDDR_D6
PDDR_D7
PDDR_D8
PDDR_D9
PDDR_D10
PDDR_D11
PDDR_D12
PDDR_D13
PDDR_D14
PDDR_D15

PDDR_BA0
PDDR_BA1
PDDR_BA2

PDDR_A0
PDDR_A1
PDDR_A2
PDDR_A3
PDDR_A4
PDDR_A5
PDDR_A6
PDDR_A7
PDDR_A8
PDDR_A9
PDDR_A10
PDDR_A11
PDDR_A12
PDDR_A13

2.2K,1%

TESTPT1

33,0402
33,0402
33,0402
33,0402
33,0402
33,0402

R60
R61
R62
R63
R64
R65
R66

R74

33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402

R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59

DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15

VDDS_DDR

33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402

R41
R42
R43

33,0402
33,0402
33,0402

33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402
33,0402

DDR_BA0
DDR_BA1
DDR_BA2

TP3

R22
0,1%

R29
R25
R30
R26
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40

32.768KHz MC-306

Y1

25pF,50V

2
OSC1_OUT1
C24

DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13

25pF,50V

C23

DGND

DDR_VTP

R76
49.9,1%

J4

G1
G2
J3

M2
P1
P2
J2
L1
L2

D2
D1
G3
H2
F1
G4
B2

M3
M4
N1
N2
N3
N4
P3
P4
J1
K1
K2
K3
K4
L3
L4
M1

F3
H1
E4
C3
C2
B1
D5
E2
D4
C1
F4
F2
E3
H3
H4
D3
C4
E1
B3

A4
A5

A6

U11
V11

V10

AM335X_ZCZ

VREFSSTL

DDR_ODT
DDR_RESETN
DDR_VTP

DDR_DQM0
DDR_DQS0
DDR_DQSN0
DDR_DQM1
DDR_DQS1
DDR_DQSN1

DDR_CK
DDR_NCK
DDR_CKE
DDR_CSN0
DDR_CASN
DDR_RASN
DDR_WEn

DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15

DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_A14
DDR_A15
DDR_BA0
DDR_BA1
DDR_BA2

OSC1_OUT
VSS_RTC

OSC1_IN

DGND

C22

5
VRTC_DETB
6
3
VRTC_DET_OUT

DGND

0,1%,DNI

R143

DGND

12.1K,1%

R18

R141

10K,1%

PORZ
NRESET_INOUT
RTC_PORZ

2 PMIC_PGOOD

RTC_PORZ

NTRST
TMS
TDI
TCK
TDO
EMU0/GPIO3_7
EMU1/GPIO3_8

MMC0_CLK/GPMC_A24/UART3_CTSN/UART2_RXD/DCAN1_TX/PR1_PRU0_PRU_R30_12/PR1_PRU0_PRU_R31_12/GPIO2_30
MMC0_CMD/GPMC_A25/UART3_RTSN/UART2_TXD/DCAN1_RX/PR1_PRU0_PRU_R30_13/PR1_PRU0_PRU_R31_13/GPIO2_31
MMC0_DAT0/GPMC_A23/UART5_RTSN/UART3_TXD/UART1_RIN/PR1_PRU0_PRU_R30_11/PR1_PRU0_PRU_R31_11/GPIO2_29
MMC0_DAT1/GPMC_A22/UART5_CTSN/UART3_RXD/UART1_DTRN/PR1_PRU0_PRU_R30_10/PR1_PRU0_PRU_R31_10/GPIO2_28
MMC0_DAT2/GPMC_A21/UART4_RTSN/TIMER6/UART1_DSRN/PR1_PRU0_PRU_R30_9/PR1_PRU0_PRU_R31_9/GPIO2_27
MMC0_DAT3/GPMC_A20/UART4_CTSN/TIMER5/UART1_DCDN/PR1_PRU0_PRU_R30_8/PR1_PRU0_PRU_R31_8/GPIO2_26

GPMC_A0/GMII2_TXEN/RGMII2_TCTL/RMII2_TXEN/GPMC_A16/PR1_MII_MT1_CLK/EHRPWM1_TRIPZONE_INPUT/GPIO1_16
GPMC_A1/GMII2_RXDV/RGMII2_RCTL/MMC2_DAT0/GPMC_A17/PR1_MII1_TXD3/EHRPWM1_SYNCI_O/GPIO1_17
GPMC_A2/GMII2_TXD3/RGMII2_TD3/MMC2_DAT1/GPMC_A18/PR1_MII1_TXD2/EHRPWM1A/GPIO1_18
GPMC_A3/GMII2_TXD2/RGMII2_TD2/MMC2_DAT2/GPMC_A19/PR1_MII1_TXD1/EHRPWM1B/GPIO1_19
GPMC_A4/GMII2_TXD1/RGMII2_TD1/RMII2_TXD1/GPMC_A20/PR1_MII1_TXD0/EQEP1A_IN/GPIO1_20
GPMC_A5/GMII2_TXD0/RGMII2_TD0/RMII2_TXD0/GPMC_A21/PR1_MII1_RXD3/EQEP1B_IN/GPIO1_21
GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/PR1_MII1_RXD2/EQEP1_INDEX/GPIO1_22
GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/PR1_MII1_RXD1/EQEP1_STROBE/GPIO1_23
GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/PR1_MII1_RXD0/MCASP0_ACLKX/GPIO1_24
GPMC_A9/GMII2_RXD2/RGMII2_RD2/MMC2_DAT7/GPMC_A25/PR1_MII_MR1_CLK/MCASP0_FSX/GPIO1_25
GPMC_A10/GMII2_RXD1/RGMII2_RD1/RMII2_RXD1/GPMC_A26/PR1_MII1_CRS/MCASP0_AXR0/GPIO1_26
GPMC_A11/GMII2_RXD0/RGMII2_RD0/RMII2_RXD0/GPMC_A27/PR1_MII1_RXER/MCASP0_AXR1/GPIO1_27

GPMC_AD0/MMC1_DAT0//////GPIO1_0
GPMC_AD1/MMC1_DAT1//////GPIO1_1
GPMC_AD2/MMC1_DAT2//////GPIO1_2
GPMC_AD3/MMC1_DAT3//////GPIO1_3
GPMC_AD4/MMC1_DAT4//////GPIO1_4
GPMC_AD5/MMC1_DAT5//////GPIO1_5
GPMC_AD6/MMC1_DAT6//////GPIO1_6
GPMC_AD7/MMC1_DAT7//////GPIO1_7
GPMC_AD8/LCD_DATA23/MMC1_DAT0/MMC2_DAT4/EHRPWM2A/PR1_MII_MT0_CLK//GPIO0_22
GPMC_AD9/LCD_DATA22/MMC1_DAT1/MMC2_DAT5/EHRPWM2B/PR1_MII0_CRS//GPIO0_23
GPMC_AD10/LCD_DATA21/MMC1_DAT2/MMC2_DAT6/EHRPWM2_TRIPZONE_INPUT/PR1_MII0_TXEN//GPIO0_26
GPMC_AD11/LCD_DATA20/MMC1_DAT3/MMC2_DAT7/EHRPWM2_SYNCI_O/PR1_MII0_TXD3//GPIO0_27
GPMC_AD12/LCD_DATA19/MMC1_DAT4/MMC2_DAT0/EQEP2A_IN/PR1_MII0_TXD2/PR1_PRU0_PRU_R30_14/GPIO1_12
GPMC_AD13/LCD_DATA18/MMC1_DAT5/MMC2_DAT1/EQEP2B_IN/PR1_MII0_TXD1/PR1_PRU0_PRU_R30_15/GPIO1_13
GPMC_AD14/LCD_DATA17/MMC1_DAT6/MMC2_DAT2/EQEP2_INDEX/PR1_MII0_TXD0/PR1_PRU0_PRU_R31_14/GPIO1_14
GPMC_AD15/LCD_DATA16/MMC1_DAT7/MMC2_DAT3/EQEP2_STROBE/PR1_ECAP0_ECAP_CAPIN_APWM_O/PR1_PRU0_PRU_R31_15/GPIO1_15

G17
G18
G16
G15
F18
F17

R13
V14
U14
T14
R14
V15
U15
T15
V16
U16
T16
V17

U7
V7
R8
T8
U8
V8
R9
T9
U10
T10
T11
U12
T12
R12
V13
U13

V12
V6
U9
V9
T13
U6
T7
R7
T6
U18
T17
U17

B10
C11
B11
A12
A11
C14
B14

B18
A15
D14

B15
A10
B5

LDO_PGOOD

NNMI
EVENT_INTR0/TIMER4/CLKOUT1/SPI1_CS1/PR1PRU1R31_16/EMU2/GPIO0_19
EVENT_INTR1/TCLKIN/CLKOUT2/TIMER7/PR1PRU0_PRUR31_16/EMU3/GPIO0_20

SN74AUP2G08,DNI

U17B

VRTC

GPMC_CLK/LCD_MEM_CLK/GPMC_WAIT1/MMC2_CLK/PRT1_MII1_TXEN/MCASP0_FSR/GPIO2_1
GPMC_CSN0/GPIO1_29
GPMC_CSN1/GPMC_CLK/MMC1_CLK/PRT1EDIO_DATA_IN6/PRT1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_12/PR1_PRU1_PRU_R31_12/GPIO1_30
GPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31
GPMC_CSN3/MMC2_CMD/PR1_MDIO_DATA/GPIO2_0
GPMC_WEN/TIMER6/GPIO2_4
GPMC_OEN_REN/TIMER7/EMU4/GPIO2_3
GPMC_ADVN_ALE/TIMER4/GPIO2_2
GPMC_BE0N_CLE/TIMER5/GPIO2_5
GPMC_BE1N/GMII2_COL/GPMC_CSN6/MMC2_DAT3/GPMC_DIR/PR1_MII1_RXLINK/MCASP0_ACLKR/GPIO1_28
GPMC_WAIT0/GM112_CRS/GPMC_CSN4/RMII2_CRS_DV/MMC1_SDCD/PR1_MII1_RXDV/UART4_RXD/GPIO0_30
GPMC_WPN/GMII2_RXERR/GPMC_CSN5/RMII2_RXERR/MMC2_SDCD/PR1_MDIO_MDCLK/UART4_TXD/GPIO0_31

DGND

0.01uf,16V,DNI

VRTC_DET
R17
1.1K,1%,DNI

SN74AUP2G08,DNI

0.01uf,16V,DNI

C21

U17A

DGND

4
OSC0_OUT
VSS_OSC0

OSC0_IN

U5A

VRTC

8
4

CLKOUT_SRC

DGND

100K,1%

R20

0,1%

0,1%

0,1%

Document Number

BeagleBone Processor 1 of 3

11
11
11
11
11
11

R221

R218

R27

450-5500-001
Date: Thursday, June 28, 2012

Size

Title

MMC0_CLKO
MMC0_CMD
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3

6
6
6
6
USR0
USR1
USR2
USR3
USB1_OC

11
11
11
11

11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11

11
11
11
11
11
11
11

11
11
11
11

10
10
10
10
10
10
10

DGND

GPIO1_16
GPIO1_17
EHRPWM1A
EHRPWM1B

GPIO1_0
GPIO1_1
GPIO1_2
GPIO1_3
GPIO1_4
GPIO1_5
GPIO1_6
GPIO1_7
EHRPWM2A
EHRPWM2B
GPIO0_26
GPIO0_27
GPIO1_12
GPIO1_13
GPIO1_14
GPIO1_15

TIMER6
TIMER7
TIMER4
TIMER5
GPIO1_28
UART4_RXD
UART4_TXD

GPIO2_1
GPIO1_29
GPIO1_30
GPIO1_31

JTAG_TRSTn
JTAG_TMS
JTAG_TDI
JTAG_TCK
JTAG_TDO
JTAG_EMU0
JTAG_EMU1

R23
10K,1%

VDD_3V3A

C25
0.01uf,16V

11,8
10,6

Sheet

GPIO3_20

of

11

2
PMIC_INT
10
XDMA_EVENT_INTR0
10,11
CLKOUT2

SYS_WARMRESETn

SYS_RESETn

Rev
A6A

GPIO0_7

GPIO0_7SRC
0,1%
GPIO3_18
0,1%

R217

R202

TP4

USB0_ID
TESTPT1

C18

R17
R18
P18
P17
F15
T18

N17
N18
M15
P16
F16
P15

C16
C17

D15
D16
D18
D17

E16
E15
E18
E17

GMII1_RXCLK/UART2_TXD/RGMII1_RCLK/MMC0_DAT6/MMC1_DAT1/UART1_DSRN/MCASP0_FSX/GPIO3_10
GMII1_RXD0/RMII1_RXD0/RGMII1_RD0/MCASP1_AHCLKX/MCASP1_AHCLKR/MCASP1_ACLKR/MCASP0_AXR3/GPIO2_21
GMII1_RXD1/RMII1_RXD1/RGMII1_RD1/MCASP1_AXR3/MCASP1_FSR/EQEP0_STROBE/MMC2_CLK/GPIO2_20
GMII1_RXD2/UART3_TXD/RGMII1_RD2/MMC0_DAT4/MMC1_DAT3/UART1_RIN/MCASP0_AXR1/GPIO2_19
GMII1_RXD3/UART3_RXD/RGMII1_RD3/MMC0_DAT5/MMC1_DAT2/UART1_DTRN/MCASP0_AXR0/GPIO2_18
GMII1_RXERR/RMII1_RXERR/SPI1_D1/I2C1_SCL/MCASP1_FSX/UART5_RTSN/UART2_TXD/GPIO3_2
GMII1_RXDV/LCD_MEMORY_CLK/RGMII1_RCTL/UART5_TXD/MCASP1_ACLKX/MMC2_DAT0/MCASP0_ACLKR/GPIO3_4

AM335X_ZCZ

Title

A14
A13
B13
D12
C12
B12
C13
D13

V5
U5
R5
R6

R1
R2
R3
R4
T1
T2
T3
T4
U1
U2
U3
U4
V2
V3
V4
T5

H18 U5_H18
M18
M17

L18
M16
L15
L16
L17
J15
J17

K18
K17
K16
K15
J18
J16
H17
H16

R201

33,0402

BeagleBone Processor 2 of 3

MCASP0_AHCLKX/EQEP0_STROBE/MCASP0_AXR3/MCASP1_AXR1/EMU4/PR1_PRU0_PRU_R30_7/PR1_PRU0_PRU_R31_7/GPIO3_21
MCASP0_ACLKX/EHRPWM0A//SPI1_SCLK/MMC0_SDCD/PR1_PRU0_PRU_R30_0/PR1_PRU0_PRU_R31_0/GPIO3_14
MCASP0_FSX/EHRPWM0B//SPI1_D0/MMC1_SDCD/PR1_PRU0_PRU_R30_1/PR1_PRU0_PRU_R31_1/GPIO3_15
MCASP0_AXR0/EHRPWM0_TRIPZONE_INPUT//SPI1_D1/MMC2_SDCD/PR1_PRU0_PRU_R30_2/PR1_PRU0_PRU_R31_2/GPIO3_16
MCASP0_AHCLKR/EHRPWM0_SYNCI_O/MCASP0_AXR2/SPI1_CS0/ECAP2_IN_PWM2_OUT/PR1_PRU0_PRU_R30_3/PR1_PRU0_PRU_R31_3/GPIO3_17
MCASP0_ACLKR/EQEP0A_IN/MCASP0_AXR2/MCASP1_ACLKX/MMC0_SDWP/PR1_PRU0_PRU_R30_4/PR1_PRU0_PRU_R31_4/GPIO3_18
MCASP0_FSR/EQEP0B_IN/MCASP0_AXR3/MCASP1_FSX/EMU2/PR1_PRU0_PRU_R30_5/PR1_PRU0_PRU_R31_5/GPIO3_19
MCASP0_AXR1/EQEP0_INDEX//MCASP1_AXR0/EMU3/PR1_PRU0_PRU_R30_6/PR1_PRU0_PRU_R31_6/GPIO3_20

LCD_PCLK/GPMC_A10//PR1_EDIO_DATA_IN4/PR1_EDIO_DATA_OUT4/PR1_PRU1_PRU_R30_10/PR1_PRU1_PRU_R31_10/GPIO2_24
LCD_VSYNC/GPMC_A8//PR1_EDIO_DATA_IN2/PR1_EDIO_DATA_OUT2/PR1_PRU1_PRU_R30_8/PR1_PRU1_PRU_R31_8/GPIO2_22
LCD_HSYNC/GPMC_A9//PR1_EDIO_DATA_IN3/PR1_EDIO_DATA_OUT3/PR1_PRU1_PRU_R30_9/PR1_PRU1_PRU_R31_9/GPIO2_23
LCD_AC_BIAS_EN/GPMC_A11//PR1_EDIO_DATA_IN5/PR1_EDIO_DATA_OUT5/PR1_PRU1_PRU_R30_11/PR1_PRU1_PRU_R31_11/GPIO2_25

ECAP0_IN_PWM0_OUT/UART3_TXD/SPI1_CS1/PR1_ECAP0_ECAP_CAPIN_APWM_O/SPI1_SCLK/MMC0_SDWP/XDMA_EVENT_INTR2/GPIO0_7

USB1_DP
USB1_DM
USB1_CE
USB1_ID
USB1_DRVVBUS/GPIO3_13
USB1_VBUS

USB0_DP
USB0_DM
USB0_CE
USB0_ID
USB0_DRVVBUS/GPIO0_18
USB0_VBUS

SPI0_SCLK/UART2_RXD/I2C2_SDA/EHRPWM0A/PR1_UART0_CTS_N/PR1_EDIO_SOF/EMU2/GPIO0_2
RMII1_REFCLK/XDMA_EVENT_INTR2/SPI1_CS0/UART5_TXD/MCASP1_AXR3/MMC0_POW/MCASP1_AHCLKX/GPIO0_29
SPI0_D0/UART2_TXD/I2C2_SCL/EHRPWM0B/PR1_UART0_RTS_N/PR1_EDIO_LATCH_IN/EMU3/GPIO0_3
MDIO_CLK/TIMER5/UART5_TXD/UART3_RTSN/MMC0_SDWP/MMC1_CLK/MMC2_CLK/GPIO0_1
SPI0_D1/MMC1_SDWP/I2C1_SDA/EHRPWM0_TRIPZONE_INPUT/PR1_UART0_RXD/PR1_EDIO_DATA_IN0/PR1_EDIO_DATA_OUT0/GPIO0_4
MDIO_DATA/TIMER6/UART5_RXD/UART3_CTSN/MMC0_SDCD/MMC1_CMD/MMC2_CMD/GPIO0_0
SPI0_CS0/MMC2_SDWP/I2C1_SCL/EHRPWM0_SYNCI_O/PR1_UART0_TXD/PR1_EDIO_DATA_IN1/PR1_EDIO_DATA_OUT1/GPIO0_5
SPI0_CS1/UART3_RXD/ECAP1_IN_PWM1_OUT/MMC0_POW/XDMA_EVENT_INTR2/MMC0_SDCD/EMU4/GPIO0_6
LCD_DATA0/GPMC_A0//EHRPWM2A//PR1_PRU1_PRU_R30_0/PR1_PRU1_PRU_R31_0/GPIO2_6
UART0_TXD/SPI1_CS1/DCAN0_RX/I2C2_SCL/ECAP1_IN_PWM1_OUT/PR1_PRU1_PRU_R30_15/PR1_PRU1_PRU_R31_15/GPIO1_11
LCD_DATA1/GPMC_A1//EHRPWM2B//PR1_PRU1_PRU_R30_1/PR1_PRU1_PRU_R31_1/GPIO2_7
UART0_RXD/SPI1_CS0/DCAN0_TX/I2C2_SDA/ECAP2_IN_PWM2_OUT/PR1_PRU1_PRU_R30_14/PR1_PRU1_PRU_R31_14/GPIO1_10
LCD_DATA2/GPMC_A2//EHRPWM2_TRIPZONE_INPUT//PR1_PRU1_PRU_R30_2/PR1_PRU1_PRU_R31_2/GPIO2_8
UART0_CTSN/UART4_RXD/DCAN1_TX/I2C1_SDA/SPI1_D0/TIMER7/PR1_EDC_SYNC0_OUT/GPIO1_8
LCD_DATA3/GPMC_A3//EHRPWM2_SYNCI_O//PR1_PRU1_PRU_R30_3/PR1_PRU1_PRU_R31_3/GPIO2_9
UART0_RTSN/UART4_TXD/DCAN1_RX/I2C1_SCL/SPI1_D1/SPI1_CS0/PR1_EDC_SYNC1_OUT/GPIO1_9
LCD_DATA4/GPMC_A4//EQEP2A_IN//PR1_PRU1_PRU_R30_4/PR1_PRU1_PRU_R31_4/GPIO2_10
LCD_DATA5/GPMC_A5//EQEP2B_IN//PR1_PRU1_PRU_R30_5/PR1_PRU1_PRU_R31_5/GPIO2_11
LCD_DATA6/GPMC_A6/PR1_EDIO_DATA_IN6/EQEP2_INDEX/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_6/PR1_PRU1_PRU_R31_6/GPIO2_12
LCD_DATA7/GPMC_A7/PR1_EDIO_DATA_IN7/EQEP2_STROBE/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_7/PR1_PRU1_PRU_R31_7/GPIO2_13
LCD_DATA8/GPMC_A12/EHRPWM1_TRIPZONE_INPUT/MCASP0_ACLKX/UART5_TXD/PR1_MII0_RXD3/UART2_CTSN/GPIO2_14
UART1_TXD/MMC2_SDWP/DCAN1_RX/I2C1_SCL//PR1_UART0_TXD/PR1_PRU0_PRU_R31_16/GPIO0_15
LCD_DATA9/GPMC_A13/EHRPWM1_SYNCI_O/MCASP0_FSX/UART5_RXD/PR1_MII0_RXD2/UART2_RTSN/GPIO2_15
UART1_RXD/MMC1_SDWP/DCAN1_TX/I2C1_SDA//PR1_UART0_RXD/PR1_PRU1_PRU_R31_16/GPIO0_14
LCD_DATA10/GPMC_A14/EHRPWM1A/MCASP0_AXR0//PR1_MII0_RXD1/UART3_CTSN/GPIO2_16
UART1_CTSN/TIMER6/DCAN0_TX/I2C2_SDA/SPI1_CS0/PR1_UART0_CTS_N/PR1_EDC_LATCH0_IN/GPIO0_12
LCD_DATA11/GPMC_A15/EHRPWM1B/MCASP0_AHCLKR/MCASP0_AXR2/PR1_MII0_RXD0/UART3_RTSN/GPIO2_17
UART1_RTSN/TIMER5/DCAN0_RX/I2C2_SCL/SPI1_CS1/PR1_UART0_RTS_N/PR1_EDC_LATCH1_IN/GPIO0_13
LCD_DATA12/GPMC_A16/EQEP1A_IN/MCASP0_ACLKR/MCASP0_AXR2/PR1_MII0_RXLINK/UART4_CTSN/GPIO0_8
LCD_DATA13/GPMC_A17/EQEP1B_IN/MCASP0_FSR/MCASP0_AXR3/PR1_MII0_RXER/UART4_RTSN/GPIO0_9
I2C0_SCL/TIMER7/UART2_RTSN/ECAP1_IN_PWM1_OUT////GPIO3_6
LCD_DATA14/GPMC_A18/EQEP1_INDEX/MCASP0_AXR1/UART5_RXD/PR1_MII_MR0_CLK/UART5_CTSN/GPIO0_10
I2C0_SDA/TIMER4/UART2_CTSN/ECAP2_IN_PWM2_OUT////GPIO3_5
LCD_DATA15/GPMC_A19/EQEP1_STROBE/MCASP0_AHCLKX/MCASP0_AXR3/PR1_MII0_RXDV/UART5_RTSN/GPIO0_11

VREFP
VREFN

AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7

GMII1_TXCLK/UART2_RXD/RGMII1_TCLK/MMC0_DAT7/MMC1_DAT0/UART1_DCDN/MCASP0_ACLKX/GPIO3_9
GMII1_TXD0/RMII1_TXD0/RGMII1_TD0/MCASP1_AXR2/MCASP1_ACLKR/EQEP0B_IN/MMC1_CLK/GPIO0_28
GMII1_TXD1/RMII1_TXD1/RGMII1_TD1/MCASP1_FSR/MCASP1_AXR1/EQEP0A_IN/MMC1_CMD/GPIO0_21
GMII1_TXD2/DCAN0_RX/RGMII1_TD2/UART4_TXD/MCASP1_AXR0/MMC2_DAT2/MCASP0_AHCLKX/GPIO0_17
GMII1_TXD3/DCAN0_TX/RGMII1_TD3/UART4_RXD/MCASP1_FSX/MMC2_DAT1/MCASP0_FSR/GPIO0_16
GMII1_TXEN/RMII1_TXEN/RGMII1_TCTL/TIMER4/MCASP1_AXR0/EQEP0_INDEX/MMC2_CMD/GPIO3_3
GMII1_CRS/RMII1_CRS_DV/SPI1_D0/I2C1_SDA/MCASP1_ACLKX/UART5_CTSN/UART2_RXD/GPIO3_1
GMII1_COL/RMII2_REFCLK/SPI1_SCLK/UART5_RXD/MCASP1_AXR2/MMC2_DAT3/MCASP0_AXR2/GPIO3_0

8
8
8
8
8
8
8

8
8
8
8
8
8
8
8

11

11
11
11
11
11

11
11
11
11

11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6
11,6

Sheet

GPIO3_20

GPIO3_19

GPIO3_21
SPI1_SCLK
SPI1_D0
SPI1_D1
SPI1_CS0

GPIO2_24
GPIO2_22
GPIO2_23
GPIO2_25

GPIO2_6
GPIO2_7
GPIO2_8
GPIO2_9
GPIO2_10
GPIO2_11
GPIO2_12
GPIO2_13
UART5_TXD
UART5_RXD
UART3_CTSN
UART3_RTSN
UART4_CTSN
UART4_RTSN
UART5_CTSN
UART5_RTSN

RMII1_REFCLK 8
8
MDIO_CLK
8
MDIO_DATA

RMII1_RXCLK
RMII1_RXD0
RMII1_RXD1
RMII1_RXD2
RMII1_RXD3
RMII1_RXERR
RMII1_RXDV

RMII1_TXCLK
RMII1_TXD0
RMII1_TXD1
RMII1_TXD2
RMII1_TXD3
RMII1_TXEN
RMII1_CRS_DV
RMII1_COL

of

11

Rev
A6A

Document Number

450-5500-001
Date: Thursday, June 28, 2012

Size

11

USB1_ID
8 USB1_DRVVBUS
USB1_VBUS

USB1_DP
USB1_DM

8
8

USB0_VBUS

USB0_DP
USB0_DM

I2C0_SCL
I2C0_SDA

9
9

UART1_TXD
UART1_RXD
I2C2_SDA
I2C2_SCL

UART0_RX
UART0_TX
UART0_RTS
UART0_CTS

2,7
2,7

11
11
11
11

10
10
10
10

11
UART2_RXD
11
UART2_TXD
11
I2C1_SDA
11
I2C1_SCL
10,11 CD/EMU4

A17
B17
B16
A16
C15

B9
A9

B6
C7
B7
A7
C8
B8
A8
C9

PMIC_POWER_EN
EXT_WAKEUP

U5B

GNDA_ADC

GNDA_ADC

0.001uf,50V

C30

AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7

VREFP_ADC
VREFN_ADC

11
11
11
11
11
11
11
2

C6
C5

0.01uf,16V

C29

C28
0.01uf,16V

R78
0,1%

2 PMIC_POWR_EN
2
WAKEUP

R77
4.75K,1%

VRTC

VDD_ADC

0.01uf,16V

C90

C80

C81

0.01uf,16V

C91

C45

C53

C82

C93

TP5

VDD_CORE

DGND

10uF,10V

C50

DGND

C95

DGND

N15
N16

E5
F5
G5
H5
J5
K5
L5

E7

N14

R15
R16

M14

VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR

VDDS_PLL_DDR

VSSA_USB

VDDA3P3V_USB1
VDDA1P8V_USB1

VSSA_USB

VDDA3P3V_USB0
VDDA1P8V_USB0

VDDS_SRAM_MPU_BB
CAP_VDD_SRAM_MPU
CAP_VBB_MPU
VDDS_SRAM_CORE_BG

CAP_VDD_SRAM_CORE
VDDS_PLL_MPU

VDD_MPU1
VDD_MPU2
VDD_MPU3
VDD_MPU4
VDD_MPU5
VDD_MPU6
VDD_MPU7
VDD_MPU_MON

VDD_CORE1
VDD_CORE2
VDD_CORE3
VDD_CORE4
VDD_CORE5
VDD_CORE6
VDD_CORE7
VDD_CORE8
VDD_CORE9
VDD_CORE10
VDD_CORE11
VDD_CORE12
VDD_CORE13
VDD_CORE14
VDD_CORE15
VDD_CORE16
VDD_CORE17
VDD_CORE18
VDD_CORE19
VDD_CORE20

U5C

AM335X_ZCZ
0.01uf,16V

C96

DGND

C86
0.01uf,16V

0.01uf,16V 0.01uf,16V

C94

VDD_1V8

D9
H15

F10
F11
F12
F13
G13
H13
J13
A2

F6
F7
G6
G7
G10
H11
J12
K6
K8
K12
L6
L7
L8
L9
M11
M13
N8
N9
N12
N13

D10
CAP_VDD_SRAM_MPU D11
CAP_VBB_MPU C10
E9

VDD_MPUON
TESTPT1
CAP_VDD_SRAM_CORE

VDD_MPU

C48

C55

C54

0.01uf,16V 0.01uf,16V

C92

C47

DGND

DGND

C46

C41

DGND

TESTOUT

VDDS_OSC

VDDS_RTC
CAP_VDD_RTC
ENZ_KALDO_1P8V

VPP
VDDS_PLL_CORE_LCD

VSSA_ADC

VDDA_ADC

VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS

VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6

VDDSHV5
VDDSHV5

VDDSHV4
VDDSHV4

VDDSHV3
VDDSHV3

VDDSHV2
VDDSHV2

VDDSHV1
VDDSHV1

A3

R11

D7
D6
B4

M5
R10

E8

D8

E6
E14
F9
K13
N6
P9
P14

E10
E11
E12
E13
F14
G14
N5
P5
P6

K14
L14

H14
J14

P12
P13

P10
P11

P7
P8

TESTPT1

TP6
TESTOUT

DGND

1uF,10V
10K,1%

R79

C64

0.01uf,16V

C58

C65

C66

0.01uf,16V

C59

C67

DGND

DGND

DGND

0.01uf,16V

C99

GNDA_ADC

FB2
2

C68

C69

DGND

VDD_PLL

GNDA_ADC

DGND

BeagleBone Processr 3 of 3

VDD_PLL

Title

DGND

C88
0.01uf,16V

FB3
2

VDD_1V8

150OHM800mA

0.01uf,16V

C79

VDD_1V8

0.01uf,16V

C78

150OHM800mA

0.01uf,16V

C77

C87
0.01uf,16V

0.01uf,16V

C76

0.01uf,16V

C98

VRTC

0.01uf,16V

C75

C97

0.01uf,16V

DGND

VDD_RTC
ENZ_KALDO_1P8V

VDD_ADC

C74

0.01uf,16V

C63

C57

C52
0.01uf,16V

C51
0.01uf,16V

0.01uf,16V 0.01uf,16V

C56

C43
0.01uf,16V

C42
0.01uf,16V

VDD_3V3A

0.01uf,16V 0.01uf,16V 0.01uf,16V0.01uf,16V0.01uf,16V 0.01uf,16V 0.01uf,16V 10uF,10V

C62

0.01uf,16V

C71

0.01uf,16V

0.01uf,16V

C70

C61

C60

Sheet

of

11

Rev
A6A

Document Number

450-5500-001
Date: Thursday, June 28, 2012

Size

10uF,10V

C89

VDD_PLL

VDD_3V3A
VDD_1V8

VDDS_DDR

DGND

0.01uf,16V

C44

10uF,10V

C40

DGND

0.01uf,16V

150OHM800mA

C39

VDD_MPU

C38

0.01uf,16V

VDD_1V8

10uF,10V

C73

0.01uf,16V

C72

0.01uf,16V

FB1
2

C35

0.01uf,16V

C49

0.01uf,16V

C34

0.01uf,16V

VDD_1V8

10uF,10V

C36

0.01uf,16V

C33

0.01uf,16V

C37

0.01uf,16V

C32
0.01uf,16V

C31

0.01uf,16V

0.01uf,16V

0.01uf,16V

0.01uf,16V

0.01uf,16V
C83
1uF,10V

VDD_CORE

0.01uf,16V

0.01uf,16V
C84
1uF,10V

0.01uf,16V
0.01uf,16V

0.01uf,16V
C85
1uF,10V

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A1
A18
F8
G8
G9
G11
G12
H6
H7
H8
H9
H10
H12
J6
J7
J8
J9
J10
J11
K7
K9
K10
K11
L10
L11
L12
L13
M6
M7
M8
M9
M10
M12
N7
N10
N11
V1
V18

VDD_3V3A

DGND

S1
B3U-1100

DGND

1uF,10V,DNI

C101

SYS_WARMRESETn

USR1
USR2
USR3

3
3
3

RESET BUTTON

USR0

10,3

DGND

R116
100K,1%

User LED's

TP10 TESTPT1

DGND

C100
4.7uF,6.3V

D2

USR0

R96
470,5%

DGND

DMC56404

Q1A

598-8170-107F

DGND

R118
100K,1%

TP12 TESTPT1
D4

USR2

R98
470,5%

DMC56404

Q2A

598-8170-107F

R119
100K,1%

DGND
DGND

Document Number

Sheet

D5

USR3

R99
470,5%

VDD_LED

TP13 TESTPT1

BeagleBone LED, Configuration and Reset

DGND

DMC56404

Q1B

598-8170-107F

D3

USR1

R97
470,5%

450-5500-001
Date: Thursday, June 28, 2012

Size

Title

DGND

R117
100K,1%

TP11 TESTPT1

FB4
150OHM800mA

SYS_5V

47k

BOOT ORDER....MMC....SPI....UART....USB......24MHZ

11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4
11,4

10k

DGND

GPIO2_6
GPIO2_7
GPIO2_8
GPIO2_9
GPIO2_10
GPIO2_11
GPIO2_12
GPIO2_13
UART5_TXD
UART5_RXD
UART3_CTSN
UART3_RTSN
UART4_CTSN
UART4_RTSN
UART5_CTSN
UART5_RTSN

Boot Configuration

SYS_BOOT0
SYS_BOOT1
SYS_BOOT2
SYS_BOOT3
SYS_BOOT4
SYS_BOOT5
SYS_BOOT6
SYS_BOOT7
SYS_BOOT8
SYS_BOOT9
SYS_BOOT10
SYS_BOOT11
SYS_BOOT12
SYS_BOOT13
SYS_BOOT14
SYS_BOOT15

47k

R80

10k

R81

R100

42.2K,1%,DNI

100K,1%

R82

R101

42.2K,1%,DNI

100K,1%

R83

R102

42.2K,1%,DNI

100K,1%

R84

R103

42.2K,1%

100K,1%,DNI

R85

R104

42.2K,1%,DNI

100K,1%

R86

R105

42.2K,1%

100K,1%,DNI

R87

R106

42.2K,1%

100K,1%,DNI

R88

R107

42.2K,1%

100K,1%,DNI

R89

R108

42.2K,1%

100K,1%,DNI

R90

R109

42.2K,1%

100K,1%,DNI

R91

R110

42.2K,1%

100K,1%,DNI

R92

R111

42.2K,1%

100K,1%,DNI

R93

R112
42.2K,1%

100K,1%,DNI

R94

R113

100K,1%,DNI

R95

42.2K,1%

100K,1%
R114
42.2K,1%,DNI

100K,1%,DNI
R115
42.2K,1%

2
1
LEDAA
LEDAC

LEDBA
LEDBC

LEDCA
LEDCC

LEDDA
LEDDC

of

11

Rev
A6A

DMC56404

Q2B

598-8170-107F

DGND

47k

10k

GRN

47k

GRN

GRN

10k
4

GRN
A

C113

C114

C115

C117

DGND

VDDS_DDR

22uF,6.3V

C116

DDR_CLK
DDR_CLKn
DDR_CKE
DDR_CSn
DDR_RASn
DDR_CASn
DDR_WEn
DDR_D[15..0]

DDR_DQS1
DDR_DQSN1
DDR_DQM1
DDR_DQSN0
DDR_DQS0
DDR_DQM0

3
3
3
3
3
3
3

0.01uf,16V
0.01uf,16V 0.01uf,16V0.01uf,16V0.01uf,16V

C112

VDDS_DDR

3
3

3
3

DGND

DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15

E3
P9
J3
N1
A3
R7
R3
E2
A2

A1
E1
M9
R1
J9

B7
A8
B3
E8
F7
F3

G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9

J8
K8
K2
L8
K7
L7
K3

VREF

VSSDL

VDDL

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

ODT

BA0
BA1
BA2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
(RFU)A13

DDR2 SDRAM

MT47H128M16RT-25E:C

VSS
VSS
VSS
VSS
VSS
RFU2
RFU1
NC1
NC2

VDD
VDD
VDD
VDD
VDD

UDQS
UDQSn
UDM
LDQSn
LDQS
LDM

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

CK
CKn
CKE
CSn
RASn
CASn
WEn

U6

J2

J7

J1

H8
B2
D2
F2
H2
A7
E7
B8
D8
F8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

K9

L2
L3
L1

M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8

DGND

R120

DGND

C118
0.01uf,16V

VDDS_DDR

DDR_VREF

0.01uf,16V

C104

DDR_A13

0.01uf,16V

C103

VDDS_DDR

DDR_BA0
DDR_BA1
DDR_BA2

DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13R 0,1%

0.01uf,16V

C106

DGND

0.01uf,16V

C105

VDDS_DDR

DDR_ODT

DDR_BA[2..0]

0.01uf,16V

C107

DDR_A[13..0]

2,4

0.01uf,16V

C108

2,4

256KX8

0.01uf,16V

C111

WP

VSS

VCC

CAT24C256W

A0
A1
A2

SCL
SDA

U7

Document Number
B

Sheet

WP
R210 10K,1%

TP2
TESTPT1

BeagleBone DDR2 Memory

0.01uf,16V

C110

DGND

1
2
3

6
5

Variable & MAC Memory

450-5500-001
Date: Thursday, June 28, 2012

Size

Title

0.01uf,16V

C109

I2C0_SCL
I2C0_SDA

of

11

DGND

C102
0.1uf,16V

VDD_3V3B

Rev
A6A

4 USB1_DRVVBUS

SYS_RESETn

30pF,50V

C131

PHYX

R144
10,1%

Y4

SYS_5V

DGND

DGND

10,1%,DNI

TXCLK

DGND

IN OUT
IN OUT
EN OUT
GND OC
PAD

U9

0,1%

TPS2051 (DGN)

2
3
4
1

DGND

30pF,50V

C132

R199

8
7
6
5
9

R200 0,1%,DNI
19

20
21
22
23
24
25
15
14

2
FB5

1
27

XTAL2

4
4
4

XTAL1/CLKIN

nRST

R148
10K,1%

VDD_3V3B

USB1_OC

USB1_DM
USB1_DP
USB1_ID

DGND

RBIAS

nINT/TXER/TXD4

LED1/REGOFF
LED2/nINTSEL

RXP
RXN

DGND

R146
0,1%

32

18
RBIAS

LED2

R145
12.1K,1%

DGND

DGND

15pF,DNI

C128

DGND

15pF,DNI

C129

DGND

R220
10K,1%

ACTIVE WHEN LINK PRESENT.

BLINKS OFF DURING ACTIVITY.
ACTIVE WHEN AT 100MB

DGND

15pF,DNI

15pF,DNI
DGND

C127

VDD_PHYA

GND

NC

VBUS

TPD4S012

ID

D-

D+

U10

DGND

C134
0.01uf,16V

SHIELD

SHIELD

P2
4 USB-A Conn. - 87520-xx1xx
1 VBUS
2 D3 D+
4 GND

nINT/RXCLK/PHYAD1

RXD3/PHYAD2

RXD2/RMIISEL

RXER/PHYAD0

CRS_DV/MODE2

RXD1/MODE1

RXD0/MODE0

VDD_3V3B

PHYAD0 MODE2 MODE1

R219
10K,1%

DGND

DGND

GRN_C

R128 470,5%

MODE0 RMISEL PHYAD1 PHYAD0

DGND

YEL_C

470,5%

R16

NOTE: There are two different configuration

connectors used for P10. The difference is
that the TX and RX pairs are swapped.
Either of these can be used as the
AUTO_MDIX feature in the LAN8710A will
compensate by swapping the TX and Rx on
the LAN8710.

USB HOST CONNECTOR

DGND

USB1_VBUS

This mode pin setting connects to the wrong pin

on the LAN8710. It should go to pin 15 instead.
For this revision R122 is not installed as it does
not do what it is intended to do. This removes the
pullup from pin 14. This will be addressed on the
next revision of the board.

RXP
RXN

31
30

3
2

TXP
TXN

C126

C125
1uF,10V

29
28

C124
470pF
50V
5%

C121
4.7uF,6.3V

DGND

DGND

C120
0.1uf,16V
DGND

TXP
TXN

PHY_VDDCR

DGND

C119
0.1uf,16V

QFN32_5X5MM_EP3P3MM

U15
TXCLK
TXEN
LAN8710A
TXD0
TXD1
TXD2
TXD3
COL/CRS_DV/MODE2
CRS

MDIO
MDC
RXD3/PHYAD2
RXD2/RMIISEL
RXD1/MODE1
RXD0/MODE0
RXDV
RXCLK/PHYAD1
RXER/RXD4/PHYAD0

DGND

5
RCLKIN

RXD3/PHYAD2
RXD2/RMIISEL
RXD1/MODE1
RXD0/MODE0
RXDV
REFCLKO
RXER/PHYAD0

16
17
8
9
10
11
26
7
13

C123
0.1uf,16V

DGND

COL/CRS_DV/MODE2
CRS_DV/MODE2

PHY_XTAL1
1M,1%,DNI
PHY_XTAL2

25.000MHz
XTAL2_5X3P2_SMD

R140

100,1%
100,1%

100,1%

R206

R207
R139

100,1%
100,1%
100,1%
100,1%
100,1%
100,1%
100,1%

R205
R153
R132
R135
R208
R136
R137

R209

+
R147
10K,1%
C133
100uF,6.3V

DGND

RMII1_TXCLK
RMII1_TXEN
RMII1_TXD0
RMII1_TXD1
RMII1_TXD2
RMII1_TXD3
RMII1_COL
RMII1_CRS_DV

4
4
4
4
4
4
4
4

11,3

MDIO_DATA
MDIO_CLK
RMII1_RXD3
RMII1_RXD2
RMII1_RXD1
RMII1_RXD0
RMII1_RXDV
RMII1_RXCLK
RMII1_RXERR

RMII1_REFCLK

4
4
4
4
4
4
4
4
4

DGND

C122
0.1uf,16V

1
150OHM800mA

R129
49.9,1%

R130
49.9,1%

R133
49.9,1%

VDD_PHYA

R134
49.9,1%

VDD_3V3B

R131

1.5K,5%

12
VDDIO

6
VDDCR

R124

VDD2A
VDD1A
GND_EP
33

R126
10K,1%,DNI
R125
10K,1%

R123
10K,1%

R5

10K,1%R122
R127
10K,1%,DNI

R211

10K,1%,DNI

10K,1%
R198

10K,1%,DNI
R212
10K,1%

10K,1%,DNI

R213
R214
10K,1%

10K,1%,DNI

R215
10K,1%,DNI
R216
10K,1%

13
14

R142
0,1%

DGND

.1,0805

R138

ESD_RING

DGND

Document Number

Sheet

BeagleBone Ethernet and USB Host

VDD_PHYA

TCT_RCT

450-5500-001
Date: Thursday, June 28, 2012

Size

Title

DGND

NC
GND

YELC SHD1
YELA SHD2
GRNC
GRNA

TCT
TD+
TDRD+
RDRCT

WE_7499010211A

11
12
10
9

0.022uF,10V

C130

GRNA

YELA

5
3
6
1
2
4

P10

ETHERNET
CONNECTOR

of

11

Rev
A6A

DGND

18pF,50V

C144

1M,1%,DNI

R160

18pF,50V

C137

DGND

HS_IND

XTALOUT

0,1%

24MHz

XTALIN

rsvd3

TESTPT1

TP8

Y5

R161

DGND

C136
0.1uf,16V
DGND

RESETn

R156
100K,1%

VDD_3V3B

DGND

R151
100K,1%

VBUS_DET

R149
100K,1%

29

15

16

23

24

17

12

18

USBDP_UP
USBDM_UP

USB2412_QFN28

PRTPWR1

USBDM_DN1

PLLFILT

CRFILT

VDD33
VDD33
VDDPLLREF/VDD33

VSS(FLAG)

VSS

HS_IND

XTALOUT

RBIAS

VDD33
VDDCRREF/VDD33

XTALIN/CLKIN

TEST

Common

RESET

NON_REM1
SUSP_IND/NON_REM0

NC

PRTPWR2

USBDM_DN2

NON_REM[0:1]/nc

OCS2

DownstreamUSBDP_DN2
2

OCS1

Downstream 1 USBDP_DN1

VBUS_DET

Upstream

U11

R157

CRFILT

DGND

DGND

C145

PLLFILT

C139

DGND

10

10

10

DGND

C143
0.1uf,16V

DGND

C142
0.1uf,16V

DGND

0.1uf,16V

DGND

USB0_DM

USB0_DP

FT_VBUS

FT_DM

C140

0.1uf,16V,DNI

C146

C141
0.1uf,16V

DGND

0.1uf,16V 4.7uF,6.3V

C138

VDD_3V3B

HUB_BIAS

NON_REM1
NON_REM2

USB_DC

FT_DP

12.1K,1%

USBDP_UP
USBDM_DN

USB0_VBUS_PWR

0.1uf,16V,DNI

25

4
20
27

14
10

26

13
19

11

28

22
21

5
4
3
2
1
P3

G1
ID
D+
DVB

DGND

TESTPT1

TP7

R155
10K,1%,DNI

R159
100K,1%

DGND

R158
10K,1%

R154
10K,1%,DNI

R152
4.75K,1%

SYS_5V

4
SN74LVC2G07DCK

U16B

USB PC
CONNECTOR

mini USB-B

VDD_3V3B

USB_DC

9
G4

G2

8
G5
G3
6

BeagleBone USB Concentrator

Document Number
B

450-5500-001
Date: Thursday, June 28, 2012

Size

Title

USB0_VBUS

Sheet

of

11

Rev
A6A

DGND

VDD_3V3B

C152

CS
SK
DIN
DOUT

5
4
3
1

R187

DGND

0.1uf,16V

C162

R167

50

XTOUT

Y6
12.000MHz
50ppm

XTIN

12.1K,1% FT_REF

2.2K,1%
DGND

13

63
62
61

14

7
8

49

VDD_1V8FT

TEST

EECS
EECLK
EEDATA

RESET

OSC0

OSCIN

USBDM
USBDP

REF

VREGOUT

VREGIN

U12

0.1uf,16V

C158

FT_RESETn
2.2K,1%

R188

F_EECS
F_EESK
F_EEDATA

R175

C155 27pF,50V

10K,1%

C164

VDD_FTREGIN

0.1uf,16V 0.1uf,16V

C163

2 FB8

2 FB7
VDD_FTVPHY

2 FB6 VDD_FTVPLL

C153 27pF,50V

FT_DM
FT_DP

10K,1%
10K,1%

DGND

DGND

93LC56B_SOT23-6

GND

VCC

R174
R173
U13

9
9

DGND

4.7uF,6.3V

1
150OHM800mA
1
150OHM800mA

1
150OHM800mA

0.1uf,16V

C161

AGND
10

DGND

VDD_3V3B

DGND

GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
1
5
11
15
25
35
47
51

36

60

48
52
53
54
55
57
58
59

38
39
40
41
43
44
45
46

26
27
28
29
30
32
33
34

16
17
18
19
21
22
23
24

0.1uf,16V

C151

FT2232LQFN64

SUSPEND

PWREN

BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7

BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7

ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7

ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7

0.1uf,16V

C150

DGND

F_ADBUS7

F_ADBUS6

F_ADBUS0
F_ADBUS1
F_ADBUS2
F_ADBUS3
F_ADBUS4

FT_VBUS

R181
10K,1%,DNI

VDD_3V3B

DGND

VDD_3V3B

0.1uf,16V

C148

C147 0.1uf,16V

R171

R170

R164
R165
R166
R168
R169

4
4
4
4

0,1%

0,1%

0,1%
0,1%
0,1%
0,1%
0,1%

4.75K,1%

4.75K,1%

R176

R182
R183
R185

VDD_3V3B

100,1%,DNI
0,DNI
0,DNI

R178
R180

DGND

DGND

0.1uf,16V

C156

DGND

2
4
6
8
10
12
14
16
18
20

DGND

EMU3R

TDIS

R184

R177

Document Number
B

3
JTAG_EMU1

0,DNI

Sheet

DGND

10 of 11

R186
4.75K,1%

CLKOUT2

DGND

R179
4.75K,1%

VDD_3V3B

3
3
3
3
3

Rev
A6A

11,3

SYS_WARMRESETn 3,6

JTAG_EMU0

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRSTn

0,DNI

BeagleBone Serial and JTAG

CTI JTAG,DNI

TMS
TRSTn
TDI
TDIS
TVDD
NC
TDO
GND
TCKRTN
GND
TCK
GND
EMU0
EMU1
SRST
GND
EMU2
EMU3
EMU4
GND

P7

6
FT_SRESETB
0,1%
SN74LVC2G07DCK
R163

U16A

450-5500-001
Date: Thursday, June 28, 2012

Size

Title

1
3
5
7
0,DNI
RTCK 9
11
0,DNI
TCK
13
15
EMU_RSTn
17
EMU2R
19
EMU4R

DGND

0,1% 1

0.1uf,16V

VDD_3V3B

OPTIONAL JTAG

VDD_3V3B

REMU_RSTn

0.01uf,16V

C154

DGND

C149

FT_SRESETn R172

SN74LVC2G00DCU

U14B

0.1uf,16V

VDD_3V3B

FT_VBUS 6

DGND

C157

VDD_3V3B

R162

FT_SRESET

3XDMA_EVENT_INTR0
11,4
CD/EMU4

UART0_TX
UART0_RX
UART0_CTS
UART0_RTS

8
4

VDD_3V3B

4
9
VPHY
VPLL

12
37
64
VCOREC
VCOREB
VCOREA

20
31
42
56
VCCIOA
VCCIOB
VCCIOB
VCCIOD

5
2

F_EEDOUT

3
3

3
3

10,4

CD/EMU4

MMC0_DAT0
MMC0_DAT1

MMC0_CLKO

MMC0_DAT2
MMC0_DAT3
MMC0_CMD

GPIO1_6
GPIO1_2
TIMER4
TIMER5
GPIO1_13
EHRPWM2B
GPIO1_15
GPIO0_27
EHRPWM2A
GPIO1_30
GPIO1_4
GPIO1_0
GPIO2_22
GPIO2_23
UART5_CTSN
UART4_RTSN
UART4_CTSN
UART5_TXD
GPIO2_12
GPIO2_10
GPIO2_8
GPIO2_6

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46

DGND

R191
10K,1%

R190

10K,1%

DGND

R192
10K,1%

VDD_3V3A

MOLEX 502570-001

DAT2
GND
CD/DAT3
CD
CMD
GND1
VDD
GND2
CLOCK
GND3
VSS
GND4
DAT0
DAT1 microSD

DGND

C160
0.1uf,16V

GPIO1_7
GPIO1_3
TIMER7
TIMER6
GPIO1_12
GPIO0_26
GPIO1_14
GPIO2_1
GPIO1_31
GPIO1_5
GPIO1_1
GPIO1_29
GPIO2_24
GPIO2_25
UART5_RTSN
UART3_RTSN
UART3_CTSN
UART5_RXD
GPIO2_13
GPIO2_11
GPIO2_9
GPIO2_7

9
10
11
12
13
14

3
3
3
3
3
3
3
3
3
3
3
3
4
4
4,6
4,6
4,6
4,6
4,6
4,6
4,6
4,6

uSD CONNECTOR

1
2
3
4
5
6
7
8

P4

10uF,10V

C159

EXPANSION HEADER

DGND

FEMALE HEADER 2x23

P8

R193
10K,1%

3
3
3
3
3
3
3
3
3
3
3
3
4
4
4,6
4,6
4,6
4,6
4,6
4,6
4,6
4,6

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45

R194
10K,1%

R195
10K,1%

SD_CD

DGND

2
3
3
3
4
4
4
3
4
4
4
4
4
4
4
4
10,3

0,1%

R197

R196

P9

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46

FEMALE HEADER 2x23

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
GNDA_ADC
DGND

10K,1%

VDD_3V3B

4.7uF,6.3V

C6

VDD_3V3A

DGND

SYS_VOLT

8
2
5
9
4

U8

FB

OUT
NC2
NC3

1
6
7

TPS73701DRBR

IN
NC1
EN
PAD
GND

0.1uf,16V

52.3K,1%

Document Number

Sheet

11 of 11

Rev
A6A

BeagleBone Expansion Headers, SD/MMC.and LDO

DGND

C166

R150

VDD_3V3EXP

4
4
4
4

450-5500-001
Date: Thursday, June 28, 2012

Size

Title

30.1K,1%

R189

3V3EXP_FB

AIN5
AIN3
AIN1
GPIO0_7

DGND
VDD_3V3EXP
VDD_5V
SYS_5V
3,8
SYS_RESETn
3
GPIO1_28
3
EHRPWM1A
3
EHRPWM1B
4
I2C1_SDA
4
I2C2_SDA
4
UART2_RXD
4
UART1_TXD
4
UART1_RXD
4
SPI1_CS0
4
SPI1_D1
VDD_ADC

EXPANSION HEADER

DGND

DGND
VDD_3V3EXP
VDD_5V
SYS_5V
PWR_BUT
UART4_RXD
UART4_TXD
GPIO1_16
I2C1_SCL
I2C2_SCL
UART2_TXD
GPIO1_17
GPIO3_21
GPIO3_19
SPI1_D0
SPI1_SCLK
AIN4
AIN6
AIN2
AIN0
CLKOUT2