DSP Lab Manual DSK Technical Programming With C, MATLAB Programs 2008 B.Tech ECE IV-I JNTU Hyd V1.9

DEPARTM ENT
OF
ELECTRONICS & COMM UNICATION ENGINEERING (ECE)
DIGITAL SIGNAL PROCESSING (DSP)
LAB MANUAL
TH
B.TECH (ECE) IV YR IST SEM
2008 Private Engineering College, Affiliated to JNTU, Hyderabad 1/52

DSP Lab Manual
Digital signal processing is an area of science and engineering

that these developed rapidly over 30 years. This rapid development
is result of significant advances in digital computer technology and
integrated circuit fabrication .the rapid development in IC
technology (VLSI) of electronics circuit as spurred the
development of power full, smaller, faster and chipper digital
computer hardware. Hence it is possible to construct highly
sophisticated digital system capable to perform complex digital
signal processing function.
In this laboratory we present the fundamentals of digital
signals, systems, modern digital processing algorithms and
applications for student in electronics and communication
engineering
In this Laboratory we are instructed to study the importance

of Digital signal processing applications in day-to-day life and the
concepts required to develop these applications. The basic concepts
can be implemented by writing high level, medium level, and
assembly level programs using the MATLAB, CCS and TMS 320C
6713 processor instructions. Hence you are requested to study the
architecture of the processor along with the instruction set and the
assembler directives used for the programming. We will also
introduce ourselves to the MATLAB tool and implement some of
the basic C, MATLAB programs to illustrate the concepts of
Digital signal processing.
You are requested to

1. Write the assembly code for the required operation
2. Download the program to the processor using the
DSPIK software (CCS – IDE)
3. Execute the program and record the results for
various inputs.

INDEX
1. Architecture of DSP chips-TMS 320C 6713 DSP Processor
2. Linear convolution
3. Circular convolution
4. FIR Filter (LP/HP) Using Windowing technique
a. Rectangular window
b. Triangular window
c. Kaiser window
5. IIR Filter(LP/HP) on DSP processors
6. N-point FFT algorithm
7. Power Spectral Density of a sinusoidal signals
8. FFT of 1-D signal plot
9. MATLAB program to generate sum of sinusoidal signals
10. MATLAB program to find frequency response of
analog(LP/HP)
10. Offline processing Examples using 6713 processor
• Addition
• Multiplication
• Shifting
• Logical Operation
• Circular Buffering
11. Real time examples using 6713 processor
• Sampling
• Linear convolution
• Circular convolution
• FIR filter design
• IIR filter design
• Fast Fourier transform
12. List of Experiments in B.Tech Lab
13. MATLAB Examples
• Computation using matrices
• Magnitude and phase of transformed signal using FFT
• Convolution and Correlation of signals
• Frequency response of a filter
• Filter design using windowing
• IIR Butterworth filters
• IIR Chebyshev filters

CHAPTER-I 1. INTRODUCTION TO DSP PROCESSORS
A signal can be defined as a function that conveys information, generally about the
state or behavior of a physical system. There are two basic types of signals viz Analog
(continuous time signals which are defined along a continuum of times) and Digital
(discrete-time).
Remarkably, under reasonable constraints, a continuous time signal can be
adequately represented by samples, obtaining discrete time signals. Thus digital signal
processing is an ideal choice for anyone who needs the performance advantage of digital
manipulation along with today’s analog reality.
Hence a processor which is designed to perform the special operations(digital

manipulations) on the digital signal within very less time can be called as a Digital signal
processor. The difference between a DSP processor, conventional microprocessor and a
microcontroller are listed below.
Microprocessor or General Purpose Processor such as Intel xx86 or Motorola 680xx

family
Contains - only CPU
-No RAM
-No ROM
-No I/O ports
-No Timer
Microcontroller such as 8051 family
Contains - CPU
- RAM
- ROM
-I/O ports
- Timer &
- Interrupt circuitry
Some Micro Controllers also contain A/D, D/A and Flash Memory
DSP Processors such as Texas instruments and Analog Devices

Contains - CPU
- RAM
-ROM
- I/O ports
- Timer
Optimized for – fast arithmetic
- Extended precision
- Dual operand fetch
- Zero overhead loop
- Circular buffering

The basic features of a DSP Processor are
Feature Use
Fast-Multiply accumulate Most DSP algorithms, including
filtering, transforms, etc. are
multiplication- intensive
Multiple – access memory Many data-intensive DSP operations
architecture require reading a program instruction
and multiple data items during each
instruction cycle for best performance
Specialized addressing modes Efficient handling of data arrays and
first-in, first-out buffers in memory
Specialized program control Efficient control of loops for many
iterative DSP algorithms. Fast interrupt
handling for frequent I/O operations.
On-chip peripherals and I/O On-chip peripherals like A/D converters
interfaces allow for small low cost system designs.
Similarly I/O interfaces tailored for
common peripherals allow clean
interfaces to off-chip I/O devices.

2. ARCHITECTURE OF 6713 DSP PROCESSOR
This chapter provides an overview of the architectural structure of the TMS320C67xx

DSP, which comprises the central processing unit (CPU), memory, and on-chip
peripherals. The C67xE DSPs use an advanced modified Harvard architecture that
maximizes processing power with eight buses. Separate program and data spaces allow
simultaneous access to program instructions and data, providing a high degree of
parallelism. For example, three reads and one write can be performed in a single cycle.
Instructions with parallel store and application-specific instructions fully utilize this
architecture. In addition, data can be transferred between data and program spaces. Such
Parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations
that can all be performed in a single machine cycle. Also, the C67xx DSP includes the
control mechanisms to manage interrupts, repeated operations, and function calling.
Fig 2 – 1 BLOCK DIAGRAM OF TMS 320VC 6713

Bus Structure
The C67xx DSP architecture is built around eight major 16-bit buses (four program/data
buses and four address buses):
_ The program bus (PB) carries the instruction code and immediate operands from
program memory.
_ Three data buses (CB, DB, and EB) interconnect to various elements, such as the CPU,
data address generation logic, program address generation logic, on-chip peripherals, and
data memory.
_ The CB and DB carry the operands that are read from data memory.
_ The EB carries the data to be written to memory.
_ Four address buses (PAB, CAB, DAB, and EAB) carry the addresses needed for
instruction execution.
The C67xx DSP can generate up to two data-memory addresses per cycle using the two
auxiliary register arithmetic units (ARAU0 and ARAU1). The PB can carry data operands
stored in program space (for instance, a coefficient table) to the multiplier and adder for
multiply/accumulate operations or to a destination in data space for data move instructions
(MVPD and READA). This capability, in conjunction with the feature of dual-operand
read, supports the execution of single-cycle, 3-operand instructions such as the FIRS
instruction. The C67xx DSP also has an on-chip bidirectional bus for accessing on-chip
peripherals. This bus is connected to DB and EB through the bus exchanger in the CPU
interface. Accesses that use this bus can require two or more cycles for reads and writes,
depending on the peripheral’s structure.
Central Processing Unit (CPU)
The CPU is common to all C67xE devices. The C67x CPU contains:
_ 40-bit arithmetic logic unit (ALU)

_ Two 40-bit accumulators
_ Barrel shifter
_ 17 × 17-bit multiplier
_ 40-bit adder
_ Compare, select, and store unit (CSSU)
_ Data address generation unit
_ Program address generation unit
Arithmetic Logic Unit (ALU)
The C67x DSP performs 2s-complement arithmetic with a 40-bit arithmetic logic unit
(ALU) and two 40-bit accumulators (accumulators A and B). The ALU can also perform
Boolean operations. The ALU uses these inputs:
_ 16-bit immediate value

_ 16-bit word from data memory
_ 16-bit value in the temporary register, T
_ Two 16-bit words from data memory
_ 32-bit word from data memory
_ 40-bit word from either accumulator
The ALU can also function as two 16-bit ALUs and perform two 16-bit operations
simultaneously.
Fig 2 – 2 ALU UNIT
Accumulators
Accumulators A and B store the output from the ALU or the multiplier/adder block. They
can also provide a second input to the ALU; accumulator A can be an input to the
multiplier/adder. Each accumulator is divided into three parts:
_ Guard bits (bits 39–32)
_ High-order word (bits 31–16)
_ Low-order word (bits 15–0)
Instructions are provided for storing the guard bits, for storing the high- and the low-order
accumulator words in data memory, and for transferring 32-bit accumulator words in or
out of data memory. Also, either of the accumulators can be used as temporary storage for
the other.
Barrel Shifter
The C67x DSP barrel shifter has a 40-bit input connected to the accumulators or to data
memory (using CB or DB), and a 40-bit output connected to the ALU or to data memory
(using EB). The barrel shifter can produce a left shift of 0 to 31 bits and a right shift of 0
to 16 bits on the input data. The shift requirements are defined in the shift count field of
the instruction, the shift count field (ASM) of status register ST1, or in temporary register
T (when it is designated as a shift count register).The barrel shifter and the exponent
encoder normalize the values in an accumulator in a single cycle. The LSBs of the output
are filled with 0s, and the MSBs can be either zero filled or sign extended, depending on

the state of the sign-extension mode bit (SXM) in ST1. Additional shift capabilities enable
the processor to perform numerical scaling, bit extraction, extended arithmetic,
and overflow prevention operations.
Multiplier/Adder Unit
The multiplier/adder unit performs 17 _ 17-bit 2s-complement multiplication with a 40-bit
addition in a single instruction cycle. The multiplier/adder block consists of several
elements: a multiplier, an adder, signed/unsigned input control logic, fractional control
logic, a zero detector, a rounder (2s complement), overflow/saturation logic, and a 16-bit
temporary storage register (T). The multiplier has two inputs: one input is selected from T,
a data-memory operand, or accumulator A; the other is selected from program memory,
data memory, accumulator A, or an immediate value. The fast, on-chip multiplier allows
the C54x DSP to perform operations efficiently such as convolution, correlation, and
filtering. In addition, the multiplier and ALU together execute multiply/accumulate
(MAC) computations and ALU operations in parallel in a single instruction cycle. This
function is used in determining the Euclidian distance and in implementing symmetrical
and LMS filters, which are required for complex DSP algorithms. See section 4.5,
Multiplier/Adder Unit, on page 4-19, for more details about the multiplier/adder unit.
Fig 2 – 3 MULTIPLIER/ADDER UNIT
Fig 2 – 3 MULTIPLIER/ADDER UNIT
These are the some of the important parts of the processor and you are instructed to go
through the detailed architecture once which helps you in developing the optimized code
for the required application.

CHAPTER-II DSP PROGRAMS IN C
1. Linear Convolution
AIM
To verify Linear Convolution.
EQUIPMENTS
TMS 320C6713 Kit.

RS232 Serial Cable
Power Cord
THEORY
Convolution is a formal mathematical operation, just as multiplication, addition, and

integration. Addition takes two numbers and produces a third number, while convolution
takes two signals and produces a third signal. Convolution is used in the mathematics of
many fields, such as probability and statistics. In linear systems, convolution is used to
describe the relationship between three signals of interest: the input signal, the impulse
response, and the output signal.
In this equation, x1(k), x2 (n-k) and y(n) represent the input to and output from the system
at time n. Here we could see that one of the input is shifted in time by a value everytime it
is multiplied with the other input signal. Linear Convolution is quite often used as a
method of implementing filters of various types.
ALGORITHM
Step 1 Declare three buffers namely Input buffer, Temporary Buffer, Output Buffer.
Step 2 Get the input from the CODEC, store it in Input buffer and transfer it to the first
location of the
Temporary buffer.
Step 3 Make the Temporary buffer to point to the last location.
Step 4 Multiply the temporary buffer with the coefficients in the data memory and
accumulate it with
the previous output.
Step 5 Store the output in the output buffer.
Step 6 Repeat the steps from 2 to 5.
PROGRAM
#include<stdio.h>
int x[15],h[15],y[15];
main()
{
int i,j,m,n;
printf("\n enter value for m");
scanf("%d",&m);
printf("\n enter value for n");
scanf("%d",&n);
printf("Enter values for i/p\n");
for(i=0;i<m;i++)
scanf("%d",&x[i]);
printf("Enter Values for n \n");
for(i=0;i<n;i++)
scanf("%d",&h[i]);
for(i=m;i<=m+n-1;i++)
x[i]=0;
for(i=n;i<=m+n-1;i++)
h[i]=0;
for(i=0;i<m+n-1;i++)
{
y[i]=0;
for(j=0;j<=i;j++)
{
y[i]=y[i]+(x[j]*h[i-j]);
}
}
for(i=0;i<m+n-1;i++)
printf("\n The Value of output y[%d]=%d",i,y[i]);
}
Result:
enter value for m4
enter value for n4

Enter values for i/p
1234
Enter Values for n
1234
The Value of output y[0]=1


2. Circular Convolution
AIM
To verify Circular Convolution.
EQUIPMENTS
SANDS TEXAS 5416 Kit.

RS232 Serial Cable
Power Cord
THEORY
Circular convolution is another way of finding the convolution sum of two input signals. It
resembles the linear convolution, except that the sample values of one of the input signals
is folded and right shifted before the convolution sum is found. Also note that circular
convolution could also be found by taking the DFT of the two input signals and finding
the product of the two frequency domain signals. The Inverse DFT of the product would
give the output of the signal in the time domain which is the circular convolution output.
The two input signals could have been of varying sample lengths. But we take the DFT of
higher point, which ever signals levels to. For eg. If one of the signal is of length 256 and
the other spans 51 samples, then we could only take 256 point DFT. So the output of
IDFT would be containing 256 samples instead of 306 samples, which follows N1+N2 – 1
where N1 & N2 are the lengths 256 and 51 respectively of the two inputs. Thus the output
which should have been 306 samples long is fitted into 256 samples. The
256 points end up being a distorted version of the correct signal. This process is called
circular convolution.
PROGRAM:
/* prg to implement circular convolution */
#include<stdio.h>
int m,n,x[30],h[30],y[30],i,j,temp[30],k,x2[30],a[30];
void main()
{
printf(" enter the length of the first sequence\n");
scanf("%d",&m);
printf(" enter the length of the second sequence\n");
scanf("%d",&n);
printf(" enter the first sequence\n");
for(i=0;i<m;i++)
scanf("%d",&x[i]);
printf(" enter the second sequence\n");
for(j=0;j<n;j++)
scanf("%d",&h[j]);

if(m-n!=0) /*If length of both sequences are not equal*/
{
if(m>n) /* Pad the smaller sequence with
zero*/
{
for(i=n;i<m;i++)
h[i]=0;
n=m;
}
for(i=m;i<n;i++)
x[i]=0;
m=n;
}
y[0]=0;
a[0]=h[0];
for(j=1;j<n;j++) /*folding h(n) to h(-n)*/
a[j]=h[n-j];
/*Circular convolution*/
for(i=0;i<n;i++)
y[0]+=x[i]*a[i];
for(k=1;k<n;k++)
{
y[k]=0;
/*circular shift*/
for(j=1;j<n;j++)
x2[j]=a[j-1];
x2[0]=a[n-1];
for(i=0;i<n;i++)
{
a[i]=x2[i];
y[k]+=x[i]*x2[i];
}
}
/*displaying the result*/

printf(" the circular convolution is\n");
for(i=0;i<n;i++)
printf("%d \t",y[i]);
}

OUTPUT:-
Enter the first sequence

5
6
7
Enter the second sequence
7
8
5
4
OUTPUT ;- the circular convolution is
94 110 122 106
Model Graph:-

3. CORRELATION
AIM: To convert Circular Convolution
EQUIPMENTS
TEXAS TMS 320 C6713 Kit.

RS232 Serial Cable
Power Cord
THEORY:
Correlation is measures of the degree to which two sequences are similar .There are two
types of Correlation 1. Cross correlation 2.Auto correlation
Cross Correlation:- given two real valued sequences x1(n) of finite energy , the cross
correlation of x1(n) and x2(n) is a sequence rxy (1) defined as
rxy( 1 )=
#include<stdio.h>
int m,n,X[30],RXY[30],Y[30],i,j,temp[30],k,X2[30],a[30];
void main()
{
printf("enter the length of the first sequence\n");
scanf("%d",&m);
printf("enter the length of the second sequence\n");
scanf("%d",&n);
printf("enter the first sequence\n");
for(i=0;i<m;i++)
scanf("%d",&X[i]);
printf("enter the secound sequence\n");
for(j=0;j<n;j++)
scanf("%d",&Y[j]);
for(i=n;i<m+n-1;i++)
X[i]=0;
for(i=m;i<n+m-1;i++)
Y[i]=0;
if(m>n)
a=m;
else
a=n
for(l=0;l<a;l++)
{
RXY[l]=0;
for(n=0;n<a;n++)

{
RXY[l]+=X[n+l]*X2[n];
}
}
printf("the correlation is\n");
for(i=0;i<n;i++)
printf("%d\t",RXY[i]);
}
enter the length of the first sequence

5
enter the length of the second sequence
5
enter the first sequence
5,5,5,5,5,5
enter the secound sequence
5,5,5,5,5,5
the correlation is
125,100,75,50,25
OUTPUT:

4. DISCRETE FOURIER TRANSFORM
AIM
To find the Fast Fourier Transform for the realtime samples.
HARDWARE REQUIREMENTS
TMS320C6713 DSK.
USB Cable.
Power Cord
5V Adapter
1. THEORY
The Transform Domain Technique involves the transformation of the time domain
signal into a frequency domain one. The available methods of implementing the
transformation are
• Discrete Fourier Transform

• Fast Fourier Transform
M nk
− j 2π
X ( k ) = ∑ x ( n) e n
;0 < k < N − 1 (4)
k =0
N −1 nk
− j 2π
x (k ) = ∑ x(n) W n
;0 < k < N − 1 (5)
n =0
PROGRAM:
#include<stdio.h>
#include<math.h>
#define pi 3.1415
#define PTS 64
float X[PTS];
main()
{
float xr[PTS],xi[PTS],k,n,N=PTS;
float XR[PTS],XI[PTS];
for(i=0;i<PTS-1;++)
{
xr[i]=sin(2*pi*10*i/64.0);
xi[i]=0;
}
for (k=0;k<N;k++)
{
Xr[k]=0;
Xi[k]=0;
for (n=0; <N; n++)
{
XR[k]+=(xr[n]*cos(2*pi*k*n/N))+(xi[n]*sin(2*pi*k*n/N));
XI[k]+=(xi[n]*sin(2*pi*k*n/N))-(xr[n]*cos(2*pi*k*n/N));
}
X[k]=sqrt((XR[k]*XR[k])+(XI[k]*XI[k]));
printf("%f\n",X[k]);
}
5. FAST FOURIER TRANSFORM

AIM
To find the Fast Fourier Transform for the realtime samples.
HARDWARE REQUIREMENTS
TMS320C6713 DSK.
USB Cable.
Power Cord
5V Adapter
THEORY
The Fast Fourier Transform is useful to map the time-domain sequence into a
continuous function of a frequency variable. The FFT of a sequence {x(n)} of length
N is given by a complex-valued sequence X(k).
M nk
− j 2π
X ( k ) = ∑ x ( n) e n
;0 < k < N − 1
k =0
The above equation is the mathematical representation of the DFT. As the number of
computations involved in transforming a N point time domain signal into its
corresponding frequency domain signal was found to be N2 complex multiplications,
an alternative algorithm involving lesser number of computations is opted.
When the sequence x(n) is divided into 2 sequences and the DFT performed
separately, the resulting number of computations would be N2/2
(i.e.)
N2 N2
2−1 2−1
x(k ) = ∑ x(2n) WN2 nk + ∑ x(2n + 1) WN( 2 n+1) k (6)
n =0 n =0
Consider x(2n) be the even sample sequences and x(2n+1) be the odd sample sequence
derived form x(n).
N2
2 −1
∑ x ( 2n)
n =0
WN2 nk
would result in (7)

N2
2 −1
(N/2)2multiplication’s
∑ x(2n + 1)
n =0
WN( 2 n+1) k (8)
an other (N/2)2 multiplication's finally resulting in (N/2)2 + (N/2)2
N2 N2 N2
= + = Computatio ns
4 4 2
Further solving Eg. (2)

N2 N
2−1 2−1 k
x( k ) = ∑ x(2n) WN2 nk + ∑ x( 2n + 1) WN( 2 nk ) W (9)
N
n =0 n =0
N N
2 −1 k 2−1
= ∑ x(2n) WN2 nk + W ∑ x(2n + 1) WN( 2 nk ) (10)
N
n =0 n =0
Dividing the sequence x(2n) into further 2 odd and even sequences would reduce the
computations.
WN  is the twiddle factor

− j 2π
=e n
 − j 2π 
  nk
W nk
N =e  n 
 N  N
K+  K+ 
W 
N
2 
= WN W 
N
2 
(11)
− j 2π − j 2π n
k n 2
=e n
e
− j 2π
k
= WNk e n
= WNk (cos π − j sin π )
 N
K+ 
=W 
N
2 
= WNk (−1)
 N
K+ 
=W  2 
= WNk (12)
N
Employing this equation, we deduce

N2 N
2−1 2−1
x(k ) = ∑ x(2n) WN2 nk + ∑ x(2n + 1) WN( 2 nk ) (13)
n =0 n=0
N
2−1 K N
N
x(k + ) = ∑ x(2n) WN2 nk − W ∑ x (2n + 1) 2−1 WN( 2 nk ) (14)
2 n =0 N
The time burden created by this large number of computations limits the usefulness of
DFT in many applications. Tremendous efforts devoted to develop more efficient
ways of computing DFT resulted in the above explained Fast Fourier Transform
algorithm. This mathematical shortcut reduces the number of calculations the DFT
requires drastically. The above mentioned radix-2 decimation in time FFT is employed
for domain transformation.
Dividing the DFT into smaller DFTs is the basis of the FFT. A radix-2 FFT divides the
DFT into two smaller DFTs, each of which is divided into smaller DFTs and so on,
resulting in a combination of two-point DFTs. The Decimation -In-Time (DIT) FFT
divides the input (time) sequence into two groups, one of even samples and the other
of odd samples. N/2 point DFT are performed on the these sub-sequences and their
outputs are combined to form the N point DFT.
FIG. 3A.1
The above shown mathematical representation forms the basis of N point FFT and is
called the Butterfly Structure.

STAGE – I STAGE - II
STAGE – III
FIG. 3A.2 – 8 POINT DIT

ALGORITHM
Step 1 sample the input (N) of any desired frequency. Convert it to fixed-point
format and scale the input to avoid overflow during manipulation.
Step 2 Declare four buffers namely real input, real exponent, imaginary exponent
and imaginary input.
Step 3 Declare three counters for stage, group and butterfly.
Step 4 Implement the Fast Fourier Transform for the input signal.
Step 5 Store the output (Real and Imaginary) in the output buffer.
Step 6 Decrement the counter of butterfly. Repeat from the Step 4 until the counter
reaches zero.
Step 7 If the butterfly counter is zero, modify the exponent value.
Step 8 Repeat from the Step 4 until the group counter reaches zero.
Step 9 If the group counter is zero, multiply the butterfly value by two and divide
the group value by two.
Step 10 Repeat from the Step 4 until the stage counter reaches zero.
Step 11 Transmit the FFT output through line out port.
PROGRAM: -
#include <math.h>
#define PTS 128 //# of points for FFT
#define PI 3.14159265358979
typedef struct {float real,imag;} COMPLEX;
void FFT(COMPLEX *Y, int n); //FFT prototype
float iobuffer[PTS]; //as input and output buffer
float x1[PTS],x[PTS]; //intermediate buffer
short i; //general purpose index variable
short buffercount = 0; //number of new samples in iobuffer
short flag = 0; //set to 1 by ISR when iobuffer full
float y[128];
COMPLEX w[PTS]; //twiddle constants stored in w
COMPLEX samples[PTS]; //primary working buffer
main()
{
float j,sum=0.0 ;
int n,k,i,a;
for (i = 0 ; i<PTS ; i++) // set up twiddle constants in w
{
w[i].real = cos(2*PI*i/(PTS*2.0)); //Re component of twiddle constants
w[i].imag =-sin(2*PI*i/(PTS*2.0)); /*Im component of twiddle constants*/
}

/****************InputSignalX(n)***************************************/
for(i=0,j=0;i<PTS;i++)
{ x[i] = sin(2*PI*5*i/PTS); // Signal x(Fs)=sin(2*pi*f*i/Fs);
samples[i].real=0.0;
samples[i].imag=0.0;
}
/********************** FFT of R(t) *****************************/
for (i = 0 ; i < PTS ; i++) //swap buffers

{
samples[i].real=iobuffer[i]; //buffer with new data
}
for (i = 0 ; i < PTS ; i++)

samples[i].imag = 0.0; //imag components = 0
FFT(samples,PTS); //call function FFT.c
/******************** PSD *******************************************/
for (i = 0 ; i < PTS ; i++) //compute magnitude

{
x1[i] = sqrt(samples[i].real*samples[i].real
+ samples[i].imag*samples[i].imag);
}
} //end of main
void FFT(COMPLEX *Y, int N) //input sample array, # of points

{
COMPLEX temp1,temp2; //temporary storage variables
int i,j,k; //loop counter variables
int upper_leg, lower_leg; //index of upper/lower butterfly leg
int leg_diff; //difference between upper/lower leg
int num_stages = 0; //number of FFT stages (iterations)
int index, step; //index/step through twiddle constant
i = 1; //log(base2) of N points= # of stages
do
{
num_stages +=1;
i = i*2;
}while (i!=N);
leg_diff = N/2; //difference between upper&lower legs
step = (PTS*2)/N; //step between values in twiddle.h // 512
for (i = 0;i < num_stages; i++) //for N-point FFT

{
index = 0;
for (j = 0; j < leg_diff; j++)
{
for (upper_leg = j; upper_leg < N; upper_leg += (2*leg_diff))
{
lower_leg = upper_leg+leg_diff;
temp1.real = (Y[upper_leg]).real + (Y[lower_leg]).real;
temp1.imag = (Y[upper_leg]).imag + (Y[lower_leg]).imag;
temp2.real = (Y[upper_leg]).real - (Y[lower_leg]).real;
temp2.imag = (Y[upper_leg]).imag - (Y[lower_leg]).imag;
(Y[lower_leg]).real = temp2.real*(w[index]).real
-temp2.imag*(w[index]).imag;
(Y[lower_leg]).imag = temp2.real*(w[index]).imag
+temp2.imag*(w[index]).real;
(Y[upper_leg]).real = temp1.real;
(Y[upper_leg]).imag = temp1.imag;
}
index += step;
}
leg_diff = leg_diff/2;
step *= 2;
}
j = 0;
for (i = 1; i < (N-1); i++) //bit reversal for resequencing data
{
k = N/2;
while (k <= j)
{
j = j - k;
k = k/2;
}
j = j + k;
if (i<j)
{
temp1.real = (Y[j]).real;
temp1.imag = (Y[j]).imag;
(Y[j]).real = (Y[i]).real;
(Y[j]).imag = (Y[i]).imag;
(Y[i]).real = temp1.real;
(Y[i]).imag = temp1.imag;
}
}
return;
}

OUTPUT:
DFT or FFT spectrum of sinusoidal signal f= 10 Hz
6.FIR FILTER
AIM: -
To design and implement a low pass FIR filter using windowing technique.
APPARATUS: -
1. TMS320C5416 DSK.
2. USB Cable.
3. Power Cord
4. 5V Adapter.
THEORY: -
A Finite Impulse Response (FIR) filter is a discrete linear time-invariant system whose
output is based on the weighted summation of a finite number of past inputs. An FIR
transversal filter structure can be obtained directly from the equation for discrete-time
convolution.
N −1
y ( n) = ∑ x ( k ) h( n − k ) 0 < n < N − 1 (1)
k =0
In this equation, x(k) and y(n) represent the input to and output from the filter at time
n. h(n-k) is the transversal filter coefficients at time n. These coefficients are
generated by using FDS (Filter Design Software or Digital filter design package).
Windows:
#include <stdio.h>
#include <math.h>
#define pi 3.1415
int N,n;
float h[64];
void main()
{
printf("enter the number of samples\n");
scanf("%d",&N);
for(n=0;n<(N-1);n++)
{
h[n]=0.0;
h[n]= 0.42+0.5*cos(2*pi*n/(N-1))+0.08*cos(4*pi*n/(N-1));
printf("h[%d]=%f\n",n,h[n]);
}
RESULT:

PROGRAM: -
#include <stdio.h>
#include <math.h>
#define pi 3.1415
int N,n;
float h[64];
void main()
{
printf("enter the number of samples\n");
scanf("%d",&N);
for(n=0;n<(N-1);n++)
{
h[n]=0.0;
h[n]=1-(4*n/(float)(n-1)) ;
printf("h[%d]=%f\n",n,h[n]);
}

Wave form:-

7. IIR FILTER
AIM: -
To design and implement a low pass IIR filter using windowing technique.
APPARATUS: -
1. TMS320C5416 DSK.
2. USB Cable.
3. Power Cord
4. 5V Adapter.
THEORY: -
The IIR filter can realize both the poles and zeroes of a system because it has a
rational transfer function, described by polynomials in z in both the numerator and the
denominator:
M
∑b
k =0
k z −k
H ( z) N (2)
∑a
k =1
k Z −k
The difference equation for such a system is described by the following:

M N
y ( n) = ∑ bk x ( n − k ) + ∑a k y (n − k ) (3)
k =0 k =1
M and N are order of the two polynomials

bk and ak are the filter coefficients. These filter coefficients are generated using FDS
(Filter Design software or Digital Filter design package).
LPF:
#include<stdio.h>
#include<math.h>
#define pi 3.1415
float Xmod[64],Xr[64],Xi[64];
float xr[64],xi[64],h[100],y[64];
int n,k,i,N,w,wc;
void main()
{
for(k=0;k<=63;k++)
{
xr[k]=sin((2*pi*10*k)/64)+sin((2*pi*50*k)/64);
xi[k]=0.0;
}
for(k=0;k<=63;k++)
{
Xr[k]=0;
Xi[k]=0;
for(n=0;n<=63;n++)
{
Xr[k]+=xr[n]*cos((2*pi*k*n)/64.0)+xi[n]*sin((2*pi*k*n)/64.0);
Xi[k]+=xi[n]*cos((2*pi*k*n)/64.0)-xr[n]*sin((2*pi*k*n)/64.0);
}
Xmod[k]=sqrt(Xr[k]*Xr[k]+Xi[k]*Xi[k]);
}
printf("enter the order of the filter\n");
scanf("%d",&w);
printf("enter the cutoff frequency\n");
scanf("%d",&wc);
for(w=0;w<100;w++)
{
h[w]=1/sqrt(1+pow(w/(float)wc,2*N));
printf("h[%d]=%f\n",w,h[w]);
}
for(k=0;k<=63;k++)
{
y[k]=Xmod[k]*h[k];
printf("y[%d]=%f\n",k,y[k]);
}}

INPUT OUTPUT

HPF:
PROGRAM: -
#include<stdio.h>
#include<math.h>
#define pi 3.1415
float Xmod[64],Xr[64],Xi[64];
float xr[64],xi[64],h[100],y[64];
int n,k,i,N,w,wc;
void main()
{
for(k=0;k<=63;k++)
{
xr[k]=sin((2*pi*10*k)/64)+sin((2*pi*50*k)/64);
xi[k]=0.0;
}
for(k=0;k<=63;k++)
{
Xr[k]=0;
Xi[k]=0;
for(n=0;n<=63;n++)
Xr[k]+=xr[n]*cos((2*pi*k*n)/64.0)+xi[n]*sin((2*pi*k*n)/64.0);
Xi[k]+=xi[n]*cos((2*pi*k*n)/64.0)-xr[n]*sin((2*pi*k*n)/64.0);
}
Xmod[k]=sqrt(Xr[k]*Xr[k]+Xi[k]*Xi[k]);
}
printf("enter the order of the filter\n");
scanf("%d",&w);
printf("enter the cutoff frequency\n");
scanf("%d",&wc);
for(w=0;w<100;w++)
{
h[w]=1/sqrt(1+pow(wc/(float)w,2*N));
printf("h[%d]=%f\n",w,h[w]);
}
for(k=0;k<=63;k++)
{
y[k]=Xmod[k]*h[k];
printf("y[%d]=%f\n",k,y[k]);
}}

INPUT OUTPUT
RESULT: -
Thus the IIR Low pass filter with cut off frequency 12Hz has been designed.
8. POWER SPECTRAL DENSITY

AIM: -
To design and implement a low pass FIR filter using windowing technique.
APPARATUS: -
1. TMS320C6713 DSK.
2. USB Cable.
3. Power Cord
4. 5V Adapter.
PROGRAM: -
#include <math.h>
#define PTS 128 //# of points for FFT
#define PI 3.14159265358979
typedef struct {float real,imag;} COMPLEX;
void FFT(COMPLEX *Y, int n); //FFT prototype
float iobuffer[PTS]; //as input and output buffer
float x1[PTS],x[PTS]; //intermediate buffer
short i; //general purpose index variable
short buffercount = 0; //number of new samples in iobuffer
short flag = 0; //set to 1 by ISR when iobuffer full
float y[128];
COMPLEX w[PTS]; //twiddle constants stored in w
COMPLEX samples[PTS]; //primary working buffer
main()
{
float j,sum=0.0 ;
int n,k,i,a;
for (i = 0 ; i<PTS ; i++) // set up twiddle constants in w
{
w[i].real = cos(2*PI*i/(PTS*2.0)); //Re component of twiddle constants
w[i].imag =-sin(2*PI*i/(PTS*2.0)); /*Im component of twiddle constants*/
}
/****************Input Signal X(n)

********************************************************/
for(i=0,j=0;i<PTS;i++)
{ x[i] = sin(2*PI*5*i/PTS); // Signal x(Fs)=sin(2*pi*f*i/Fs);
samples[i].real=0.0;
samples[i].imag=0.0;
}

/********************Auto Correlation of X(n)=R(t)
*********************************/
for(n=0;n<PTS;n++)
{
sum=0;
for(k=0;k<PTS-n;k++)
{
sum=sum+(x[k]*x[n+k]); // Auto Correlation R(t)
}
iobuffer[n] = sum;
}
/********************** FFT of R(t) *****************************/
for (i = 0 ; i < PTS ; i++) //swap buffers

{
samples[i].real=iobuffer[i]; //buffer with new data
}
for (i = 0 ; i < PTS ; i++)

samples[i].imag = 0.0; //imag components = 0
FFT(samples,PTS); //call function FFT.c
/******************** PSD *******************************************/
for (i = 0 ; i < PTS ; i++) //compute magnitude

{
x1[i] = sqrt(samples[i].real*samples[i].real
+ samples[i].imag*samples[i].imag);
}
} //end of main
void FFT(COMPLEX *Y, int N) //input sample array, # of points

{
COMPLEX temp1,temp2; //temporary storage variables
int i,j,k; //loop counter variables
int upper_leg, lower_leg; //index of upper/lower butterfly leg
int leg_diff; //difference between upper/lower leg
int num_stages = 0; //number of FFT stages (iterations)
int index, step; //index/step through twiddle constant
i = 1; //log(base2) of N points= # of stages
do
{
num_stages +=1;
i = i*2;
}while (i!=N);
leg_diff = N/2; //difference between upper&lower legs
step = (PTS*2)/N; //step between values in twiddle.h // 512
for (i = 0;i < num_stages; i++) //for N-point FFT
{
index = 0;
for (j = 0; j < leg_diff; j++)
{
for (upper_leg = j; upper_leg < N; upper_leg += (2*leg_diff))
{
lower_leg = upper_leg+leg_diff;
temp1.real = (Y[upper_leg]).real + (Y[lower_leg]).real;
temp1.imag = (Y[upper_leg]).imag + (Y[lower_leg]).imag;
temp2.real = (Y[upper_leg]).real - (Y[lower_leg]).real;
temp2.imag = (Y[upper_leg]).imag - (Y[lower_leg]).imag;
(Y[lower_leg]).real = temp2.real*(w[index]).real
-temp2.imag*(w[index]).imag;
(Y[lower_leg]).imag = temp2.real*(w[index]).imag
+temp2.imag*(w[index]).real;
(Y[upper_leg]).real = temp1.real;
(Y[upper_leg]).imag = temp1.imag;
}
index += step;
}
leg_diff = leg_diff/2;
step *= 2;
}
j = 0;
for (i = 1; i < (N-1); i++) //bit reversal for resequencing data
{
k = N/2;
while (k <= j)
{
j = j - k;
k = k/2;
}
j = j + k;
if (i<j)
{
temp1.real = (Y[j]).real;
temp1.imag = (Y[j]).imag;
(Y[j]).real = (Y[i]).real;
(Y[j]).imag = (Y[i]).imag;
(Y[i]).real = temp1.real;
(Y[i]).imag = temp1.imag;
}
}
return;
}

CHAPTER-III
OFFLINE PROCESSING EXAMPLES
The term offline processing indicates that the programs which you are designing are like
simulation i.e. you are not using the real time inputs and outputs also you are seeing in the
processor registers or memory only.
1. ADDITION
Aim: - To perform addition operation on two numbers residing in memory.
Apparatus: - TMS 320C 5416 processor
Program: -
.include “5416_IV.asm”
.data
.word 0003h, 0004h // input numbers //
.text
.include “intvect.asm”
Begin STM #1000h,AR1 // memory location of first number //

STM #1001h,AR2 // memory location of second number //
STM #1500h,AR3 // memory location of result //
LD *AR1,A
LD *AR2,B
ADD A,0,B
STL B,*AR3
.end
Result: - The result of addition operation can be recorded from the memory location.

2. MULTIPLICATION
Aim: - To perform multiplication operation on two numbers residing in memory.
Program: -
.data
.word 0005h, 0002h // input numbers //
.text

STM #1500h,AR3 // memory location of result //
MPY *AR1,*AR2,B
STL B,*AR3
.end
Result: - The result of multiplication operation can be recorded from the memory
location.

3. SHIFTING
Aim: - To perform left shift and right shift operation on a number residing in memory.
Program: -
.data
.word 0003h, // input number //
.text

STM #1600h,AR2 // memory location of left shifted number //
STM #1500h,AR3 // memory location of right shifted number //
LD *AR5,A
LD *AR5,B
SFTA A,-1
SFTA B,1
STL A,*AR2
STL B,*AR3
.end
Result: - Shifting the number left by one bit is equivalent to multiplying number by 2
Shifting the number left by one bit is equivalent to dividing number by 2

4. LOGICAL OPERATIONS
Aim: - To perform logical operations on two numbers residing in memory.
Program: -
.data
.word 0003h,0007h // input numbers //
.text

STM #1500h,AR3 // memory location of result due to AND operation //
STM #1600h,AR2 // memory location of result due to OR operation //
STM #1700h,AR1 // memory location of result due to NEGATE operation //
LD *AR5,A
LD *AR4,B
AND A,0,A
OR B,0,B
STL A,*AR3
STL B,*AR2
LD *AR5,A
NEG A
STL A,*AR1
.end
Result: - The logical operations are performed on a number.

5. CIRCULAR BUFFERING
Aim: - To reveal the concept of circular buffering.
Program: -
.data
.word 1h,2h,3h,4h,5h // array of numbers //
.text
Begin STM #1000h,AR5 // data memory address //

STM #2000h,AR6 // output buffer //
STM #4h,BK // loading the size of circular buffer to BK register //
STM #20h,BRC
RPTB L1
LD *AR5+%,0,A
STL A,0,*AR6+
L1 NOP
.end
Result: - The concept of circular buffering is observed

CHAPTER-IV
REAL TIME EXAMPLES
1. SAMPLING
AIM: -
To study the concept of sampling continuous signal with a sampling frequency of
48KHz and reconstruct the same.
APPARATUS: -
1. TMS320C5416 DSK.
2. USB Cable.
3. Power Cord
4. 5V Adapter.
THEORY: -
Sampling is a process by which a continuous-time signal is converted into a discrete-
time signal.
Let x(t) be a continuous time varying signal. The signal x(t) is sampled at regular
interval of time with sampling period T. The sampled signal x(nT) is given by
x(nT) = x(t) | t = nT = x(nT), -∞ < n < ∞
The continuous time signal x(t) is multiplied by the sampling function s(t) which is a
series of impulses. The resultant signal is a discrete time signal x(n).
x(n) = x(t) s(t) | t = nT, -∞ < n < ∞
x(T) x(nT)
T T
T 3T 5T 7T 9T 11T 13T 15T
Continuous Time Signal
nT Discrete Time Signal
nT
PROGRAM: -
;Sampling program
;Starting address : 1000h
;DSPIK output : 1600h
.include "5416_IV.asm"
.data
.text
start RSBX INTM

LD #022Bh,0,A
STLM A,PMST
;------------------------Serial Port Initializations-------------------------

;--------------------------McBSP0 Initializations----------------------------
SSBX INTM
STM SPCR1, McBSP0_SPSA ;SPCR1 reset
STM #0090h,McBSP0_SPSD
NOP
NOP
STM SPCR2,McBSP0_SPSA ;SPCR2 reset

STM PCR,McBSP0_SPSA ;PCR

STM #0A00h,McBSP0_SPSD
STM RCR1,McBSP0_SPSA ;RCR1

STM #00A0h,McBSP0_SPSD ;32 BITS WORDSIZE

STM XCR1,McBSP0_SPSA ;XCR1


STM SRGR1,McBSP0_SPSA ;SRGR1

STM #0017h,McBSP0_SPSD ;--17

STM #303Fh,McBSP0_SPSD
STM MCR1,McBSP0_SPSA ;MCR1


STM RCERB,McBSP0_SPSA ;RCERB

STM RCERA,McBSP0_SPSA ;RCERA

STM XCERB,McBSP0_SPSA ;XCERB


STM XCERA,McBSP0_SPSA ;XCERA
STM SPCR1,McBSP0_SPSA
STM #0091h,McBSP0_SPSD ;Take 'em out of reset
NOP
NOP
;--------------------------McBSP2 Initializations------------------------------

NOP
NOP

STM PCR,McBSP2_SPSA ;PCR






STM #0005h,McBSP2_SPSD ;--5

STM #303Bh,McBSP2_SPSD


STM RCERB,McBSP2_SPSA ;RCERB

STM RCERA,McBSP2_SPSA ;RCERA

STM XCERB,McBSP2_SPSA ;XCERB
STM XCERA,McBSP2_SPSA ;XCERA

STM #0091h,McBSP2_SPSD ;Take 'em out of reset
NOP
NOP
;--------------------End of Serial Ports Initializations-----------------------
RSBX INTM
LD #02Fh,0,A
STLM A,IMR
STM #0h,McBSP0_DXR1
STM #0h,McBSP0_DXR2
STM #0007h,GPIOCR
STM #0003h,GPIOSR
STM #SPCR2,McBSP2_SPSA
STM #00E1h,McBSP2_SPSD ;Mclk
NOP
STM #0007h,GPIOSR
STM #SPCR2,McBSP0_SPSA
STM #00E1h,McBSP0_SPSD ;Sclk & Fs
;----------------------------------------------------------------------------
STM #128,BK
STM #1600h,AR1
SSBX SXM
WAIT NOP
NOP
NOP
B WAIT
RESULT: -
Thus the continuous time signal is sampled at 48 KHz and the original signal is
reconstructed.

CHAPTER-V
MATLAB EXAMPLES
1. Computation using matrices
AIM:- To perform some arithmetic operations using matrices.
THEORY: - ‘MATLAB ‘itself means that matrix laboratory. To compute matrix

multiplications, addition, inverse of the matrix etc of any order can be obtained
easily.
PROGRAM: -
A= [ 1 2 3; 4 5 6; 7 8 9 ];
B= [ 2 3 4; 5 4 7; 1 1 1 ];
C= A * B
D= A’
D1=D+2
E= INV (A)
F= A(3,1:3)
G= A(1:3;1 )
H= G.*G
SUM (H)
RESULT: - Basic arithmetic operations on matrices were observed using

MATLAB.

2. Magnitude and Phase
AIM:- To compute Magnitude and Phase of transformed signal using FFT.
THEORY: - Fast Fourier Transform algorithms are faster algorithms to

compute DFT. Magnitude and Phase plots can be observed for the Fourier
transformed signal. Cestral analysis is special case of frequency domain
techniques.
PROGRAM: -
Fs = 1000;
T = 1/ Fs;
t = 0:T:1;
y = sin ( 2 * pi * 200 * t ); // generates sine wave of 200Hz //
plot(y)
z = fft(y,1024); // gets 1024 point fft for y //
N = ( 0 :1023 )’ * Fs / 1024;
z1 = abs(z);
plot( N, z1)
title( ‘ FFT Plot ‘ )
z2 = angle (z);
plot( N, z2 )
title( ‘ Phase Plot ‘)
RESULT: - Magnitude and Phase plots were observed and plotted.

3. Convolution and Correlation
AIM:- To find convolution and correlation of signals
THEORY: - If input is given to any system, output from the system is nothing
but convolution of input time signal and the system impulse response.
Convolution in time domain is same as multiplication in frequency domain.
Correlation is measurement of similarity. Cross correlation gives the similarity
between two different signals whereas autocorrelation gives the similarity of
the signal when the same signal was delayed. Fourier transform of
autocorrelation is power spectral density of the signal (PSD)
PROGRAM: -
x = [ 1 1 -1 1 -1 -1 ];
h = [ -1 -1 1 -1 -1 -1 ];
y = conv( x, h )
cr = xcorr ( x , h )
plot ( cr )
title ( ‘ Plot of Cross correlation ‘ )
ylabel( ‘ Magnitude ‘ )
xlabel( ‘ Lag ‘)
ar = xcorr(x)
plot ( ar )
RESULT: - Convolution and Correlation plots were observed and plotted.

4. Frequency Response of Filter
AIM:- To find frequency response of filter for specified coefficients.
THEORY: - Filter with coefficients are given. The frequency – magnitude plot
gives the frequency response.
PROGRAM: -
b = [ 0.0995 0.1989 0.0995 ];

a = [ 1 -0.9316 0.3294 ];
[ h w ] = freqz ( b, a, 100 );
y = abs(h);
i = freqz( b, a, 100, 200 )
plot(i)
semilogx(w, y)
RESULT: - Frequency response of specified filter is plotted.

5. FIR Filter Design
AIM:- To design FIR digital filters.
THEORY: - FIR – filter is a finite impulse response filter. Order of the filter
should be specified. Infinite response is truncated to get finite impulse
response. placing a window of finite length does this. Types of windows
available are Rectangular, Barlett, Hamming, Hanning, Blackmann window
etc. This FIR filter is an all zero filter.
PROGRAM: -
n = 20;
fp = 200;
fq = 300;
fs = 1000;
fn = 2 * fp / fs;
window = Blackman ( n+1 );
b= fir1 ( n, fn , window ) // low pass filter //
[ h w ] = freqz( b, 1, 128 );
plot( w/pi , abs(h) )
RESULT: - A LPF is designed using Blackman window.

6. IIR Butter worth Filter Design
AIM:- To design IIR Butterworth digital filters.
THEORY: - IIR filters can be expanded as infinite impulse response filters. In

designing IIR filters, cutoff frequencies of the filters should be mentioned. The
order of the filter can be estimated using butter worth polynomial. That’s why
the filters are named as butter worth filters. Filter coefficients can be found and
the response can be plotted.
PROGRAM: -
fs = 1000;
wpn = 2 * wp / fs;
wqn = 2 * wq / fs;
[ n wn ] = buttord( wpn, wqn, rp, sp )
[ b a ] = butter( n, wn )
[ h w ] = freqz( b, a, 128);
plot( (w/pi) * ( fs/2 ), abs(h) )
RESULT: - A Butterworth LPF is designed and response is plotted.

7. IIR Chebyshev Filter Design
AIM:- To design IIR Chebyshev digital filters.
THEORY: - IIR filters can be expanded as infinite impulse response filters. In

designing IIR filters, cutoff frequencies of the filters should be mentioned. The
order of the filter can be estimated using Chebyshev polynomial with the help
of cutoff frequencies and the gain at that frequencies. That’s why the filters are
named as Chebyshev filters. Filter coefficients can be found and the response
can be plotted.
PROGRAM: -
wp = 200;
wq = 300;
rp = 2;
sp = 40;
fs = 1000;
wpn = 2 * wp / fs;
wqn = 2 *wq / fs ;
[ n wn ] = cheb1ord(wpn, wqn, rp, sp )
[ b a ] =cheby1(n, rp, wn );
[ h w ] = freqz(b, a, 128 );
plot( w/pi, abs(h) )
RESULT: - A Chebyshev LPF is designed and response is plotted.

DSP Lab Manual DSK Technical Programming With C, MATLAB Programs 2008 B.Tech ECE IV-I JNTU Hyd V1.9

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

DSP Lab Manual DSK Technical Programming With C, MATLAB Programs 2008 B.Tech ECE IV-I JNTU Hyd V1.9

Caricato da

Copyright:

Formati disponibili

DEPARTM ENT

ELECTRONICS & COMM UNICATION ENGINEERING (ECE)

DIGITAL SIGNAL PROCESSING (DSP)

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 1/52

Digital signal processing is an area of science and engineering

In this Laboratory we are instructed to study the importance

You are requested to

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 2/52

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 3/52

Hence a processor which is designed to perform the special operations(digital

Microprocessor or General Purpose Processor such as Intel xx86 or Motorola 680xx

DSP Processors such as Texas instruments and Analog Devices

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 4/52

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 5/52

This chapter provides an overview of the architectural structure of the TMS320C67xx

Fig 2 – 1 BLOCK DIAGRAM OF TMS 320VC 6713

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 6/52

Central Processing Unit (CPU)

_ 40-bit arithmetic logic unit (ALU)

Arithmetic Logic Unit (ALU)

_ 16-bit immediate value

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 8/52

Fig 2 – 3 MULTIPLIER/ADDER UNIT

Fig 2 – 3 MULTIPLIER/ADDER UNIT

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 9/52

TMS 320C6713 Kit.

Convolution is a formal mathematical operation, just as multiplication, addition, and

enter value for n4

The Value of output y[0]=1

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 11/52

SANDS TEXAS 5416 Kit.

/* prg to implement circular convolution */

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 12/52

/*displaying the result*/

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 13/52

Enter the first sequence

OUTPUT ;- the circular convolution is

94 110 122 106

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 14/52

AIM: To convert Circular Convolution

TEXAS TMS 320 C6713 Kit.

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 15/52

enter the length of the first sequence

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 16/52

• Discrete Fourier Transform

5. FAST FOURIER TRANSFORM

would result in (7)

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 18/52

an other (N/2)2 multiplication's finally resulting in (N/2)2 + (N/2)2

Further solving Eg. (2)

WN  is the twiddle factor

= WNk (cos π − j sin π )

Employing this equation, we deduce

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 19/52

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 20/52

FIG. 3A.2 – 8 POINT DIT

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 21/52

2008 Private Engineering College, Affiliated to JNTU, Hyderabad 22/52

/********************** FFT of R(t) *****************************/

for (i = 0 ; i < PTS ; i++) //swap buffers

for (i = 0 ; i < PTS ; i++)

FFT(samples,PTS); //call function FFT.c

/******************** PSD *******************************************/

/displaying the result/

/ FFT of R(t) *******/

/ PSD ***********************/

/ FFT of R(t) *******/

/ PSD ***********************/