EC2354 -VLSI DESIGN

Syllabus
UNIT I CMOS TECHNOLOGY A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non ideal IV effects, DC transfer characteristics - CMOS technologies, Layout design Rules, CMOS process enhancements, Technology related CAD issues, Manufacturing issues UNIT II CIRCUIT CHARACTERIZATION AND SIMULATION Delay estimation, Logical effort and Transistor sizing, Power dissipation, Interconnect, Design margin, Reliability, Scaling- SPICE tutorial, Device models, Device characterization, Circuit characterization, Interconnect simulation

UNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN Circuit families Low power logic design comparison of circuit families Sequencing static circuits, circuit design of latches and flip flops, Static sequencing element methodology- sequencing dynamic circuits synchronizers

Syllabus Contd.,
UNIT IV CMOS TESTING Need for testing- Testers, Text fixtures and test programs- Logic verification- Silicon debug principles- Manufacturing test Design for testability Boundary scan UNIT V SPECIFICATION USING VERILOG HDL Basic concepts- identifiers- gate primitives, gate delays, operators, timing controls, procedural assignments conditional statements, Data flow and RTL, structural gate level switch level modeling, Design hierarchies, Behavioral and RTL modeling, Test benches, Structural gate level description of decoder, equality detector, comparator, priority encoder, half adder, full adder, Ripple carry adder, D latch and D flip flop.

References
TEXTBOOKS:

Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, 2005 Uyemura J.P: Introduction to VLSI circuits and systems, Wiley 2002. Samir Palnitkar; Verilog HDL - Guide to Digital design and synthesis, III edition, Pearson Education, 2003
REFERENCES:

D.A Pucknell & K.Eshraghian Basic VLSI Design, Third edition, PHI, 2003 Wayne Wolf, Modern VLSI design, Pearson Education, 2003 M.J.S.Smith: Application specific integrated circuits, Pearson Education, 1997 J.Bhasker: Verilog HDL primer, BS publication,2001 Ciletti Advanced Digital Design with the Verilog HDL, Prentice Hall of India, 2003

WHAT IS VLSI

WHY VLSI

VLSI
VLSI stands for "Very Large Scale Integration". This is the field which involves packing more and more logic devices into smaller and smaller areas.

Evolution of ICs

Vacuum tubes

ULSI Ultra large scale integration more than thousands of gates in a single package.

Many other factors grow exponentially Ex: clock frequency, processor performance

ADVANTAGES OF VLSI DESIGN

The most important message here is that the logic complexity per chip has been (and still is) increasing exponentially. The monolithic integration of a large number of functions on a single chip usually provides:

Less area/volume and therefore, compactness

Less power consumption Less testing requirements at system level

Higher reliability, mainly due to improved on-chip interconnects

Higher speed, due to significantly reduced interconnection length

Significant cost savings

VLSI Design Flow

Design Specification
specifications describe abstractly the functionality, interface and overall architecture of the digital circuit to be designed. to describe the circuit in terms of its behavior.

Behavioral Description and RTL Description

The design at the behavioral level is to be elaborated in terms of known and acknowledge functional blocks.

Written with Language)

HDLs(Hardware

Description

Behavioral converted to Register Transfer Level(RTL) description.

Functional Verification and Testing

to check whether all the functions are carried out as expected and rectify them. All such activities are carried out by the simulation tool.

The tool also has an editor to carry out any corrections to the source code.
Simulation involves testing the design for all its functions, functional sequences, timing constraints and specifications

Logic Synthesis
The hardware realization is carried out by a synthesis tool. Logic synthesis tools convert the RTL description to a gate-level netlist.

A gate-level netlist is a description of the circuit in terms of gates and connections between them. Logic synthesis tool ensure that the gate level netlist meets timing, area and power specifications.

Physical Design

FPGA-Field Programmable Gate Array

System Partitioning

The

design is partitioned into convenient compartments or functional blocks.

The main objective of system partitioning is to minimize the number of external connections between the functional blocks.

Floor Planning
Calculate the sizes of all the functional blocks and assign them locations. The main objective is to keep the highly connected blocks physically close to each other.

Blocks with I/O pins are kept close to the periphery; those which interact frequently or through a large number of interconnections are kept close together, and so on.

Placement
Assign the interconnect areas and the location of all the logic cells within the flexible blocks Minimize all the critical net delays. Minimize power dissipation. Minimize cross talk between signals. Minimize the total estimated interconnect length. Meet the timing requirements for critical nets. Minimize the interconnect congestion

Routing
routing step determines the channels to be used for each interconnect Minimize total interconnect length and area. Minimize the number of layer changes that the connections have to make. Minimize the delay of critical paths

Post layout Simulation & Verification

The performance specifications like silicon area, power consumed, path delays, etc., can be computed. Equivalent circuit can be extracted at the component level and performance analysis carried out. This constitutes verification

the final stage called

Design flow -summary

Design Specification Describes abstractly functionality, interface & overall architecture of digital circuit. Behavioral Description Design in terms of functionality, performance compliance to standards, & other high level issues. Written with HDLs(Hardware Description Language) RTL Description (HDL) Behavioral converted to Register Transfer Level(RTL) description. Logic synthesis / Timing verification Converts RTL to gate level net list. Gate level net list Describes circuits in terms of gates & connections between them. Logical verification & testing ensures gate level net list meets timing, area & power specifications. Floor planning ,Automatic place & Route, Physical Layout Automatic place & route which creates layout. Layout verification ,Implementation Layout verification & fabrication in to chip.

FPGA Modern Design Methodology

always mu mble mu Synthesis gates, gates, gates,

mble
blah blah Synthesizable Verilog

Place and Route LE 1 LE 2

*

Logic Elements in FPGA Chip Bushnell:Digital Systems Design Bushnell: Digital Systems Lecture 7 Design Lecture 7

HDL (Hardware Description Language)

PALASM,ABEL & CUPL

PALASM (from PAL assembler) language was used to express boolean equations . The PALASM compiler was written in FORTRAN IV on an IBM 370/168. The Advanced Boolean Expression Language (ABEL) is a Hardware description language and an associated set of design tools for programming PLDs. -It was created in 1983 by Data I/O Corporation, in Redmond, Washington. -ABEL includes both concurrent equation and truth table logic formats as well as a sequential state machine description format. Logical Devices, Inc. released the Universal Compiler for Programmable Logic (CUPL), which runs under MSDOS on the IBM PC.

HDL (Hardware Description Language)

All modern digital designs start with a designer writing a hardware description of the IC (using HDL or) in Verilog/VHDL. A Verilog or VHDL program essentially describes the hardware (logic gates, Flip-Flops, counters etc) and the interconnect of the circuit blocks and the functionality. VHDL stands for "VHSIC Hardware Definition Language", where VHSIC stands for "Very High Speed Integrated Circuit". VHDL & VerilogHDL is an IEEE standard(it reduces confusion and makes interfaces between tools, companies, and products easier).

What is Verilog?
Hardware Description Language (HDL) Developed in 1984

Standard: IEEE 1364, Dec 1995

Verilog was created by Phil Moore in 1983-4 at
Gateway Design Automation.

The syntax is deliberately close to that of C.

History Of Verilog HDL

MAJOR FEATURES
Built in primitive gates AND,OR,NAND etc.. Allows flexibility for creating user defined primitives (UDP) Built in Switch level modeling primitive gates PMOS,NMOS,CMOS etc.. Four different styles Or abstraction level Gate level uses primitive gates(AND,OR,NAND ) Switch level uses pMOS, nMOS, CMOS Dataflow uses assignment (LHS = RHS) Behavioral uses 2 structural procedural statement always &

Basic Limitation of Verilog

Description of digital systems only

Abstraction Levels in Verilog

Behavioral

RTL
Gate Layout (VLSI)

Our focus

Design Methodologies
1.Top down Design 2. Bottom up Design Top down : Define top level block, identify sub- block, further subdivide sub-blocks into leaf cells (cells that cannot be further subdivided.)
define the top-level block and identify the sub-blocks necessary to built the top-level block. further subdivide the sub-blocks until to leaf cells, which are the cells that cannot be further divided

Bottom-Up design

In a bottom-up design methodology, first identify the building blocks that are available and built bigger cells, using these building blocks. These cells are then used for higher-level blocks until we built the top-level block in the design

Example

MODULES
Basic building block. Can be collection of lower level design blocks or an element. Describes the functionality on structure of a design & also ports through which it communicates.

User Identifiers
Formed from {[A-Z], [a-z], [0-9], _, $}, but .. .. cant begin with $ or [0-9]

myidentifier m_y_identifier 3my_identifier $my_identifier

_myidentifier$

Case sensitivity
myid Myid

Comments

// The rest of the line is a comment /* Multiple line comment

*/
*/

/* Nesting /* comments */ do NOT work

Operators

Numbers in Verilog (i)

No of bits

<size><radix> <value>
Binary Octal Decimal Hexadecimal b or B o or O d or D h or H Consecutive chars 0-f, x, z

8h ax = 1010xxxx 12o 3zx7 = 011zzzxxx111

Numbers in Verilog (ii)

You can insert _ for readability
12b 000_111_010_100 12b 000111010100 12o 07_24 Represent the same

Bit extension
MS bit = 0, x or z
4b x1 = 4b xx_x1

number

extend this

MS bit = 1

zero extension

4b 1x = 4b 00_1x

Numbers in Verilog (iii)

If size is ommitted it
is inferred from the value or takes the simulation specific number of bits or takes the machine specific number of bits(at least 32)

If radix is ommitted too .. decimal is assumed

15 = <size>d 15

Data Types

Nets (i)
Can be thought as hardware wires driven by logic Equal z when unconnected Various types of nets
wire

wand wor tri

(wired-AND) (wired-OR) (tri-state)

In following examples: Y is evaluated, automatically, every time A or B changes

Nets (ii)
A B
wire Y; // declaration assign Y = A & B;

wand Y; // declaration assign Y = A; assign Y = B;

Y
B
wor Y; // declaration assign Y = A; assign Y = B;

dr A Y
tri Y; // declaration assign Y = (dr) ? A : z;

Registers
Variables that store values Do not represent real hardware but .. .. real hardware can be implemented with registers Only one type: reg
reg A, C; // declaration // assignments are always done inside a procedure A = 1; C = A; // C gets the logical value 1 A = 0; // C is still 1 C = 0; // C is now 0

Register values are updated explicitly!!

Vectors
Represent buses

wire [3:0] busA; reg [1:4] busB; reg [1:0] busC;

Left number is MS bit Slice management

busA[1]; busC = busA[2:1]; busA[2];

busC[1] =
busC[0] =

Vector assignment (by position!!)

busB = busA; busB[1] = busA[3]; busB[2] = busA[2]; busB[3] = busA[1]; busB[4] = busA[0];

Integer & Real Data Types

Declaration

integer i, k; real r;

Use as registers (inside procedures)

i = 1; // assignments occur inside procedure r = 2.9; k = r; // k is rounded to 3

Integers are not initialized!! Reals are initialized to 0.0

Time Data Type

Special data type for simulation time

measuring
Declaration

time my_time;

Use inside procedure

my_time = $time; // get current sim time

Simulation runs at simulation time, not real

time

Arrays (i)
Syntax
integer count[1:5]; // 5 integers reg var[-15:16]; // 32 1-bit regs reg [7:0] mem[0:1023]; // 1024 8-bit regs

Accessing array elements

Entire element: mem[10] = 8b 10101010; Element subfield (needs temp storage):

reg [7:0] temp; .. temp = mem[10]; var[6] = temp[2];

Arrays (ii)
Limitation: Cannot access array subfield or entire array at once
var[2:9] = ???; // WRONG!! var = ???; // WRONG!!

No multi-dimentional arrays
reg var[1:10] [1:100]; // WRONG!!

Arrays dont work for the Real data type

real r[1:10]; // WRONG !!

Strings
Implemented with regs:

reg [8*13:1] string_val; // can hold up to 13 chars
.. string_val = Hello Verilog; string_val = hello; // MS Bytes are filled with 0

string_val = I am overflowed; // I is truncated

Escaped Characters:
\n \t %% \\ \
newline tab % \

Parameters

System Tasks
Always written inside procedures

$display(.., arg2, arg3, ..); much like printf(), displays formatted string in std output when encountered $monitor(.., arg2, arg3, ..); like $display(), but .. displays string each time any of arg2, arg3, .. Changes $stop; suspends sim when encountered $finish; finishes sim when encountered $fopen(filename); returns file descriptor (integer); then, you can use $fdisplay(fd, .., arg2, arg3, ..); or $fmonitor(fd, .., arg2, arg3, ..); to write to file $fclose(fd); closes file $random(seed); returns random integer; give her an integer as a seed

$display & $monitor string format

Compiler Directives
`include filename inserts contents of file into current file; write it anywhere in code .. `define <text1> <text2>
text1 substitutes text2;
in declaration part:

e.g. `define BUS reg [31:0] `BUS data;

`timescale <time unit>/<precision>

e.g. `timescale 10ns/1ns later: #5 a = b;

50 ns

Modules

Ports

Port Connection Rules

Port Connection Rules

Test Bench