VLSI MAIN PROJECT LIST 1. 2.

LOW POWER AND AREA EFFICIENT CARRY SELECT ADDER HIGH SPPED BOOTH ENCODER MULTIPLIER FOR SIGNED AND UNSIGNED NUMBERS 3. 4. DESIGN OF LOW POWER TPG USING LP-LFSR DESIGN AND IMPLEMENTATION OF REED SOLOMAN DECODER FOR 802.1b 5. FPGA NETWORK USING FPGA IMPLEMENTATION OF CHAOTIC PSEUDO RANDOM BIT

GENERATORS 6. DESIGN AND SIMULATION OF 32 POINT FFT USING RADIX 2 ALGORITHM FOR FPGA IMPLEMENTATION 7. DESIGN AND IMPLEMENATION OF HIGH PERFORMANCE MULTIPLER USING HDL 8. DESIGN AND REALIZATION OF SERIAL FRONT PANEL DATA PORT (SFPDP) PROTOCOL 9. IMPLEMENTATION OF VLSI ORIENTED FELICS ALGORITHM USING PSEUDO DUAL PORT RAM 10. A NOVEL ENCODING SCHEME FOR LOW POWER IN NETWORK ONCHIPLINKS 11. EFFICIENT CONFIGURABLE DECODER ARCHITECTURE FOR NON BINARY QUASI LDPC CODES 12. FPGA IMPLEMENTATION OF 16 BIT BBS AND LFSR PN SEQUENCE GENERATOR 13. DESIGN AND IMPLEMENTATION OF AUTOMATED WAVE PIPELINE CIRCUIT USIG ASIC

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IMPLEMENTATION OF DFT FILTER BANKS BASED ON FPGA

15. DESIGN OF FPGA BASED TRAFFIC LIGHT CONTROLLER SYSTEM 16. DESIGN AND IMPLEMENTATION OF FLOATING POINT MULTIPLER USING VERILOG HDL 17. SIMULATION OF UART USING VERILOG HDL 18. AREA OPTIMIZED AES BASED ON VERILOG HDL 19. COMPLEX MULTIPLIER USING NIKHILAM SUTRAS 20. SERIAL COMMUNICATION INTERFACING 21. 16 BIT RISC PROCESSOR USING VERILOG HDL 22. SHA-1 ALGORITHM USING VERILOG HDL 23. IMAGE ENCRYPTION BASED ON AES 24. DIRECT DIGITAL SYNTHESIZER USING VHDL 25. SPUR REDUCTON BASED ON VERILOG HDL 26. BOOTH MULTIPLIER USING VERILOG HDL 27. COMPLEX COMPARATOR USING VERILOG HDL 28. 32 BIT UNSIGNED MULTIPLIER USING VERILOG HDL 29. 32- BIT ALU USING VERILOG HDL 30. 32-BIT BARREL SHIFTER USING VERILOG HDL.