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Main.CPP
/*****************************************************************************
The following code is derived, directly or indirectly, from Powen Ko and Hung-Jui Wang
Copyright (c) 2006 by all NPU.
All Rights reserved.
*****************************************************************************/
/*****************************************************************************
main.cpp -- This is the top level file instantiating the modules and
binding ports to signals.
Original Author: Amit Rao, Synopsys, Inc.
*****************************************************************************/
#include "systemc.h"
#include "stage1.h"
#include "stage2.h"
#include "stage3.h"
#include "display.h"
#include "numgen.h"
#include "AHBBridge.h"
#define NS * 1e-9
int sc_main(int ac, char *av[])
{
//Clock
sc_signal<bool>
clk;
//Signals
sc_signal<bool>
HRESETn;
sc_signal<sc_uint<32> > HADRR;
sc_signal<sc_uint<2> > HTRANS;
sc_signal<bool>
HWRITE;
sc_signal<sc_uint<32> > HWDATA;
sc_signal<bool>
HSELAPBif;
sc_signal<sc_uint<32> > HRDATA;
sc_signal<bool>
HREADin;
sc_signal<bool>
HREADYout;
sc_signal<sc_uint<2> > HRESP;
sc_signal<sc_uint<32> > PRDATA;
sc_signal<sc_uint<32> > PWDATA;
sc_signal<bool> PENABLE;
sc_signal<bool> PSELx;
sc_signal<sc_uint<32> > PADDR;
sc_signal<bool> PWRITE;
//Signals
sc_signal<double> in1;
sc_signal<double> in2;
sc_signal<double> sum;
sc_signal<double> diff;
sc_signal<double> prod;
sc_signal<double> quot;
sc_signal<double> powr;
AHBBridge AHBBridge1("AHBBridge");
AHBBridge1(clk,HRESETn,HADRR,HTRANS,
HWRITE,HWDATA,HSELAPBif,HRDATA,
HREADin,HREADYout,HRESP,PRDATA,PWDATA,PENABLE,
PSELx,PADDR,PWRITE );
/*
numgen N("numgen");
N(in1, in2, clk );
stage1 S1("stage1");
//Named port binding
S1.in1(in1);
S1.in2(in2);
S1.sum(sum);
S1.diff(diff);
S1.clk(clk);
stage2 S2("stage2");
//instance of `stage2' module
S2(sum, diff, prod, quot, clk ); //Positional port binding
stage3 S3("stage3");
//instance of `stage3' module
S3( prod, quot, powr, clk);
//Positional port binding
*/
display D("display");
//instance of `display' module
D(powr, clk);
//Positional port binding
sc_initialize();
//Initialize simulation
for(int i = 0; i < 50; i++){
clk.write(1);
sc_cycle( 10 NS );
clk.write(0);
sc_cycle( 10 NS );
}
return 0;
}
AHBBridge.H
/*****************************************************************************
AHBBridge.H -- This is the interface file for the stage1 module.
Original Author: Amit Rao, Synopsys, Inc.
*****************************************************************************/
#ifndef AHBBRIDGE1_H
#define AHBBRIDGE_H
struct AHBBridge : sc_module {
//Signals
sc_in<bool>
clk;
sc_in<bool>
HRESETn;
sc_in<sc_uint<32> > HADRR;
sc_in<sc_uint<2> > HTRANS;
sc_in<bool>
HWRITE;
sc_in<sc_uint<32> > HWDATA;
sc_in<bool>
HSELAPBif;
sc_out<sc_uint<32> > HRDATA;
sc_in<bool>
HREADin;
sc_out<bool>
HREADYout;
sc_out<sc_uint<2> > HRESP;
sc_in<sc_uint<32> > PRDATA;
sc_out<sc_uint<32> > PWDATA;
sc_out<bool> PENABLE;
sc_out<bool> PSELx;
sc_out<sc_uint<32> > PADDR;
sc_out<bool>
PWRITE;
//u_int
// sc_uint<32> Memory[0xff];
//Signals
AHBBridge.cpp
#include "systemc.h"
#include "AHBBridge.h"
//Definition of addsub method
/*
sc_in<bool>
clk;
sc_in<bool>
HRESETn;
sc_in<sc_uint<32> > HADRR;
sc_in<sc_uint<2> > HTRANS;
sc_in<bool>
HWRITE;
sc_in<sc_uint<32> > HWDATA;
sc_in<bool>
HSELAPBif;
sc_out<sc_uint<32> > HRDATA;
sc_in<bool>
HREADin;
sc_out<bool>
HREADYout;
sc_out<sc_uint<2> > HRESP;
sc_in<sc_uint<32> > PRDATA;
sc_out<sc_uint<32> > PWDATA;
sc_out<bool> PENABLE;
sc_out<bool> PSELx;
sc_out<sc_uint<32> > PADDR;
sc_out<bool> PWRITE;
*/
void AHBBridge::Action()
{
bool i_HRESETn;
bool i_HWRITE;
bool valid=true;
sc_uint<32> i_PRDATA;
sc_uint<32> i_HWDATA;
// double b;
i_HRESETn = HRESETn.read();
i_HWRITE = HWRITE.read();
i_PRDATA = PRDATA.read();
i_HWDATA = HWDATA.read();
Main.CPP
//main.cpp
#include "systemc.h"
#include "fetch.h"
#include "decode.h"
#include "exec.h"
#include "mem_acc.h"
#include "wr_back.h"
#include "Memory.h"
int sc_main(int ac, char *av[])
{
//Memory
sc_signal<bool> m_Read_en;
sc_signal<int> m_addressShift;
sc_signal<int> m_address;
sc_signal<sc_uint<32> > m_MemoryData32;
//fetch
sc_signal<int> nnpc; // out of mem_acc
sc_signal<int> npc;
sc_signal<int> ir;
//decode
sc_signal<int> mux3_out;
sc_signal<int> A;
sc_signal<int> B;
sc_signal<int> imm;
sc_signal<bool> mux0_en;
sc_signal<bool> mux1_en;
sc_signal<sc_uint<5> > alu_cont;
sc_signal<sc_uint<3> > cond_sel;
sc_signal<int> dest_out;
//exec
sc_signal<bool> cond_out;
sc_signal<int> alu_out;
sc_signal<bool> mux3_en;
sc_signal<bool> wrd;
//mem_acc
sc_signal<int> lmd;
//wr_back all signals have been already defined
//const int delay_cycles = 2;
sc_clock clk("Clock", 1, 0.5, 0.0);
Memory MEM ("memory_block");
MEM << clk << m_Read_en << m_addressShift << m_address << m_MemoryData32 ;
// << ir << mux3_out << A << B << imm << mux0_en << mux1_en<<alu_cont << cond_sel << dest_out;
decode IDU ("decode_block");
IDU << clk << ir << mux3_out << A << B << imm << mux0_en << mux1_en<<alu_cont << cond_sel << dest_out;
/*//initialize nnpc
nnpc.write(0); //***********check it out
mux3_out.write(777);
//instantiation
fetch IFU("fetch_block") ;
IFU << nnpc << clk << npc << ir ;
decode IDU ("decode_block");
IDU << clk << ir << mux3_out << A << B << imm << mux0_en << mux1_en<<alu_cont << cond_sel << dest_out;
exec IEU("execute_block");
IEU << clk << npc << A << mux0_en << B << imm << mux1_en << alu_cont <<cond_sel << cond_out << alu_out << mux3_en
<< wrd;
mem_acc MU("memory_access_block");
MU << clk << dest_out << wrd << alu_out << cond_out << npc << nnpc << lmd ;
wr_back WB("write_back_block");
WB << lmd << alu_out << mux3_en << mux3_out;
*/
sc_start(clk, -1);
cout << "Time for simulation = " << (time(NULL) - tbuffer) << endl;
return 0; /* this is necessary */
} //end of main
decode.h
//------------------------/*
sc_in<short> i_P;
sc_out<short> o_PopP;
*/
// sc_uint<4> t_P;
//sc_short<>
//-----------------------//output ports
sc_out<int> A;
sc_out<int> B;
sc_out<int> imm;
sc_out<bool> mux0_en;
sc_out<bool> mux1_en;
sc_out<sc_uint<5> > alu_cont;
sc_out<sc_uint<3> > cond_sel; //branch select to cond
sc_out<int> dest_out; //for store
// registers 16x32
sc_int<32> reg_mem[16];
//temp
sc_uint<32> ir_temp;
sc_uint<32> imm_temp;
// inst format
sc_uint<5> opcode;
sc_uint<4> dest;
sc_uint<4> src_a;
sc_uint<4> src_b;
sc_uint<16> offset;
//constructor
SC_CTOR(decode) {
reg_mem[0] = 0x1;
reg_mem[1] = 0x2;
reg_mem[2] = 0x5;
reg_mem[3] = 0x4;
reg_mem[4] = 0x5;
reg_mem[5] = 0x1;
reg_mem[6] = 0x7;
reg_mem[7] = 0x3;
reg_mem[8] = 0xA;
reg_mem[9] = 0x7;
reg_mem[10]
reg_mem[11]
reg_mem[12]
reg_mem[13]
reg_mem[14]
reg_mem[15]
=
=
=
=
=
=
0xB;
0x1;
0x1;
0x1;
0x1;
0x1;
SC_CTHREAD(decoder, clk.pos());
SC_CTHREAD(sign_extend, clk.pos());
SC_CTHREAD(registers, clk.pos());
}
//fuctionality of the process
void decoder();
void sign_extend();
void registers();
/*
void
void
void
void
*/
};
//end of constructor
CodecInitialize();
CodecPushPixel(); //short p);
CodecPopPixel();//void);
CodecDoFdct();//void);
//end of decode.h
decode.cpp
cond_sel.write(0);
break; }
case 10: {
mux0_en.write(1); //and
mux1_en.write(0);
alu_cont.write(10);
cond_sel.write(0);
break; }
case 11: {
mux0_en.write(1); //andi
mux1_en.write(1);
alu_cont.write(11);
cond_sel.write(0);
break; }
case 12: {
mux0_en.write(1); //or
mux1_en.write(0);
alu_cont.write(12);
cond_sel.write(0);
break; }
case 13: {
mux0_en.write(1); //ori
mux1_en.write(1);
alu_cont.write(13);
cond_sel.write(0);
break; }
case 14: {
mux0_en.write(1); //xor
mux1_en.write(0);
alu_cont.write(14);
cond_sel.write(0);
break; }
case 15: {
mux0_en.write(1); //xori
mux1_en.write(1);
alu_cont.write(15);
cond_sel.write(0);
break; }
case 16: {
mux0_en.write(1); //not
mux1_en.write(0); //don't care
alu_cont.write(16);
cond_sel.write(0);
break; }
case 17: {
mux0_en.write(1); //lsl
mux1_en.write(0); //don't care
alu_cont.write(17);
cond_sel.write(0);
break; }
case 18: {
mux0_en.write(1); //lsr
mux1_en.write(0); //don't care
alu_cont.write(18);
cond_sel.write(0);
break; }
case 19: {
mux0_en.write(1); //asr
mux1_en.write(0); //don't care
alu_cont.write(19);
cond_sel.write(0);
break; }
case 20: {
mux0_en.write(0); //jmp
mux1_en.write(1);
alu_cont.write(20);
cond_sel.write(7);
break; }
case 21: {
mux0_en.write(1); //jmpr
mux1_en.write(1);
alu_cont.write(21);
cond_sel.write(7);
break; }
case 22: {
mux0_en.write(0); //jali
mux1_en.write(1);
alu_cont.write(22);
cond_sel.write(7);
break; }
case 23: {
mux0_en.write(0); //beqz
mux1_en.write(1);
alu_cont.write(23);
cond_sel.write(1);
break; }
case 24: {
mux0_en.write(0); //bneqz
mux1_en.write(1);
alu_cont.write(24);
cond_sel.write(2);
break; }
case 25: {
mux0_en.write(0); //bgtz
mux1_en.write(1);
alu_cont.write(25);
cond_sel.write(3);
break; }
case 26: {
mux0_en.write(0); //bgtez
mux1_en.write(1);
alu_cont.write(26);
cond_sel.write(4);
break; }
case 27: {
mux0_en.write(0); //bltz
mux1_en.write(1);
alu_cont.write(27);
cond_sel.write(5);
break; }
case 28: {
mux0_en.write(0); //bltez
mux1_en.write(1);
alu_cont.write(28);
cond_sel.write(6);
break; }
case 29: {
mux0_en.write(1); //trap
mux1_en.write(1);
alu_cont.write(29);
cond_sel.write(0);
break; }
case 30: {
mux0_en.write(0); //tret
mux1_en.write(1);
alu_cont.write(30);
cond_sel.write(0);
break; }
case 31: {
mux0_en.write(1); //don't care //noop
mux1_en.write(0); //don't care
alu_cont.write(31);
cond_sel.write(0);
break; }
} //end of switch stmt
wait();
}
// idx = 0;
} //end of decoder
void decode :: registers()
{ int counter =0;
while ( 1 ) {
counter =counter+1;
ir_temp=ir.read();
opcode = ir_temp.range(31,27);
printf ("opcode in REG %x \n", opcode);
printf("IR is %x \n", ir.read());
ir_temp=ir.read();
dest = ir_temp.range(26,23);
src_a = ir_temp.range(22,19);
src_b = ir_temp.range(18,15);
cout << " dest is " << dest << endl;
cout << " src_a is " << src_a << endl;
cout << " src_b is " << src_b << endl;
A.write(reg_mem[src_a]);
B.write(reg_mem[src_b]);
memory.h
SC_MODULE(Memory){
//input ports
//sc_in_clk clk;
/* sc_in<int> mux3_0;
sc_in<int> mux3_1;
sc_in<bool> mux3_en;
*/
//input ports
sc_in_clk clk;
sc_in<bool> i_Read_en;
sc_in<int> i_addressShift;
sc_in<int> i_address;
//output ports
sc_out<sc_uint<32> > o_MemoryData32;
sc_uint<32>
t_MemoryData32;
sc_int<32>
t_address;
/*
sc_out<int> mux3_out;
*/
SC_CTOR(Memory){
SC_METHOD(ReadWriteMemory);
//SC_METHOD(mux3);
// sensitive << mux3_en ;
}
//functionality of the process
//void mux3();
void ReadWriteMemory();
};
//end of mem_acc.h
memory.cpp
/*--------------------------------------------------------------------------*/
static const short COS_MemoryTABLE[8*8*8*8] = {
//1,1
00001, 00001, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, 23170, -32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, -27245, 23170,
-18204, 12539, -6392,
//1,2
00001, 00002, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, 23170, -32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, -27245, 23170,
-18204, 12539, -6392,
//1,3
00001, 00003, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, 23170, -32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, 27245, 23170, -18204, 12539, -6392,
//1,4
00001, 00004, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, 23170, -32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, 27245, 23170, -18204, 12539, -6392,
//1,5
00001, 00005, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, 23170, -32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, 27245, 23170, -18204, 12539, -6392,
//1,6
00001, 00006, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, 23170, -32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, 27245, 23170, -18204, 12539, -6392,
//1,7
00001, 00007, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, 23170, -32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, 27245, 23170, -18204, 12539, -6392,
//1,8
00001,
8, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, -23170,
-32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, 27245, 23170, -18204, 12539, -6392,
//2,1
//5,6
00005, 00006, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, 23170, -32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, 27245, 23170, -18204, 12539, -6392,
//5,7
00005, 00007, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, 23170, -32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, 27245, 23170, -18204, 12539, -6392,
//5,8
00005,
8, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, -23170,
-32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, 27245, 23170, -18204, 12539, -6392,
//6,1
00006, 00001, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, 23170, -32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, -27245, 23170,
-18204, 12539, -6392,
//6,2
00006, 00002, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, 23170, -32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, -27245, 23170,
-18204, 12539, -6392,
//6,3
00006, 00003, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, 23170, -32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, 27245, 23170, -18204, 12539, -6392,
//6,4
00006, 00004, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, 23170, -32138, -30273, -18204,
32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245,
32768, 6392, -30273, 18204, 23170, 27245, -12539, -32138,
32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138,
32768, -18204, -12539, 32138, 23170, -6392, 30273, -27245,
32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204,
32768, -32138, 30273, 27245, 23170, -18204, 12539, -6392,
//6,5
00006, 00005, 30273, 27245, 23170, 18204, 12539, 6392,
32768, 27245, 12539, -6392, -
6392, -30273, -
6392, -30273, -
6392, -30273, -
/*
void Memory :: mux3()
{
cout << " I AM IN MUX3" << endl;
if (mux3_en.read() == 0) {
mux3_out.write(mux3_0.read()); }
else {
mux3_out.write(mux3_1.read()); }
}
*/