Trojan

2-D Router Project Part-3 -2012 SPRING

Professor: Dr. Jerey Draper
By Arthur Chen Parth Desai
EE- 577B Date: 04/23/2012

Work DistribuPon Input Controller Output Controller Dierent Test Benches Synthesis errors SoluPon to errors Synthesis Results Improvements to Design Are Delay product Further Improvement? Prime Time SoC Encounter

OUTLINE

Work DistribuPon
Project

PARTH ARTHUR

Project part 1
Input Controller Output Controller Combining the input and output controller

Project part 2
Gather test bench 50 other Test benches for exhausPve tesPng Help in making the top module ModicaPon in the design to get blocking condiPon work Top module

Project part 3
Synthesis

Help in debugging the erros -synthesis Prime Time Placing and rouPng

 Input Controller Roles

Handshaking with sending router RouPng Handshaking with output controllers Controlling FIFO

Input Controller Role:Handshaking

Use non-blocking assignment in always @(posedge clk) block to model sequenPal logic

GeneraPon of ri is shown only for the one state

Input Controller Role: RouPng

Decoding rouPng header of newly arrived packet to determine which output controller to request .The following code is for the rouPng for XP input controller. Non blocking Assignment

ArbitraPon/Output Controller Roles

Handshaking with receiving router ArbitraPon Handshaking with input controllers UpdaPng rouPng info

Output Controller Role: ArbitraPon

Negedge of clock

Output Controller Role: Handshaking with input controller- GeneraPng the ack signal
All the inputs are in the sensiPvity list Blocking condiPon

The output is assigned in every control path These are the key rules that we learnt in the class to specify combinaPonal block using procedural statement.

Output Controller Role: UpdaPng the rouPng informaPon

The transiPon is at the negaPve edge of colck

The non blocking assignment

Dened the else condiPon in order to prevent the latch

Dierent TesPng approaches:

Our method was to go from simple tests based on gather to more complicated tests similar to ooding.

XP_connecn XP_connecn

node 0

XN_connecn

node 1

XN_connecn

node 2

node 3

YN_connecn YN_connecn

YN_connecn

YN_connecn

node 6

YP_connecn
XP_connecn XN_connecn

node 4

YP_connecn
XP_connecn XN_connecn

node 5

YP_connecn

YN_connecn

YN_connecn

YP_connecn
XP_connecn XN_connecn

node 7

YP_connecn
XP_connecn XN_connecn

node 8

YP_connecn

We also checked the prioriPzaPon of outputs, but aber a while we stopped hand calculaPng them since we were somewhat condent in our priority scheme.
XP_connecn XP_connecn

node 0

XN_connecn

node 1

XN_connecn

node 2

YN_connecn

YN_connecn

YN_connecn

YP_connecn

YP_connecn

YP_connecn

I am going to reach rst

Wait!! I have the priority

XP_connecn

XP_connecn

node 3

XN_connecn

node 4

XN_connecn

node 5

YN_connecn

YN_connecn

YN_connecn

node 6

YP_connecn

YP_connecn

YP_connecn

XP_connecn XN_connecn

XP_connecn

node 7

XN_connecn

node 8

In a few of the test cases we also send in wrong packets, which cause our NoC to lock up, such as test cases when we put a posiPve hop count in the x eld for y-input.
XP_connecn XP_connecn

node 0

XN_connecn

node 1

XN_connecn

node 2

node 3

YN_connecn YN_connecn

YN_connecn

YN_connecn

node 6

YP_connecn
XP_connecn XN_connecn

node 4

YP_connecn
XP_connecn XN_connecn

node 5

YP_connecn

YN_connecn

YN_connecn

YP_connecn
XP_connecn XN_connecn

node 7

YP_connecn
XP_connecn XN_connecn

node 8

YP_connecn

The lader tests basically just test the interconnecPon, and test if the router is deadlock free and that all the packets go somewhere and aren't all lost.
XP_connecn XP_connecn

node 0

XN_connecn

node 1

XN_connecn

node 2

node 3

YN_connecn YN_connecn

YN_connecn

YN_connecn

node 6

YP_connecn

YP_connecn

YP_connecn

XP_connecn XN_connecn

XP_connecn

node 4

XN_connecn

node 5

YN_connecn

YN_connecn

YP_connecn

YP_connecn

YP_connecn

XP_connecn XN_connecn

XP_connecn

node 7

XN_connecn

node 8

Towards the end of our test cases we ood the NoC with a gather test on all the possible nodes and count the amount of peso's that come out of that node to make sure we aren't losing packets
XP_connecn XP_connecn

node 0

XN_connecn

node 1

XN_connecn

node 2

node 3

YN_connecn YN_connecn

YN_connecn

YN_connecn

node 6

YP_connecn
XP_connecn XN_connecn

node 4

YP_connecn
XP_connecn XN_connecn

node 5

YP_connecn

YN_connecn

YN_connecn

YP_connecn
XP_connecn XN_connecn

node 7

YP_connecn
XP_connecn XN_connecn

node 8

YP_connecn

SYNTHESIS
Architecture DescripPon HDL SpecicaPon Synthesis
(Behavioral, Structural)

Now that RTL has been fully veried, we can generate layout through synthesis and place & route steps

(Structural)

Place & Route

(Physical)

Physical VericaPon
(DRC, LVS, etc)

Synthesis Report Errors & Warnings Error: Net '/home/scf-06/parthdes/syn/src/output_control_4.v:54:

counter[0]' or a directly connected net is driven by more than one source, and not all drivers are three-state. (ELAB-366) Warning: /home/scf-06/parthdes/syn/src/input_ctrl_yp.v:185: PotenPal simulaPon-synthesis mismatch if index exceeds size of array 'fo'. (ELAB-349) Warning: /home/scf-06/parthdes/syn/src/output_control_4.v:193: signed to unsigned assignment occurs. (VER-318) Warning: /home/scf-06/parthdes/syn/src/output_control_4.v:307: 'reset' is being read, but does not appear in the sensiPvity list of the block Warning: Unable to determine wired-logic type for mulPple-driver net 'counter[0]'. (TRANS-5)

Solu:ons to Errors

Solu:ons to Errors

Synthesis Results

Area

CriPcal Path

Improvements/Revisions

Revision 1

Revision 1 Result

Revision 2

Revision 2 Result

Delay in Cri:cal Path

5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 Original Rev 1 Rev 2

Delay

Area
680000 678000 676000 674000 672000 670000 668000 666000 664000 662000 660000 Original Rev 1 Rev 2

Area

Area Delay Product

3000000 2500000 2000000 1500000 1000000 500000 0 IniPal Current Area ADP 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 IniPal Current Delay

Further Improvements?
Input Controller Might be able to do it with out any state machines, just counters Output Controller Might be possible with no state machine either, or to simplify boolean expressions in case statements

Prime Time

SoC Encounter

P&R Summary

Pre-CTS

Post-CTS

To Do
Logical Equivalency Check Further Reduce ADP

Layout of the Design