Schematic and PCB Numbers

8
2
REV ECN
1
DESCRIPTION OF REVISION CK APPD DATE
2010-07-22
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
SCHEM,MLB DVT,K99
D
(.csa)
07/22/10
Date (.csa) Date
Page
TABLE_TABLEOFCONTENTS_HEAD
Contents
1
Sync
TABLE_TABLEOFCONTENTS_HEAD
Page
57
Contents
WELLSPRING 1
61
Sync
07/07/2010 K16_MLB 07/07/2010 K16_MLB 02/09/2010
1
TABLE_TABLEOFCONTENTS_ITEM
Table of Contents
2 12/11/2009
46
K6_MLB 12/11/2009
2
System Block Diagram

3
47
66
SPI ROM AUDI0: SPEAKER AMP

69
3
Power Block Diagram

4
K6_MLB 12/11/2009
48 49
07/20/2009
AUDIO 11/09/2009
4
K99 BOM Variants

5
K6_MLB
DC-In & Battery Connectors

70
K84_MLB 11/09/2009
5
BOM Configuration
6
K24_MLB 01/19/2009
50
72
PBus Supply & Battery Charger 5V / 3.3V Power Supply

73
K6_MLB 07/07/2010 K16_MLB 07/07/2010
6
Revision History
7
K24_MLB 12/11/2009
51 52
12/11/2009
7
FUNCTIONAL TEST
8
K6_MLB
1.5V/1.35V LVDDR3 Supply

74
K16_MLB 07/13/2005
8
Power Aliases
9
K6_MLB 12/11/2009
53
75
IMVP6 CPU VCore Regulator MCP VCore Regulator

76
POWER 12/11/2009 K6_MLB 07/07/2010
9
SIGNAL ALIAS
10
K6_MLB 07/07/2010
54 55
07/07/2010
10
CPU FSB
11
K16_MLB
CPUVTT (1.05V) Power Supply

77
K16_MLB 07/07/2010
11
CPU Power & Ground

12
K16_MLB
56
03/24/2010 78
Misc Power Supplies Power Sequencing

79
K16_MLB 07/07/2010 K16_MLB 07/07/2010
12
CPU Decoupling & VID

13
K16_MLB
57
07/07/2010
13
eXtended Debug Port (Micro-XDP)

14
K16_MLB
58
07/07/2010 90
Power FETs Internal DisplayPort Connector

93
K16_MLB 07/07/2010 K16_MLB 07/07/2010
14
MCP CPU Interface

15
K16_MLB 07/07/2010
59 60
07/07/2010
15
MCP Memory Interface

16
K16_MLB
External DisplayPort Support

94
K16_MLB 07/07/2010
16
MCP PCIe Interfaces

17
K16_MLB 07/07/2010
61
97
DisplayPort Connector LCD Backlight Driver

98
K16_MLB 03/31/2010 K16_MLB 07/07/2010
17
MCP Graphics
18
K16_MLB 07/07/2010
62 63
07/07/2010
18
MCP SATA, USB & Ethernet

19
K16_MLB
LCD Backlight Support

99
K16_MLB 07/07/2010
19
MCP HDA, LPC & MISC

20
K16_MLB 07/07/2010
64
100
Additional CPU/GPU Decoupling CPU/FSB Constraints

101
K16_MLB 07/07/2010 K16_MLB 07/07/2010
20
MCP Power & Ground

23
K16_MLB 07/07/2010
65 66
07/07/2010
21
MCP89 Memory Rail Gating

24
K16_MLB
Memory Constraints
102
K16_MLB 07/07/2010
22
MCP89 GFX Core Rail Gating

25
K16_MLB 07/07/2010
67
103
MCP Constraints 1 MCP Constraints 2

104
K16_MLB 07/07/2010 K16_MLB 07/07/2010
23
MCP Standard Decoupling

26
K16_MLB 07/07/2010
68 69
12/11/2009
24
MCP Graphics Support

28
K16_MLB
Ethernet Constraints
106
K16_MLB 07/07/2010
25
SB Misc
31
K6_MLB 07/07/2010
70
108
SMC Constraints K16/K99 Specific Constraints

109
K16_MLB 07/07/2010 K16_MLB 07/07/2010
26
DDR3 DRAM Channel A (0-31)

32
K16_MLB 07/07/2010
71 72
07/07/2010
27

33
K16_MLB
K99 RULE DEFINITIONS

110
K16_MLB 07/07/2010
28
DDR3 DRAM Channel B (0-31)

34
K16_MLB 07/07/2010
73
07/07/2010
Acoustic Cap BOM Config Tables
K16_MLB
29

35
K16_MLB
30
DDR BYPASSING 1
36
K16_MLB 07/07/2010
31
DDR BYPASSING 2
37
K16_MLB 07/07/2010
32
Memory Active Termination

39
K16_MLB 07/07/2010
33
FSB/DDR3 Vref Margining

40
K16_MLB 07/07/2010
34
X21 WIRELESS CONNECTOR

45
K16_MLB 07/07/2010
35
SATA CONNECTOR
46
K16_MLB 07/07/2010
36
External USB Connectors

47
K16_MLB N/A
37
LIO CONNECTORS
49
N/A 07/07/2010
38
SMC
50
K16_MLB 07/07/2010
39
SMC Support
51
K16_MLB 07/07/2010
40
LPC+SPI Debug Connector

52
K16_MLB 07/07/2010
41
K16/K99 SMus Connections

53
K16_MLB 07/07/2010
42
Voltage & Current Sensing

54
K16_MLB 07/07/2010
43
Current Sensing
55
K16_MLB 07/07/2010
44
Thermal Sensors
56
K16_MLB 07/07/2010
45
Fan
K16_MLB
A
DRAWING TITLE
A
SCHEM,MLB,K99
DRAWING NUMBER SIZE
Schematic / PCB #s
PART NUMBER
051-8379 820-2796
Apple Inc.
DESCRIPTION
SCHEM,MLB,K99
051-8379
REVISION
QTY
1 1
REFERENCE DES
SCH PCB
CRITICAL
CRITICAL CRITICAL
BOM OPTION
4.4.0
BRANCH PAGE
NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
PCBF,MLB,K99
1 OF 110
SHEET
1 OF 73
6
U1000
INTEL CPU
1.6 GHZ PENRYN
J1300
XDP CONN
PG 13
1GB
PG 10
D
PG 14
FSB 64-BIT 800MHZ BASE FREQ.=200MHZ
U3100,U3200
MEMORY
128MX8
D
1GB
J6950,U7000
DDR3-1066/1333MHZ
A 64-BIT
PG 26,27
CHARGER,BATT CONN
PG 50,51
POWER SUPPLY
PG 52-57
GPIO
PG 19
FSB INTERFACE
MAIN MEMORY
U3300,3400 PG 15 U5515.U5535
MEMORY
DDR3-1066/1333MHZ
B 64-BIT
PG 28,29 128MX8
CPU/MCP TEMP SENSOR

PG 44
Y2815
RTC XTAL 32.768KHZ

PG 25
VOLTAGE/CURRENT SENSOR
PG 42,43
MISC
U6100 J5600
Y2810
PG 19
SPI
PG 19
MCP 25MHZ
PG 25
SPI BOOTROM
PG 48
FAN CONN
PG 45
U5920
SATA
SUPPORT GEN3,6.0GB/S UP TO 2 PORTS
SMS
PG 47
NVIDIA
U4900
J4501
SSD SATA
MCP89U-A01
J5100
SMB_BSA
SMB_B/0
ADC
FAN0
SMS
SATA 2.0 3GBIT/S
SATA_A0
LPC
CONN
PG 35
24.5X24.5MM 0.6MM PITCH FCPBGA 1244P
LPC+SPI CONN
PG 40
SERIAL PORT
SMC
PG 38 LID SYS_LED SMB_A
PG 19
PM_SLP S3/S4
PG 18
FLAT PANEL
LVDS OUT RGB OUT HDMI OUT DVI OUT TMDS OUT
PWR CTRL
PG 19
J6955
HALL EFFECT CONN

PG 50
J9000
INTERNAL DISPLAY
CONN
PG 60
X2 DP LINK
DP1[1:0]
J5700
USB 2.0
TRACKPAD (IPD) CONN

PG 46
X4 DP LINK
J9400
DP0[3:0]
USB_2 PG 17
EXTERNAL DISPLAY
CONN
PG 62
PE0[4,5]:X2,X1 GEN2,UP TO 2 LANES PE1[0,1]:X1,X1 GEN1,UP TO 2 LANES
PCI-E
USB_6
(UP TO 8 DEVICES)
USB_0
J4600 USB_7
RIGHT EXT USB

CONN
PG 36
B
J4001
USB_5
PG 18
USB_4
AIRPORT+ BLUETOOTH
CONN
PG 34
PCIE GEN1
PE1_0
PG 16
LAN RGMII
PG 18
SMB
PG 19
HDA
J6903 PG 19
U6610
SIL+ SPEAKER
CONN
PG 50
SPEAKER
AMPS
PG 49
J4700
I2C MIKEY
HDA
USB CAMERA
USB EXT
SPK
LIO FLEX CONN

PG 37
I2C LIO
J4702
J4610
U6201
CAMERA+
ALS CONN
PG 5
LEFT EXT USB

CONN
PG 6
AUDIO CODEC
PG 6
A
U6620
SYNC_MASTER=K6_MLB
PAGE TITLE
SYNC_DATE=12/11/2009
LIO BOARD
SPEAKER
AMPS
PG 9
LINE IN
FILTER
PG 11
HEADPHONE
FILTER
PG 8
System Block Diagram

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE
J6702
J6700

JACK
PG 10
LEFT SPEAKER
CONN
PG 10
HEADPHONE/ LINE IN
2 OF 110
SHEET
2 OF 73
7
PP18V5_DCIN_CONN
K99 POWER SYSTEM ARCHITECTURE

Q7080
02
PPDCIN_G3H_OR_PBUS
ENABLE
Need to update!!!
03
SMC PWRGD RN5VD30A-F
Q7085
8A FUSE
PBUS_VSENSE
3.425V G3HOT LT3470

VOUT
PP3V42_G3H_REG
04
D
01
CHGR_EN (S5)
ENABLES
V
PPBUS_G3H
U6990
U5010
Q5315
PBUS_G3H_VSENSE
PPVBAT_G3H_CHGR_REG F7040
D
PP1V05_S0
02
VIN
CPUVTTS0_EN (S0)
EN_PSV
VOUT
F6905
CPUVTT
(1.05V)
(8A MAX CURRENT)
AC ADAPTER IN
6A FUSE DCIN(16.5V)
A
R7020
SMC_DCIN_ISENSE
VIN VOUT
ISL95870 U7600
MCP89
PWRBTN*
06-1
R7050
PBUS SUPPLY/ BATTERY CHARGER ISL6259 U7000
01 02
SMC_BATT_ISENSE
PGOOD PLTRST*
31
LPC_RESET_L
A
CPUVTTS0_PGOOD
RSMRST*
V
CPU VCORE
VOUT VIN
SMC_CPU_VSENSE PPVCORE_S0_CPU
MCP_PS_PWRGD
PWRGD
CPU_PWRGD
29 26
U2850
CPUPWRGD(GPIO49)
30
CPU_RESET# FSB_CPURST_L
J6950
IMVP_VR_ON_R 3S2P Q7055 PPVBAT_G3H_CONN
PPVBAT_G3H_CHGR_R
SMC_CPU_ISENSE ISL6261A
(44A MAX CURRENT)
U1400
VR_ON
28
PGOOD
(9 TO 12.6V)
25
U7400
VR_PWRGOOD_DELAY
C
CHGR_BGATE
CPU PPBUS_G3H
4.5V AUDIO MAX8840 VIN PWRGOOD PP4V5_AUDIO_ANALOG
VOUT
C
RESET*
U6200
EN
U1000
MCP89
PM_SLP_S4_L
32 11
11-1
P3V3S3_EN
Q7940
SMC
15
PM_SLP_S3_L
11-3 P16
02
PP5V_S0_FET
U4900
04
SMC_PM_G2_EN P60
P5VS3_EN_L 05
VIN
EN1
5V
(RT)
VOUT1
PP5V_S3_REG
(13A MAX CURRENT)
17
P5VS0_EN
U1400
RC DELAY
DDRREG_EN
(S5)
PP3V3_S5_REG
VOUT2
P3V3S5_EN_L
EN2
3.3V TPS51980 U7201
(5.5A MAX
CURRENT)
07
Q7910 PP3V3_S3_FET
11-2
02 P5VS3_EN_L
VIN
U7840
13
VREG3
RC DELAY
PGOOD1,2
Q4050 P3V3S3_EN P3V3_S3_WLAN
BKLT_EN
MC34845 U9700
ENA VOUT
P5V3V3_PGOOD
PPVOUT_SW_LCDBKLT
PM_WLAN_EN_L
B
Q7930 Q7890
AP_PWR_EN
PM_WLAN_EN_L
EN
24
ALL_SYS_PWRGD
PWRGD(P12)
SMC
RSMRST_OUT(P15)
10
PM_RSMRST_L
IMVP_VR_ON_R
18
PP3V3_S0_FET
VIN
VOUT
99ms DLY
IMVP_VR_ON(P16)
25
09
PP0V9_S5_REG P3V3S0_EN
1.8V
TPS62202 U7760
RSMRST_PWRGD SMC_ONOFF_L
RSMRST_IN(P13) PLT_RST*
16
ISL8009B U7750
PP1V8_S0_REG
PWR_BUTTON(P90)
05
P17(BTN_OUT)
PM_PWRBTN_L SMC_RESET_L
RST*
1.5V
ISL8009B
P1V5S0_PGOOD PP1V5_S0_REG P5V3V3_PGOOD

SLP_S5_L SLP_S5_L(P95) SLP_S4_L SLP_S4_L(P94) SLP_S3_L SLP_S3_L(P93)
Q7890,Q7891 PM_SLP_S3_L
U7710
MCPCORES0_PGOOD CPUVTTS0_PGOOD SMC_ADAPTER_EN

04-1
Q2300
PP1V5R1V35_SW_MCP
1.05V
TPS74701
MCPPLLDO_PGOOD
21
1.2V
ST1S12G12R
U7740
S0PGOOD_RST_L
PP1V05_S0_MCP_PLL_REG
U4900
02
VIN
PP1V2_ENET_REG
=DDRREG_EN PM_SLP_S3_L
1.5V
S5 S3
VOUT1
MCPMEM_GATE
PP1V5_S3_REG (12A MAX CURRENT) PP0V75_S0_REG (1A MAX CURRENT)
U7720
=DDTVTT_EN
14
RST*
PP3V3_S0 V1 V2 V3
0.75V
VOUT2
PP1V5_S0 PP1V05_S0
RC DELAY
P1V8S0_EN
16-3
16-1
PBUSVSENSE_EN (S0) P1V5S0_EN

16-4 16-1
TPS51116 U7300
ISL88042 U7870
SYNC_MASTER=K6_MLB
PAGE TITLE
20
MCP_CORE
PPMCPCORE_S0_R
VOUT
R7525
PPMCPCORE_S0_REG
RC DELAY
Power Block Diagram

DRAWING NUMBER SIZE
P5VS0_EN (S0)
MCPCORES0_EN
EN
(25A MAX CURRENT)

R
Apple Inc.
051-8379
REVISION
RC DELAY
CPUVTTS0_EN
16-6
RC DELAY
P3V3S0_EN
16-2
4.4.0
BRANCH PAGE
DDRVTT_EN MCPCORES0_EN
RC DELAY
VIN
16-5
02
ISL9563B U7500
3 OF 110
SHEET
3 OF 73
8
BOM Variants
7
BOM NAME
PCBA,MLB,HY 2GB,SS CAP,K99 PCBA,MLB,HY 2GB,MU CAP,K99 PCBA,MLB,HY 2GB,TY CAP,K99 PCBA,MLB,HY 4GB,SS CAP,K99 PCBA,MLB,HY 4GB,MU CAP,K99 PCBA,MLB,HY 4GB,TY CAP,K99 PCBA,MLB,SA 2GB,SS CAP,K99 PCBA,MLB,SA 2GB,MU CAP,K99 PCBA,MLB,SA 2GB,TY CAP,K99 PCBA,MLB,SA 4GB,SS CAP,K99 PCBA,MLB,SA 4GB,MU CAP,K99 PCBA,MLB,SA 4GB,TY CAP,K99 PCBA,MLB,MI 2GB,SS CAP,K99 PCBA,MLB,MI 2GB,MU CAP,K99 PCBA,MLB,MI 2GB,TY CAP,K99 PCBA,MLB,MI 4GB,SS CAP,K99 PCBA,MLB,MI 4GB,MU CAP,K99 PCBA,MLB,MI 4GB,TY CAP,K99 PCBA,MLB,1.6GHZ,EL 2GB,SS CAP,K99 PCBA,MLB,1.6GHZ,EL 2GB,MU CAP,K99 PCBA,MLB,1.6GHZ,EL 2GB,TY CAP,K99 PCBA,MLB,1.6GHZ,EL 4GB,SS CAP,K99 PCBA,MLB,1.6GHZ,EL 4GB,MU CAP,K99 PCBA,MLB,1.6GHZ,EL 4GB,TY CAP,K99 CMN PTS,PCBA,MLB,K99 K99 MLB DEVELOPMENT BOM PCBA,MLB,1.4GHZ,HY 2GB,SS CAP,K99 PCBA,MLB,1.4GHZ,HY 2GB,MU CAP,K99 PCBA,MLB,1.4GHZ,HY 2GB,TY CAP,K99 PCBA,MLB,1.4GHZ,HY 4GB,SS CAP,K99 PCBA,MLB,1.4GHZ,HY 4GB,MU CAP,K99 PCBA,MLB,1.4GHZ,HY 4GB,TY CAP,K99 PCBA,MLB,1.4GHZ,SA 2GB,SS CAP,K99 PCBA,MLB,1.4GHZ,SA 2GB,MU CAP,K99 PCBA,MLB,1.4GHZ,SA 2GB,TY CAP,K99 PCBA,MLB,1.4GHZ,SA 4GB,SS CAP,K99 PCBA,MLB,1.4GHZ,SA 4GB,MU CAP,K99 PCBA,MLB,1.4GHZ,SA 4GB,TY CAP,K99 PCBA,MLB,1.4GHZ,MI 2GB,SS CAP,K99 PCBA,MLB,1.4GHZ,MI 2GB,MU CAP,K99 PCBA,MLB,1.4GHZ,MI 2GB,TY CAP,K99 PCBA,MLB,1.4GHZ,MI 4GB,SS CAP,K99 PCBA,MLB,1.4GHZ,MI 4GB,MU CAP,K99 PCBA,MLB,1.4GHZ,MI 4GB,TY CAP,K99 PCBA,MLB,1.4GHZ,EL 2GB,SS CAP,K99 PCBA,MLB,1.4GHZ,EL 2GB,MU CAP,K99 PCBA,MLB,1.4GHZ,EL 2GB,TY CAP,K99 PCBA,MLB,1.4GHZ,EL 4GB,SS CAP,K99 PCBA,MLB,1.4GHZ,EL 4GB,MU CAP,K99 PCBA,MLB,1.4GHZ,EL 4GB,TY CAP,K99
6
TABLE_BOMGROUP_HEAD
5
Bar Code Labels / EEE #s
4
PART NUMBER QTY
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3
REFERENCE DES
[EEE_DX7] [EEE_DD0L] [EEE_DD0M] [EEE_DD0N] [EEE_DD0P] [EEE_DD0Q] [EEE_DD0R] [EEE_DD0T] [EEE_DD0V] [EEE_DD0W] [EEE_DD0X] [EEE_DD0Y] [EEE_DD10] [EEE_DD11] [EEE_DD12] [EEE_DD13] [EEE_DD14] [EEE_DD15] [EEE_DF82] [EEE_DF83] [EEE_DF84] [EEE_DF85] [EEE_DF86] [EEE_DF87] [EEE_DF88] [EEE_DF89] [EEE_DF8C] [EEE_DF8D] [EEE_DF8F] [EEE_DF8G] [EEE_DF8H] [EEE_DF8J] [EEE_DF8K] [EEE_DF8L] [EEE_DF8M] [EEE_DF8N] [EEE_DG4G] [EEE_DG4H] [EEE_DG4J] [EEE_DG4K] [EEE_DG4M] [EEE_DG4N] [EEE_DG4P] [EEE_DG4Q] [EEE_DG4R] [EEE_DG4L] [EEE_DG4T] [EEE_DG4V]
2
BOM OPTION
EEE:DX7 EEE:DD0L EEE:DD0M
BOM NUMBER
639-0651 639-1055 639-1048 639-1043 639-1044 639-1039
BOM OPTIONS
TABLE_BOMGROUP_ITEM
DESCRIPTION
LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99 LABEL,MLB,K16/K99
CRITICAL
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
DRAM CFG CHART

VENDOR CFG 1 CFG 0 HYNIX 0 0
K99_CMNPTS,CPU:1.6GHZ,EEE:DX7,DDR3:HYNIX_2GB,CAPS:SS
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.6GHZ,EEE:DD15,DDR3:HYNIX_2GB,CAPS:MU K99_CMNPTS,CPU:1.6GHZ,EEE:DD0X,DDR3:HYNIX_2GB,CAPS:TY
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0Q,DDR3:HYNIX_4GB,CAPS:SS K99_CMNPTS,CPU:1.6GHZ,EEE:DD0R,DDR3:HYNIX_4GB,CAPS:MU
TABLE_BOMGROUP_ITEM
EEE:DD0N EEE:DD0P EEE:DD0Q
825-7557 825-7557
TABLE_BOMGROUP_ITEM
SAMSUNG
1 0 1
0 1 1
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0L,DDR3:HYNIX_4GB,CAPS:TY K99_CMNPTS,CPU:1.6GHZ,EEE:DD0T,DDR3:SAMSUNG_2GB,CAPS:SS
TABLE_BOMGROUP_ITEM
MICRON
825-7557 825-7557 EEE:DD0R EEE:DD0T EEE:DD0V
639-1045 639-1054 639-1049 639-1052 639-1046 639-1040 639-1042 639-1053 639-1047 639-1051 639-1041 639-1050 639-1446 639-1438 639-1444 639-1449 639-1448 639-1445
D
DIE REV CFG 3
K99_CMNPTS,CPU:1.6GHZ,EEE:DD14,DDR3:SAMSUNG_2GB,CAPS:MU
TABLE_BOMGROUP_ITEM
ELPIDA
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0Y,DDR3:SAMSUNG_2GB,CAPS:TY
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
SIZE
EEE:DD0W EEE:DD0X EEE:DD0Y 825-7557
CFG 2
K99_CMNPTS,CPU:1.6GHZ,EEE:DD12,DDR3:SAMSUNG_4GB,CAPS:SS K99_CMNPTS,CPU:1.6GHZ,EEE:DD0V,DDR3:SAMSUNG_4GB,CAPS:MU
TABLE_BOMGROUP_ITEM
2GB 4GB
A B
0 1
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0M,DDR3:SAMSUNG_4GB,CAPS:TY
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0P,DDR3:MICRON_2GB,CAPS:SS K99_CMNPTS,CPU:1.6GHZ,EEE:DD13,DDR3:MICRON_2GB,CAPS:MU
TABLE_BOMGROUP_ITEM
EEE:DD10 EEE:DD11 EEE:DD12 EEE:DD13 EEE:DD14 EEE:DD15 EEE:DF82 EEE:DF83 EEE:DF84 EEE:DF85 EEE:DF86 EEE:DF87 EEE:DF88 EEE:DF89 EEE:DF8C EEE:DF8D EEE:DF8F EEE:DF8G EEE:DF8H EEE:DF8J EEE:DF8K EEE:DF8L EEE:DF8M EEE:DF8N EEE:DG4G EEE:DG4H EEE:DG4J EEE:DG4K EEE:DG4M EEE:DG4N EEE:DG4P EEE:DG4Q EEE:DG4R EEE:DG4L EEE:DG4T EEE:DG4V
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0W,DDR3:MICRON_2GB,CAPS:TY K99_CMNPTS,CPU:1.6GHZ,EEE:DD11,DDR3:MICRON_4GB,CAPS:SS
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.6GHZ,EEE:DD0N,DDR3:MICRON_4GB,CAPS:MU K99_CMNPTS,CPU:1.6GHZ,EEE:DD10,DDR3:MICRON_4GB,CAPS:TY
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.6GHZ,EEE:DG4Q,DDR3:ELPIDA_2GB,CAPS:SS K99_CMNPTS,CPU:1.6GHZ,EEE:DG4G,DDR3:ELPIDA_2GB,CAPS:MU
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.6GHZ,EEE:DG4N,DDR3:ELPIDA_2GB,CAPS:TY K99_CMNPTS,CPU:1.6GHZ,EEE:DG4V,DDR3:ELPIDA_4GB,CAPS:SS
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.6GHZ,EEE:DG4T,DDR3:ELPIDA_4GB,CAPS:MU K99_CMNPTS,CPU:1.6GHZ,EEE:DG4P,DDR3:ELPIDA_4GB,CAPS:TY
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
607-6999 085-1121 639-1355 639-1341 639-1353 639-1350 639-1356 639-1348 639-1349 639-1351 639-1357 639-1344 639-1352 639-1354 639-1342 639-1346 639-1343
K99_COMMON K99_DEVEL:ENG
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8L,DDR3:HYNIX_2GB,CAPS:SS K99_CMNPTS,CPU:1.4GHZ,EEE:DF83,DDR3:HYNIX_2GB,CAPS:MU
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8J,DDR3:HYNIX_2GB,CAPS:TY K99_CMNPTS,CPU:1.4GHZ,EEE:DF8F,DDR3:HYNIX_4GB,CAPS:SS
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8M,DDR3:HYNIX_4GB,CAPS:MU K99_CMNPTS,CPU:1.4GHZ,EEE:DF8C,DDR3:HYNIX_4GB,CAPS:TY
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8D,DDR3:SAMSUNG_2GB,CAPS:SS K99_CMNPTS,CPU:1.4GHZ,EEE:DF8G,DDR3:SAMSUNG_2GB,CAPS:MU
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8N,DDR3:SAMSUNG_2GB,CAPS:TY K99_CMNPTS,CPU:1.4GHZ,EEE:DF86,DDR3:SAMSUNG_4GB,CAPS:SS
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.4GHZ,EEE:DF8H,DDR3:SAMSUNG_4GB,CAPS:MU K99_CMNPTS,CPU:1.4GHZ,EEE:DF8K,DDR3:SAMSUNG_4GB,CAPS:TY
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.4GHZ,EEE:DF84,DDR3:MICRON_2GB,CAPS:SS K99_CMNPTS,CPU:1.4GHZ,EEE:DF88,DDR3:MICRON_2GB,CAPS:MU
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.4GHZ,EEE:DF85,DDR3:MICRON_2GB,CAPS:TY K99_CMNPTS,CPU:1.4GHZ,EEE:DF89,DDR3:MICRON_4GB,CAPS:SS
TABLE_BOMGROUP_ITEM
639-1347 639-1345 639-1340 639-1442 639-1443 639-1447 639-1441 639-1439 639-1440
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.4GHZ,EEE:DF87,DDR3:MICRON_4GB,CAPS:MU K99_CMNPTS,CPU:1.4GHZ,EEE:DF82,DDR3:MICRON_4GB,CAPS:TY
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.4GHZ,EEE:DG4L,DDR3:ELPIDA_2GB,CAPS:SS K99_CMNPTS,CPU:1.4GHZ,EEE:DG4M,DDR3:ELPIDA_2GB,CAPS:MU
TABLE_BOMGROUP_ITEM
825-7557 825-7557
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.4GHZ,EEE:DG4R,DDR3:ELPIDA_2GB,CAPS:TY K99_CMNPTS,CPU:1.4GHZ,EEE:DG4K,DDR3:ELPIDA_4GB,CAPS:SS
TABLE_BOMGROUP_ITEM
825-7557
K99_CMNPTS,CPU:1.4GHZ,EEE:DG4H,DDR3:ELPIDA_4GB,CAPS:MU
TABLE_BOMGROUP_ITEM
K99_CMNPTS,CPU:1.4GHZ,EEE:DG4J,DDR3:ELPIDA_4GB,CAPS:TY
Sub-BOMs
PART NUMBER
QTY
1 1
DESCRIPTION
K99 MLB DEVELOPMENT BOM CMN PTS,PCBA,MLB,K99
REFERENCE DES
DEVEL CMNPTS
CRITICAL
CRITICAL CRITICAL
BOM OPTION
DEVEL_BOM K99_CMNPTS
085-1121 607-6999
SYNC_MASTER=K6_MLB
PAGE TITLE
K99 BOM Variants

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

4 OF 110
SHEET
4 OF 73
8
Programmable Parts
4
Module Parts
3
QTY
1 1 1 1 1 1 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1 1 1
2
REFERENCE DES
U1000 U1000 U1000 U1400 U1400 U1400 U3100,U3110,U3120,U3130 U3200,U3210,U3220,U3230 U3300,U3310,U3320,U3330 U3400,U3410,U3420,U3430 U3100,U3110,U3120,U3130 U3200,U3210,U3220,U3230 U3300,U3310,U3320,U3330 U3400,U3410,U3420,U3430 U3100,U3110,U3120,U3130 U3200,U3210,U3220,U3230 U3300,U3310,U3320,U3330 U3400,U3410,U3420,U3430 U3100,U3110,U3120,U3130 U3200,U3210,U3220,U3230 U3300,U3310,U3320,U3330 U3400,U3410,U3420,U3430 U3100,U3110,U3120,U3130 U3200,U3210,U3220,U3230 U3300,U3310,U3320,U3330 U3400,U3410,U3420,U3430 U3100,U3110,U3120,U3130 U3200,U3210,U3220,U3230 U3300,U3310,U3320,U3330 U3400,U3410,U3420,U3430 U3100,U3110,U3120,U3130 U3200,U3210,U3220,U3230 U3300,U3310,U3320,U3330 U3400,U3410,U3420,U3430 U3100,U3110,U3120,U3130 U3200,U3210,U3220,U3230 U3300,U3310,U3320,U3330 U3400,U3410,U3420,U3430 U7000 U7000 J6955
1
BOM OPTION
CPU:1.2GHZ CPU:1.6GHZ CPU:1.4GHZ MCP89U:A01 MCP89U:A02 MCP89U:A03 DRAM_TYPE:HYNIX_2GB DRAM_TYPE:HYNIX_2GB DRAM_TYPE:HYNIX_2GB DRAM_TYPE:HYNIX_2GB DRAM_TYPE:SAMSUNG_2GB DRAM_TYPE:SAMSUNG_2GB DRAM_TYPE:SAMSUNG_2GB DRAM_TYPE:SAMSUNG_2GB DRAM_TYPE:MICRON_2GB DRAM_TYPE:MICRON_2GB DRAM_TYPE:MICRON_2GB DRAM_TYPE:MICRON_2GB DRAM_TYPE:ELPIDA_2GB DRAM_TYPE:ELPIDA_2GB DRAM_TYPE:ELPIDA_2GB DRAM_TYPE:ELPIDA_2GB DRAM_TYPE:HYNIX_4GB DRAM_TYPE:HYNIX_4GB DRAM_TYPE:HYNIX_4GB DRAM_TYPE:HYNIX_4GB DRAM_TYPE:SAMSUNG_4GB DRAM_TYPE:SAMSUNG_4GB DRAM_TYPE:SAMSUNG_4GB DRAM_TYPE:SAMSUNG_4GB DRAM_TYPE:MICRON_4GB DRAM_TYPE:MICRON_4GB DRAM_TYPE:MICRON_4GB DRAM_TYPE:MICRON_4GB DRAM_TYPE:ELPIDA_4GB DRAM_TYPE:ELPIDA_4GB DRAM_TYPE:ELPIDA_4GB DRAM_TYPE:ELPIDA_4GB ISL6259_SCREENED:NO ISL6259_SCREENED:YES
PART NUMBER
338S0563 341T0261 335S0610 341T0262 341T0263
1
DESCRIPTION
CDC,QKWH,QS,1,2,10W,800,R0,1M,BGA
CRITICAL
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
IC,SMC,HS8/2117,9X9MM,TLP,HF
U4900 U4900 U6100 U6100 U6100
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
SMC:BLANK
337S3792
1
IC ASSY,SMC EXTERNAL,K99 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
SMC:PROG
337S3947
1
PDC,SLGFN,PRQ,1,6,10W,R0,3M,BGA
BOOTROM:BLANK
337S3954
1
PDC,SLGAK,PRQ,1,4,10W,R0,3M,BGA
IC ASSY,EFI UNLOCKED,K99
BOOTROM:UNLOCKED
337S3820
1
IC,MCP89U-A01,24.5MMX24.5MM,1244FCBGA
IC ASSY,EFI,LOCKED,K99
BOOTROM:LOCKED
337S3868
Alternate Parts
TABLE_ALT_HEAD
337S3939
PART NUMBER
ALTERNATE FOR PART NUMBER

138S0638 152S0516 152S0586 353S2988 104S0018 107S0075 138S0673 155S0367 376S0610 155S0329 377S0066
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
333S0552 333S0552
TABLE_ALT_ITEM
HYNIX,LVDDR3,1GBIT,7.5X11.0
138S0681 152S0874 152S0847 353S2987 104S0023 107S0139 138S0671 155S0578 376S0926 155S0457 377S0107
ALL
TAIYO YUDEN AS ALTERNATE
ALL
MAGLAYERS AS ALTERNATE
TABLE_ALT_ITEM
333S0552 333S0552
TABLE_ALT_ITEM
ALL
HVDDLDO:FIXED
ALL
TPS71725DCK AS ALTERNATE FOR U2590

TABLE_ALT_ITEM
333S0553 333S0553
SAMSUNG,LVDDR3,1GBIT,7.5X11.0
ALL
CYNTEC/DALE AS ALTERNATES
TABLE_ALT_ITEM
ALL
CYNCTEC AS ALTERNATE
TABLE_ALT_ITEM
333S0553 333S0553
TABLE_ALT_ITEM
ALL
TAIYO AS ALTERNATE
ALL
TAIYO AS ALTERNATE
TABLE_ALT_ITEM
333S0554 333S0554
TABLE_ALT_ITEM
MICRON,LVDDR3,1GBIT,8X11.5
ALL
FAIRCHILD AS ALTERNATE
ALL
TABLE_ALT_ITEM
333S0554 333S0554 333S0565 333S0565 333S0565 333S0565
ALL
ONSEMI AS ALTERNATE
ELPIDA,LVDDR3,1GBIT,7.5X10.6
333S0555 333S0555 333S0555 333S0555 333S0556 333S0556 333S0556 333S0556 333S0557
HYNIX,LVDDR3,2GBIT,9X11.1
BOM Groups
TABLE_BOMGROUP_HEAD
333S0557
BOM GROUP
K99_COMMON K99_MISC K99_PROGPARTS K99_DEVEL:ENG K99_DEVEL:PVT K99_DEBUG:ENG K99_DEBUG:PVT
BOM OPTIONS
TABLE_BOMGROUP_ITEM
333S0557 333S0557
TABLE_BOMGROUP_ITEM
COMMON,ALTERNATE,PROJ:K99,K99_MISC,MCP89U:A03,K99_DEBUG:ENG,K99_PROGPARTS,SPI:41MHZ,LVDDR3:YES,WLAN_PCTL:HW,IPD_5V:S5_INT,IPD_3V3:S5
DP_ESD,DP_PWR:SMC,VFRQ:SLPS3,HVDDLDO:FIXED,MCPHVDD:P2V5,MCPPLL_R:REG,S0PGOOD_BJT,ISL6259_SCREENED:YES,DPI2C:SMC
TABLE_BOMGROUP_ITEM
333S0566 333S0566
TABLE_BOMGROUP_ITEM
ELPIDA,LVDDR3,2GBIT,9X11.5
BOOTROM:UNLOCKED,SMC:PROG BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,MCPPLL_LDO,S3_S0_LED
TABLE_BOMGROUP_ITEM
333S0566 333S0566
TABLE_BOMGROUP_ITEM
LPCPLUS DEVEL_BOM,SMC_DEBUG:YES,XDP
TABLE_BOMGROUP_ITEM
353S2392 353S2929
TABLE_BOMGROUP_ITEM
IC,ISL6259,BATCHARGER,4X4MM,QFN28
DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO
TABLE_BOMGROUP_ITEM
IC,ISL6259,BATCHARGER,3%,4C4MM,QFN28
K99_DEBUG:PROD DDR3:HYNIX_2GB DDR3:SAMSUNG_2GB DDR3:MICRON_2GB DDR3:ELPIDA_2GB DDR3:HYNIX_4GB DDR3:SAMSUNG_4GB DDR3:MICRON_4GB DDR3:ELPIDA_4GB CAPS:SS CAPS:MU CAPS:TY
607-6811
ASSEMBLY,SUBASSY,PCBA HALL EFFECT, K99
DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:HYNIX_2GB
TABLE_BOMGROUP_ITEM
DRAM_CFG0:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_2GB
TABLE_BOMGROUP_ITEM
DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:MICRON_2GB
TABLE_BOMGROUP_ITEM
DRAM_CFG0:H,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_2GB
TABLE_BOMGROUP_ITEM
DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:HYNIX_4GB
TABLE_BOMGROUP_ITEM
DRAM_CFG0:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_4GB
TABLE_BOMGROUP_ITEM
DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:MICRON_4GB
TABLE_BOMGROUP_ITEM
DRAM_CFG0:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_4GB
TABLE_BOMGROUP_ITEM
SS_CAP_2_2UF,SS_CAP_10UF,SS_CAP_1UF,SS_CAP_22UF
TABLE_BOMGROUP_ITEM
MU_CAP_2_2UF,MU_CAP_10UF,MU_CAP_1UF,MU_CAP_22UF
TABLE_BOMGROUP_ITEM
TY_CAP_2_2UF,TY_CAP_10UF,TY_CAP_1UF,TY_CAP_22UF
SYNC_MASTER=K24_MLB
PAGE TITLE
BOM Configuration
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

5 OF 110
SHEET
5 OF 73
8
Revision History
7
NOTE: All page numbers are .csa, not PDF.
-
6
See page 1 for .csa -> PDF mapping.
03/05/2010: RELEASE 0.41.0 (MAJOR)- PAGE 9: ADDED Z0920 (OMIT) APN 998-3068 METAL TAB SYMBOL FOR MDP CONNECTOR - PAGE 19: ADDED 10K R1954 APN 117S0007 PD ON MLB_RAM_CFG0 AS THERE IS NO INTERNAL PD ON GPIO 48 - PAGE 72: RENAMED =P5VS3_EN_L TO =P5VS3_EN AND =P3V3S5_EN_L TO =P3V3S5_EN - PAGE 78: MOVED P3V3S5_EN_L NET FROM PIN 4 TO PIN 3 (NON-INVERTING) AND RENAMED IT TO P3V3S5_EN AS IT IS ACTIVE HIGH SIGNAL. LEFT PIN 4 NC - PAGE 78: NO STUFF C7801 - PAGE 78: ALIASED =P0V9S5_EN TO CONNECT TO =PP3V3_S5_P0V0S5 - PAGE 78: DELETED Q7891 (PINS 3,4,5) SYMBOL AS P5VS3_EN_L IS ACTIVE HIGH SIGNAL (SO NO NEED TO INVERT) AND RENAMED IT TO P5VS3_EN. ALSO, CONNECTED IT TO PM_SLP_S4_L VIA RC NETWORK - R7813 & C7813 - PAGE 78: REPLACED R7813 WITH 0 OHMS APN 117S0002 FOR NOW 03/05/2010: RELEASE 0.42.0 (MAJOR)- PAGE 4: ADDED DRAM_CFG0:L TO RAM TABLES NOT CALLING OUT DRAM_CFG0:H, AND REMOVED DRAM_CFG1:H AS IT IS NO LONGER NEEDED - PAGE 4: DELETED MODULE TABLE ENTRY FOR ZS0907 AS POR SYMBOL IS READY - PAGE 4: ADDED MODULE TABLE ENTRY FOR Z0920 MLB STIFFENER: 806-1176 - PAGE 9: REPLACED ZS0907 WITH POR APN 870-1938 AND DELETED OMIT ATTRIBUTE - PAGE 9: REPLACED POGO PIN ZS0906 WITH APN 870-1938 PER PD - PAGE 19: REMOVED R1955 PULL-UP ON MLB_RAM_CFG1 (INTERNAL PULL-UP) - PAGE 19: CHANGED R1956 PULL-DOWN TO 470 OHMS (STRONGER PD VS 8.5K PU) APN 117S0103 - PAGE 19: REPLACED R1957 WITH 10K APN 117S0007 TO BE CONSISTENT - PAGE 78: ADDED BYPASS PROPERTIES TO C7895 AND C7896 - PAGE 78: CHANGED BASE NET FOR PM_SLP_S4_DLY_L PER WILL 03/05/2010: RELEASE 0.43.0 (MAJOR)- PAGE 2: REPLACED THIS PAGE WITH QUANTAS UPDATED ONE - PAGE 4: SWITCHED BOM TABLE TO USE SCREENED ISL6259 PART - PAGE 4: ADDED APN 376S0895 UNDER MODULE PART TABLE FOR Q7220 & Q7225 PER DAYU FOR PART SUPPLY ISSUE - PAGE 4: MOVED SMS_YES BOM OPTION FROM K99_MISC TO DEVEL_BOM - PAGE 4: UPDATED MICRON 2GB APN 333S0557 IN THE BOM TABLE - PAGE 9: FIXED MCPCOREISNS SIGNALS ALIASES PER WILLS CHANGES ON K16 - PAGE 39: REMOVED CRITICAL ATTRIBUTE FROM THE BOM TABLE AS IT IS NOT NEEDED - PAGE 70: NO STUFF Q7080, D7005,Q7055 AND F7040 FOR NON-FUNCTIONAL BOARD - PAGE 72: ADDED OMIT BOM OPTION TO Q7220 & Q7225 AS SYMBOL IS NOT READY - PAGE 72: CHANGED R7246 AND R7247 TO 1.69K, 1% APN 118S0134 PER VENDOR - PAGE 72: CHANGED R7216 AND R7256 TO 4.02K, 1% APN 118S0354 PER VENDOR - PAGE 72: CHANGED C7237 AND C7239 TO 1000PF, 10% APN 132S0122 PER VENDOR - PAGE 76: CHANGED OCP TEXT NOTE PAR VENDOR - PAGE 76: CHANGED R7641 AND R7642 TO 1.78K, 1% APN 118S0144 PER VENDOR - PAGE 78: ADDED NC SYMBOL TO PIN 5 OF U7896 03/07/2010: PROTO1 NON-FUNCTIONAL AGILE RELEASE 1.0.0 (FAB)- NON-FUNCTIONAL PROTO 1 OK2FAB RELEASE!!! 3/19/2010: RELEASE 1.1.0 (MAJOR)- PAGE 4: REMOVED SMS_YES BOM OPTION FROM K99_DEVEL:ENG BOM GROUP. INSTEAD, ADDED SMS:NO TO K99_MISC [ALSO SEE BELOW CHANGES FOR PAGES 50,59] - PAGE 50: ADDED BOM OPTION ATTRIBUTE SMS:NO TO R5093 PU ON SMS_INT_L. IDEA IS TO PULL THIS NET TO S5 RAIL WHEN SMS IN NOT STUFFED, ELSE PU TO S3 RAIL (PAGE 59) PER RADAR 7765442 - PAGE 52: CONNECTED SMC 0 SMBUS INTERFACE TO THE TCON-A CHIP IN THE INTERNAL DISPLAY. ALSO, PROVIDED 0 OHMS STUFFING OPTIONS TO BE DRIVEN FROM MCP89 0 SMBUS [R5240-R5243 APN 117S0002] PER RADAR 7749046 - PAGE 59: REPLACED BOM OPTION SMS_YES WITH SMS:YES - PAGE 59: ADDED 10K R5924 PU ON SMS_INT_L TO =PP3V3_S3_SMS WITH BOM OPTION ATTRIBUTE SMS:YES PER RADAR 7765442 - PAGE 70: STUFF BACK Q7080, D7005,Q7055 AND F7040 - PAGE 75: REPLACED L7560 WITH 10X10X3MM APN 152S1236 PER RADAR 7769386 - PAGE 90: ROUTED NEWLY ADDED =I2C_TCON_SDA/SCL TO PINS 1 & 30 OF J9000 RESPECTIVELY PER RADAR 7749046 - PAGE 93: ADDED 3300PF APN 132S0241 C9302 CAP ON DP_CA_DET TO GND PER RADAR 7742010 - PAGE 108: ADDED SMBUS_SMC_0_S0_SCL/SDA_R CONSTRAINTS SET
03/30/2010: Release 1.5.0 (MAJOR)Page 4: Deleted 376S0895 alternate part entry to avoid mixing of vendors between high & low side FETs, per Dayu Page 4: Deleted DPI2C:SMC BOM OPTION as eDP I2C Bus wont be routed on Proto 1 Page 4: Changed BOM OPTION SPI:25MHz to 62MHz Page 9: Changed BOM OPTION attribute of ZS0904 to OMIT_TABLE Page 10-11: Changed BOM OPTION attribute of U1000 to OMIT_TABLE Page 14-20: Changed BOM OPTION attribute of U1400 to OMIT_TABLE Page 25: Changed BOM OPTION attribute of C2600 to OMIT_TABLE Page 31-34: Changed BOM OPTION attribute of U3100-U3430 to OMIT_TABLE Page 35-36: Changed BOM OPTION attribute of all caps to OMIT_TABLE Page 49: Changed BOM OPTION attribute of U4900 to OMIT_TABLE Page 52: Changed R5290 & R5291 to 2K APN 118S0174 per RADAR# 7810865 Page 61: Changed BOM OPTION attribute of U6100 to OMIT_TABLE Page 69: Changed R6905 to 10 Ohms APN 101S0089 & C6990 to 2.2uF APN 138S0672 to improve noise immunity & reduce inrush stress, per Dayu - Page 69: Changed BOM OPTION attribute of U6955 to OMIT_TABLE - Page 69: Changed BOM OPTION attribute of C6999 to OMIT_TABLE - Page 70: Changed BOM OPTION attribute of U7000 to OMIT_TABLE - Page 72: Replaced Q7220 & Q7225 with APN 376S0895 (RJK03E0) per Dayu - Page 72: Changed R7220 to 41.2K APN 118S0360 to boost 5V, per Dayu - Page 73: Replaced Q7330 with APN 376S0749 (SIS426) per Dayu - Page 76: Replaced Q7630 & Q7635 with APN 376S0895 (RJK03E0) per Dayu - Page 77: Changed R7751 to 2.55K APN 118S0234 & R7752 to 20K APN 118S0175 to improve noise immunity & reduce inrush stress, per Dayu 03/31/2010 - Proto 1 Agile Release 2.0.0 (FAB) - Proto 1 Ok2FAB Agile Release!!! 3/31/2010: Proto 1+ Release 2.1.0 (MAJOR) - Page 4: Activated PROJ:K99 BOMOPTION to select proper APN for U9701 - Page 97: Changed BOM OPTION attribute of C9797 to OMIT_TABLE after syncing from K16 ***Synced from K16*** -Page 90: Added Q9090 isolation FET to support LCD panel power-down per radar 7761747 -Page 97: Reversed previous change, U9701 back to 353S2896, handled via a table now to support/clarify different values for K16/K99 -Page 108: Added constraints for new nets on page90, I2C_TCON_SCL/SDA_CONN per radar 7761747 3/31/2010: Proto 1+ Release 2.2.0 (MAJOR) - Page 97: Swapped pins of R9700 to match original orientation before syncing with K16 - Page 97: Deleted OMIT_TABLE BOM option attribute from C9797 and replaced it with actual POR APN 138S0673 symbol. Also, deleted it from BOM table as it is no longer required 5/12/2010: Proto 1+ Agile Release 3.0.0 (FAB) - Proto 1+ OK2FAB Agile Release!!! 5/17/2010: Release 3.1.0 (Major)<rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V - Page 4: Added APNs 353S2987 & 353S2988 as alternates for 353S2986 <rdar://problem/7964678> K99 MLB BOM: Change MCP APN to A03 version - Page 4: Added MCP89U:A03 BOM table. Changed K99_Common to call out A03 <rdar://problem/7861271> K99 MLB: Set SPI operating frequency to 42MHz <rdar://problem/7851979> K16/K99: Set SPI operating frequency to 42Mhz - Page 4: Changed SPI:62Mhz to SPI:41MHZ BOM option <rdar://problem/7838450> K99 MLB: WoW / WoL power control architecture change - Page 4: Added WLAN_PCTL:HW to K99_Common <rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD <rdar://problem/7953783> K99 IPD power regulator new design - Page 4: Added IPD_PWR:S5 to K99_Common - Page 8: Aliased =PPBUS_5V_S5 to PPBUS_G3H signal <rdar://problem/7825507> K99 MLB BOM: Change label P/N - Page 4: Replaced label APN 826-4393 with 825-7557 <rdar://problem/7749046> K99 MLB: Connect SMBUS to internal display connector - Page 7: Renamed PP3V3_LCDVDD_SW_F to PP3V3_SW_LCD to match page 90, making it
<rdar://problem/7963570> K99 MLB: Remove SMS circuit from layout - Page 4: Deleted SMS:NO BOM option as SMS has been removed - Page 50: Deleted BOM option SMS:NO from R5093 - Page 52: Deleted Accelerometer block from the SMBUS page <rdar://problem/8007333> K99 MLB: Stuff R7872 to enable output connection of ISL power monitor to ALL_SYS_PWRGD - Page 78: Added BOM option S0PGOOD_ISL to R7872 <rdar://problem/7993210> K99 MLB: Cosmetic updates - Page 8: Added =PP3V3_S3_DBGLEDS alias to =PP3V3_S3_FET for debug LEDS (like K16) - Page 57: Changed PP3V3_S5_TPAD_CONN to PP3V3_TPAD_CONN - Page 69: Renamed PP3V3_S3 going to debug LEDs to =PP3V3_S3_DBGLEDS <rdar://problem/8007524> K99 MLB: Stuff C9799 to provide better phase margin - Page 97: Stuff C9799 <rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements - Page 8: Changed min neck width of PP3V3_S3 to 0.1mm - Page 8: Changed min neck width of PP5V3_S3 to 0.2mm - Page 74: Deleted IMVP6_CS_P/N & IMVP6_CS_R_P/N nets from the constraints set as the bottom of the page - Page 97: Changed min neck width of PPBUS_SW_BKL to 0.25mm 05/19/2010: Release 3.3.0 (Major)<rdar://problem/7993210> K99 MLB: Cosmetic updates - Page 69: Fixed netname =PP3V3_S3_DBGLEDs (= sign was missing) 05/21/2010: Release 3.4.0 (Major)<rdar://problem/7993210> K99 MLB: Cosmetic updates - Page 2: Updated CPU block to reflect 1.6GHz <rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD - Page 4: Changed IPD_PWR:S5 to IPD_5V:S5_INT BOM option to use internal LDO of 5V/3.3V switcher for IPD 5V supply <rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep - Page 4: Added IPD_3V3:S5 BOM option under K99_COMMON to select 3.3V S5 power supply - Page 7: Renamed =PP3V3_S3_TPAD to PP3V3_TPAD_CONN and =PP5V_S3_TPAD TO PP5V_TPAD_FILT - Page 8: Added =PP3V3_SMC_PME alias to PP3V3_S5 <rdar://problem/8009884> K99 MLB: Add new CPU APN for U1000 - Page 4: Added SU9600 CPU APN 337S3947 1.6GHz to the module part table. And, updated BOM variant table to call out this new APN <rdar://problem/8011930> K99 MLB: Remove SIL BOM option as SIL is not POR - Page 4: Removed SIL BOM option from the development BOM <rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements - Page 8: Changed min neck width of PP3V3_S3 to 0.1mm - Page 40: Deleted line/neck width attributes from =PP3V3_S3_WLAN as duplicates <rdar://problem/7825507> K99 MLB BOM: Change label P/N - Fixed typo in APN (first column) <rdar://problem/7986457> K99 MLB: Change LIO Flex connector J4700 to accommodate new LIO - Page 47: Connected pin 38 to GND <rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V - Page 4: Added APN 353S2988 (MICREL) as an alternate for 353S2986 - Page 4: Added APN 353S2987 (TI) as an alternate for 353S2986 - Page 4: Deleted APN 353S3047 entry from the alternate table - Page 25: Reverted U2590 back to the 2.5 LDO APN 353S2988 - Page 25: Replaced APN 353S3048 with 353S2986 in the BOM table for U2590 as primary for HVDDLDO:FIXED ***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16 - changes below*** ** Didnt sync page 52 as K16 need to sync it first from K99 to remove accelerometer** ** Didnt sync page 25 as K16 need to sync it first from K99 to revert to 2.5 LDO** ** Didnt sync page 40 as K16 needs to sync it first from K99 for above change** <rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements - Page 24: Changed PPVCORE_SW_MCP_GFX min neck width to 0.12mm for routing <rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD - Page 77: Changed IPD_PWR:S5 to IPD_5V:S5_EXT BOM option - Page 77: Changed IPD_PWR:S3 to IPD_5V:S3 BOM option - Page 77: Added R7761 0 ohm bypass option to use internal LDO of 5V/3.3V switcher for IPD 5V supply. Added BOM option IPD_5V:S5_INT to R7761 - Page 77: Added place near J5700.10:1.5mm to R7761 to avoid long stub <rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep - Page 49: Changed port P92 from SMC_BS_ALRT_L to SMC_PME_S4_L - Page 50: Changed R5076 to a PU to =PP3V3_SMC_PME. And, renamed SMC_BS_ALERT_L to SMC_PME_S4_L - Page 57: Changed IPD_PWR:S5 to IPD_3V3:S5 BOM option - Page 57: Changed IPD_PWR:S3 to IPD_3V3:S3 BOM option - Page 57: Removed U5750, R5751,R5750 and C5750 USB_IPD Debug Mux as it is not needed - Page 57: Renamed pins 5 & 6 to USB_TPAD_CONN_P/N as before - Page 57: Renamed pin 10 to PP5V_TPAD_FILT - Page 78: Removed =USB_TPAD_MUX_EN alias to DDREG_EN as MUX has been removed <rdar://problem/7779132> K99 MLB: Implement deeper sleep S4 state - Page 19: Added alias for PM_SLP_S4_L to PM_SLP_S5_L - Page 49: Changed port P94 from SMC_DP_HPD_L to PM_SLP_S4_L - Page 49: Changed port P95 from PM_SLP_S4_L to PM_SLP_S5_L - Page 49: Changed port PB6 from SMC_PB6 to SMC_DP_HPD_L - Page 50: Removed R5095 PU resistor on SMC_PB6
07/07/2010: Release 4.2.0 (MAJOR)<rdar://problem/7993210> K99 MLB: Cosmetic updates - Moved BOM group table on page 4 to page 5 for space limitations <rdar://problem/8065425> K99 MLB: Add new CPU APN for U1000 - SU9400 - Page 4: Updated SU9400 BOMs with correct EEEEs (Elpidas still pending) - Page 4: Updated Label table with correct EEEEs for SU9400 configs <rdar://problem/8151087> K99 MLB BOM: Add new Elpida 2Gb memory - Page 4: Added 12 new BOMs corresponding to Elpida 2GB and 4GB configs - Page 5: Added DDR3:ELPIDA_4GB BOM group - Page 5: Added DRAM_TYPE:ELPIDA_4GB BOM option to the Module Parts table (2Gb APN is not ready yet- using 2Gb Micron APN as a placeholder) <rdar://problem/8168390> K99 MLB BOM: Swap 155S0556-> 155S0578, fix 0402 pad with 0603 - Page 5: Changed 155S0556 to 155S0578 to address the 0603 0402 mismatch alternate parts <rdar://problem/8151651> K99 MLB BOM: Reduce CPU VCORE 0603 bypass caps - Page 12: Changed BOM option attribute of C1200,C1201,C1202,C1203,C1204, C1205,C1206,C1207,C1208,C1209,C1211,C1212,C1213,C1215,C1216, C1219, C1220,C1221,C1222,C1224,C1225,C1228,C1229,C1231 from OMIT_TABLE to NOSTUFF ***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16*** <rdar://problem/8118512> K99 MLB BOM: Swap 155S0423 -> 155S0559, Supply Constraint (TDK) - Page 90: Changed FL9000, FL9001 from 155S0423 to 155S0559 - Page 94: Changed FL9400-FL9403 from 155S0423 to 155S0559 <rdar://problem/8151651> K99 MLB BOM: Reduce CPU VCORE 0603 bypass caps - Page 110: Removed caps listed above on page 12 from the BOM table as these would get NOSTUFFed 7/12/2010: Release 4.3.0 (MAJOR)<rdar://problem/8151087> K99 MLB BOM: Add new Elpida 2Gb memory - Page 4: Updated BOM options table with correct EEEEs for Elpida configs - Page 4: Added label table with correct EEEEs for Elpida configs - Page 5: Updated Elpida 2Gb configs with correct APN 333S0566 <rdar://problem/8180364> K99 MLB BOM: Remove 806-1176 stiffener - Page 9: Deleted CRITICAL attribute from MT0900 and NOSTUFFed it 7/22/2010: Release 4.4.0 (MAJOR)<rdar://problem/8175202> K99 MLB: Move MCP Temp Sensor to SMC B SMBUS - Page 52: Move MCP TEMP I2C connections to SMC B Bus - Page 52: NOSTUFFed R5250 & R5251 - Page 52: Changed MCP TEMP I2C address note to reflect 0XD8/0XD9 - Page 55: Changed R5536 to 15K APN 118S0105 to set ADDR = 0XD8/0XD9. Updated schematic note too for address <rdar://problem/8141673> K99 MLB: Change eDP connector J9000 pinout - Page 90: Changed pine 2 to NC and connected pin 4 to PPVOUT_SW_LCDBKLT Flex <rdar://problem/8224515> K99 MLB: Remove Q9090 isolation FET - Page 90: Removed Q9090 FET and directly connected TCON I2C bus J9000 - Page 90: Deleted =I2C_TCON_SCL/SDA_CONN net names and kept =I2C_TCON_SCL/SDA <rdar://problem/8224857> K99 MLB: Replace APN 155S0559 with 155S0423 (incompatible pad sizes) - Page 90: Changed FL9000 and FL9001 back to the original APN 155S0423 - Page 94: Changed FL9400-FL9403back to the original APN 155S0423 <rdar://problem/8224921> K99 MLB: Change R9714 (BKLT_ISET) resistor to 18.2K 1% APN 118S0155 - Page 97: Change R9714 to 18.2K 1% APN 118S0155 <rdar://problem/7993210> K99 MLB: Cosmetic updates - Page 97: Fixed schematic note - I_LED=369/Riset
03/24/2010: Release 1.2.0 (MAJOR)- Text sizes have been fixed - safe to sync - Page 8: Renamed PP3V3_S5_LCD to PP3V3_S0_LCD - Page 8: Moved PP3V3_S0_LCD & PP3V3_S5_DP_PORT_PWR to S5 rail - Page 7: Added =I2_TCON_SCL/SDA FCTs under INT DP FUNC_TEST group - Page 12: After syncing from K16, deleted C1273 as it NA to K99 - Page 90: After syncing, renamed PP3V3_S5_LCD to PP3V3_S0_LCD ***Synced ALL but pages 1-9,28,47,69,70,74,75 and 97 from K16*** *Please NOTE that some of the below changes were already part of 1.1 release. Below list depicts all the changes since 3/1 K16 release * - Page 12: Fixed invisible pins on CPU bypass caps. Also changed all OMITs to OMIT_TABLEs and performed other cleanup - Page 14: Swapped BCLK_IN_N/P after library symbol refresh - Page 17: Added CKPLUS_WAIVE properties to VDD_IFPx pins that are legally grounded on K16 - Page 19: Removed PM_SLP_S5_L alias. Other cleanup to make all CRefs visible - Page 19: Removed pull-up on MLB_RAM_CFG1 (internal pull-up), changed pull-down to 470 ohms. Added pull-down on MLB_RAM_CFG0, made both pull-up and pull-down 10K - Page 25: Added MCPHVDD LDO, SC-70 version. Added 1uF 0201 input cap and 10K pull-up resistor, BOMOPTIONed same as LDO. L2590 retained with MCPHVDD:P3V3 BOMOPTION - Page 25: Added voltage divider for HVDD LDO. OMIT_TABLEd U2590, added tables for fixed (2.5V Intersil) and adjustable (TI) regulators - Page 39: Removed CRITICAL flag from 0-ohm resistor table - Page 49: PB3 changed from SMC_DRAM_S3_PWRDN to SMC_SLPS5_L. P74 changed from PM_SLP_S4_L to SMC_DP_HPD_L. P75 changed from PM_SLP_S5_L to PM_SLP_S4_L - Page 49: C4902 changed from 0805 to 0603 to free up some layout space for MCP VCore regulator - Page 50: Added SMS:NO BOMOPTION to SMS_INT_L pull-up. Other cleanup including deleting unused alias for SMC_PB3 - Page 50: Added 2 resistors to control DP_PWR and one to connect DP_EXT_HPD_L to SMC. Updated netname on R5090 and added BOMOPTION of DP_PWR:S0 - Page 52: Added TCON I2C block and Rs to connect to SMC 0 and MCP 0 - Page 53: Removed PP prefix from non-power nets. Added OMIT_TABLE to buses. Other cosmetic cleanup including grid compliance C5310 for vendor control - Page 59: Synced with K99 (adds R5924, S3 pull-up on SMS_INT_L), plus lots of cleanup including removing PP prefix from signal net, correcting BYPASS & PLACE_NEAR properties, correcting offpages, etc - Page 72: Changed Q7220 & Q7225 to 376S0895 per Dayus request. Fixed netnames on switcher enables, removing _L suffixes since they are active-high - Page 72: Value changes to C7237/C7239/R7216/R7246/R7247/R7256 per Dayu. Changed C7288 to match C7218. Removed alias that was serving no purpose and was incorrect since it lacked a MAKE_BASE anyhow - Page 76: Value changes to R7641/R7642 and OCP note correction per Dayu - Page 78: Removed RAM power-down circuit, reconnecting =DDRREG_EN to original net - Page 78: Disconnected half of Q7891 from 5V S3 power sequencing, gate left indicated as unused. Removed inverter from P5VS3_EN and reconnected P3V3S5_EN to be non-inverted. R7813 changed from pull-up to series R (0-ohms). P0V9S5_EN changed to alias to 3.3V S5 rail. Cleaned up page including fixing grid issues. Added BYPASS properties to C7895 and C7896. Changed base net for PM_SLP_S4_DLY_L - Page 93: Added RC between DP_CA_DET and DDC bypass FETs. Also cleaned up page, adding offpages, fixed grid issues, made power nets convention-compliant and added note about DP_CA_DET pull-up / FET Vgs reqirements - Page 93: Added RC between DP_CA_DET and DDC bypass FETs. Also cleaned up page, adding offpages, fixed grid issues, made power nets convention-compliant and added note about DP_CA_DET pull-up / FET Vgs reqirements - Page 93: Added CKPLUS_WAIVE properties to _P nets connecting to FET DRAIN pins - Page 94: Renamed DP_PWR nets to indicate SW state instead of S0. Switch input changed from PM_SLP_S3_L to =DP_PWR_EN. HPD_L netname changed, offpage added and pull-up changed to DP_PWR. Other cleanup including removing PLACE_NEARs that should be handled via constraints, OMIT_TABLEs for caps, CRITICAL flags on common-mode chokes and cosmetic changes - Page 108: Added net constraints for diffpairs reported by diffpNoPhysNet report (except for 4 false errors). Other cleanup including removing some unnecessary net properties 03/25/2010: Release 1.3.0 (MAJOR)- Page 4: Fixed DRAM CFG table - swapped CFG 1 and 0 columns - Page 4: Updated EEE numbers - Page 4: Pulled new 607-XXXX APN and added K99_CMNPTS BOM option corresponding to this new sub-BOM consisting of common parts between 18 BOMs - Page 4: Replaced K99_COMMON with K99_CMNPTS in the BOM variant table - Page 4: Replaced K99_SS/MU/TY_CAP BOM option with better nomenclature CAPS:SS/MU/TY - Page 4: Removed K99_ prefix from K99_DDR3_ BOM Group - Page 4: Deleted 376S0895 APN module parts table entry as it is already duplicated on page 72 - Page 4: Deleted module table entry for 806-1176 as actual symbol has been added - Page 9: Replaced Z0920 with POR stiffener symbol for APN 806-1176 and deleted OMIT - Page 46: Replaced Q4690 with single port switch APN 353S1930 (Higher DCR) to fix USB short issue - Page 46: Changed BOM attribute OMIT to OMIT_TABLE for C4690 & C4695 - Page 54: Changed R5418 to 4.53K 0201 APN 118S0384 - Page 54: Changed R5471 to 4.53K 0402 APN 114S0281 - Page 72: Changed R7246, R7247 to 1.87K, 1% APN 118S0159 per Dayu - Page 72: Changed R7216, R7256 to 3.16K, 1% APN 118S0289 per Dayu - Page 72: Changed C7236, C7238 to 0.01uF, 10% APN 132S0097 per Dayu - Page 72: Changed C7237, C7239 to 100pF, 10% APN 131S0287 per Dayu - Page 97: Replaced U9701 with new improved E00 version APN 353S2967 - Page 97: Changed R9704 to 33 ohms APN 117S0080 per Kiran - Page 97: Stuffed C9704 per Kiran 3/26/2010: Release 1.4.0 (MAJOR)- Page 4: Added 376S0895 as an alternate for 376S0749 per Dayu - Page 4: Added 138S0681 as an alternate for 138S0638 per GSM - Page 4: Added 138S0676 as an alternate for 138S0635 per GSM - Page 4: Removed alternates that were NA to K99 - Page 72: Deleted OMIT_TABLE attribute from Q7220 & Q7225. Also deleted the BOM table. Plan is to use 376S0895 as alternate instead
convention compliant power net convention compliant power net
<rdar://problem/7779132> K99 MLB: Implement deeper sleep S4 state - Page 7: Renamed PP3V3_S0_DPPWR to PP3V3_SW_DPPWR to match page 94 changes, making it
<rdar://problem/7993210> K99 MLB: Cosmetic updates - Page 7: Removed SYS_LED_ANODE_R - Page 8: Removed =PP3V3_S5_PWRCTL alias <rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep - Page 8: Added =PP3V3_S5_TPAD to PP3V3_S5 net <rdar://problem/7963570> K99 MLB: Remove SMS circuit from layout - Page 59: Deleted csa page as SMS is no longer POR <rdar://problem/7795028> K99 MLB: 5V/3V3 power supply BOM changes per characterization - Page 74: Changed C7451/C7452 to same APN 131S0287 as C7237/C7239 for BOM consolidation <rdar://problem/7993241> K99 MLB: Cleanup of CheckPlus warnings/errors 05/26/2010: Release 3.5.0 (Major)- Page 4: Deleted ZS0904 entry from the module parts table as symbol is ready - Page 9: Renamed stiffener Z0920 to MT0900, similar to K16 ***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16 - changes below*** - Page 9: Tagged POGOS and MT0900 as CRITICAL ** Didnt sync page 52 as K16 need to sync it first from K99 to remove accelerometer** - Page 9: Replaced ZS0904 with actual symbol for APN 870-1940 and deleted OMIT_TABLE ** Didnt sync page 40 as K16 needs to sync it first from K99 to remove neck width - Page 9: Cleaned-up TP/NC _P/_N errors from PP3V3_S3_WLAN** - Page 74: Renamed VSNS nets to VSEN to match page 100 constraints and deleted these nets from constraints table on the same page <rdar://problem/8033353> K99 MLB: Change to dual USB port power switch - Page 79: Changed OMIT associated with C7980 to OMIT_TABLE - Page 46: Changed USB port power switch U4690 back to dual port TPS2052B APN 353S2298 - Page 99: Changed OMIT associated with all caps to OMIT_TABLE <rdar://problem/7744955> K99 Proto0 Task: Characterize Voltage/Current/Temperature <rdar://problem/7935301> K99 MLB BOM: Change BOM per CE request Sensors - Page 75: Added Critical attribute to R7560 _ Page 53: For IZDM, change U5360 to INA210 (APN : 353S2073) - Page 97: Added Critical attribute to R9700 - Page 54: For IN1C, change R5412 to 118 Ohms, APN : 114S0127 ***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16*** <rdar://problem/8033256> K99 MLB: Implement 3V3 S5 bleed resistor to satisfy IPD Cumulus ** Didnt sync pages 79 & 99 as K16 need to sync it first from K99 to fix OMIT_TABLE power sequencing on shutdown attribute as mentioned above** - Page 78: Added R7899 0ohm 0603 (will change later) pull-up to =PP3V3_S5_REG and connected R7899 to pin 3 of Q7890; Q7890.5 gate tied to P3V3S5_EN_L; Q7890.4 <rdar://problem/7749046> K99 MLB: Connect SMBUS to internal display connector to GND and, U7840.4 output to P3V3S5_EN_L - Page 52: Added notes about I2C addresses on panel, may not be 100% accurate yet <rdar://problem/8007560> K99 MLB: Change min neck width to meet layout requirements <rdar://problem/7993210> K99 MLB: Cosmetic updates - Page 108: Changed Therm, Sense, Audio line-to-line spacing to 1:1 instead of 2:1 - Page 13: Changed XDP SMBus nets to =I2C_XDP_* for new aliases on page52 - Page 52: Added XDP to MCP_0 SMBus diagram - Page 76: Cleaned-up page, including correcting application of two PLACE_NEAR 05/28/2010: Release 3.6.0 (Major)properties and changing an OMIT to OMIT_TABLE <rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V (not POR) <rdar://problem/7779132> K99 MLB: Implement deeper sleep S4 state -Page 4: Removed MIC5366 from alternate BOM table as it is primary now and replaced - Page 50: Added PLACE_NEAR property on R5022 to ensure no stub in fallback case. 353S2986 with 353S2988, making TI its alternate - Page 4: Deleted 138S0635 from alternate table as its been replaced per GSM(see below) <rdar://problem/7794868> K99 MLB: Change to single USB port power switch <rdar://problem/8036605> K99 MLB BOM: Implement MCP VCORE characterization changes - Page 46: Corrected Refdes from Q4690 to U4690 - Page 75: Changed C7580 to 560pF APN 132S4001 per Intersil FAE <rdar://problem/7993278> K99 MLB: Schematic sync with K16 MLB ***Synced ALL but pages 1-9,12,28,47,69,70,74,75 and 97 from K16 - changes below*** - Page 26: Synced with K16, OMIT changed to OMIT_TABLE - Page 73: Synced with K16, OMITs changed to OMIT_TABLE and cosmetic clean-up <rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V (not POR) - Page 25: Changed BOM table from ISL 353S2986 to MIC5366 353S2988, as Intersil is NOT <rdar://problem/7994057> K99 MLB: Need to add Need_TP=True property to CPU POR - Page 10: Added Need_TP=True attribute to pin E37 & D40 <rdar://problem/8027047> K99 MLB BOM: Swap 132s0247 w/132s0257, 138s0621 w/138s0653, 138s0635 w/138s0654 <rdar://problem/7871167> K99 MLB: Change RC on CPUVCORE PMON output - Page 25,26: Swapped 138s0621 w/138s0653 as per GSM - Page 54: Changed R5471 from 4.53K to 15k for higher PMON pin sink capability - Page 31-34,37,49: Swapped 132s0247 w/132s0257 as per GSM - Page 54: Changed C5470 from 0.22UF to 68nF 10%. Only one in the library - Page 49,73: Swapped 138s0635 w/138s0654 as per GSM <rdar://problem/7934374> K99 MLB BOM: Replace 376S0868 with 376S0912 <rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD - Page 23: Changed Q2300 from 376S0868 to 376S0912 - Page 77: Fixed BOM table attribute to attach BOM option value to TBL_BOMOPTION <rdar://problem/7838450> K99 MLB: WoW / WoL power control architecture change - Page 78: Swapped unused gate to Q7890 and SMC_Adapter_En fet to Q7891. 6/4/2010: EVT Agile Release 4.0.0 (FAB)- Page 78: Added BOM Options WLAN_PCTL:HW to Q7891 both halves - Page 78: Added R7891 0 ohm 5% *** EVT OK2FAB Agile Release *** - Page 78: Added Bom option WLAN_PCTL:SW to R7891 - No changes since last release 3.6.0 - This release matches Quantas official BOM for EVT build <rdar://problem/7871918> K99 MLB: Investigate larger replacement for LCD backlight fuse - Page 98: Changed F9800 to 0603 package APN 740S0115 - Upcoming changes (Acoustic, Alternates) will be reflected in 4.1 major release, which will match Quantas deviations for EVT <rdar://problem/7968723> K99 MLB: Implement 5V LDO for IPD <rdar://problem/7953783> K99 IPD power regulator new design 06/06/2010: Release 4.1.0 (MAJOR)- Page 57: L5720.2 now connects to PP5V_S5_LDO - Page 77: Added U7760 and surrounding circuits. BOM table need to replace later <rdar://problem/8065425> K99 MLB: Add new CPU APN for U1000 - SU9400 - Page 77: Added R7760 for switching capability - Page 4: Added 18 new 639-XXXX BOMS corresponding to 1.4GHz SU9400 CPU - Page 77: Added min line and neck width properties to PP5V_S5_LDO - Page 4: Added 18 new EEEs corresponding to new BOMs - Page 78: Aliased =P5V_S5_EN to =P5V3V3_REG_EN - Page 5: Added SU9400 1.4GHz APN 337S33954 to the BOM module parts table - Page 78: Added R7846 and C7846 0ohm 0.47F (NO STUFF) stuffing options <rdar://problem/8065431> K99 MLB: Add new Elpida 1Gb memory APN - 333S0565 <rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep - Page 4: Added DDR3:ELPIDA_2GB BOM group and set appropriate CFG bits - Page 57: Added R5730 & R5731 for power switch on PP3V3_TPAD - Page 4: Added Elpida DRAM to the CFG table - Page 57: Added U5750 USB Mux - Page 5: Added Elpida 1Gb APN 333S0565 to the BOM module parts table with DRAM_TYPE: - Page 57: Added R5751 (NO STUFF) to bypass U5750 MUX ELPIDA_2GB BOM option - Page 78: Added =USB_TPAD_MUX_EN to DDRREG_EN <rdar://problem/8066033> K99 MLB BOM: Change CPU VCORE 0603 bypass caps for acoustics <rdar://problem/7935301> K99 MLB BOM: Change BOM per CE request - Page 4: Added SS_CAP_22uF, MU_CAP_22uF and TY_CAP_22uF BOM options for corresponding - Page 39: Added Critical attribute to U3920, U3940 vendor BOM group SYNC_MASTER=K24_MLB SYNC_DATE=01/19/2009 - Page 54: Added Critical attribute to Q5401,U5413 - Page 49: Added OMIT_TABLE BOM option to C4902 PAGE TITLE - Page 77: Removed Critical from C7710, C7715 - Page 73: Added OMIT_TABLE BOM option to C7360 & C7361 - Page 98: Added Critical attribute toF9800 - Page 94: Added OMIT_TABLE BOM option to C9480 - page 110: Added BOM config table for 22uF caps for three vendors - Samsung (138S0635), 5/19/2010: Release 3.2.0 (Major)Murata (138S0676) and Taiyo (138S0688). Also assigned C1200-C1231, C4902, C7360, C7361 and C9480 to these groups DRAWING NUMBER SIZE <rdar://problem/8006037> K99 MLB: Change RC Filter Values on AMON, and BMON - Page 110: Removed C1200-C1231 from 10uF caps BOM config table - Page 54: Changed R5481 to 150K APN 118S0106 and C5487 to 0.0068uF APN 132S0009 - Page 54: Changed R5401 to 300K APN 118S0276 and C5490 to 0.0033uF APN 132S0049 <rdar://problem/7993210> K99 MLB: Cosmetic updates - Page 5: Deleted revision history and replaced it with BOM module parts, Programmable REVISION <rdar://problem/7986457> K99 MLB: Change LIO Flex connector J4700 to accommodate new LIO parts and Alternate parts tables as space was limited R Flex - Page 47: Replaced J4700 with new POR connector APN 516S0862 <rdar://problem/8065428> K99 MLB: Add alternates per GSM - Page 5: Added APN 104S0023 as an alternate for APN 104S0018 per GSM/CE NOTICE OF PROPRIETARY PROPERTY: BRANCH - Page 5: Added APN 107S0139 as an alternate for APN 104S0075 per GSM/CE <rdar://problem/7992365> K99 MLB: Change MCP HVDD_PLL rail to 2.85V - Page 4: Deleted APN 353S2988 entry from the alternate table THE INFORMATION CONTAINED HEREIN IS THE - Page 5: Added APN 138S0671 as an alternate for APN 138S0673 per GSM/CE - Page 4: Replaced APN 353S2987 entry with APN 353S3047 (TI) as an alternate PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. - Page 5: Added APN 155S0556 as an alternate for APN 155S0367 per GSM/CE - Page 25: Replaced U2590 with 2.85V LDO APN 353S3048 (MICREL) THE POSESSOR AGREES TO THE FOLLOWING: PAGE - Page 5: Added APN 376S0926 as an alternate for APN 376S0610 per GSM/CE - Page 25: Replaced APN 353S2986 with 353S3048 in the BOM table too for HVDDLDO:FIXED - Page 5: Added APN 155S0457 as an alternate for APN 155S0329 per GSM/CE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE - Page 5: Added APN 377S0107 as an alternate for APN 377S0066 per GSM/CE <rdar://problem/7978044> K99 MLB: Modify IPD interface for deeper sleep II NOT TO REPRODUCE OR COPY IT - Page 57: Connected a new PME signal SMC_PME_S4_L to pin 2 <rdar://problem/8064296> K99 MLB: Change pull-up values for SMC 0 SMBus for TCON I2C III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET - Page 52: Changed R5250 & R5251 with 2K APN 117S0052 to reduce rise time <rdar://problem/8004981> K99 MLB: Connect eDP SMBUS interface to SMC SMBUS 0 IV ALL RIGHTS RESERVED - Page 4: Added BOM option DPI2C:SMC to stuff R5242 & R5243
Revision History
Apple Inc.
051-8379 4.4.0
6 OF 110 6 OF 73
Functional Test Points
Fan Connectors
I12
LIO CONNECTOR
7 8 57 45 45
LCP + SPI CONN

37 8
DEBUG VOLTAGE
8 40
TRUE TRUE TRUE
I15 I16
PP5V_S0 FAN_RT_PWM FAN_RT_TACH

(NEED TO ADD 1 GND TP)
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
SPEAKER FUNC_TEST
I228
TRUE
48 49 48 49
TRUE TRUE
SPKRAMP_R_N_OUT SPKRAMP_R_P_OUT
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
I230
INT DP FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
TRUE
(NEED 2 TP)
7 59
PP3V3_SW_LCD PPVOUT_SW_LCDBKLT DP_INT_ML_F_N<0> DP_INT_ML_F_P<0> DP_INT_ML_F_N<1> DP_INT_ML_F_P<1> DP_INT_AUX_CH_C_N DP_INT_AUX_CH_C_P DP_INT_HPD_CONN LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 =I2C_TCON_SCL =I2C_TCON_SDA
TRUE
=PP3V3_S0_AUDIO =PP3V42_G3H_ONEWIRE SMC_BC_ACOK SYS_ONEWIRE =USB_PWR_EN USB_EXTD_OC_L USB_CAMERA_P USB_CAMERA_N USB_EXTD_P USB_EXTD_N =PP1V8R1V5_S0_AUDIO =I2C_LIO_SDA =I2C_LIO_SCL AUD_GPIO_3 AUD_I2C_INT_L =I2C_MIKEY_SDA =I2C_MIKEY_SCL AUD_IP_PERIPHERAL_DET SPKRAMP_INR_P SPKRAMP_INR_N HDA_SDIN0 HDA_SDOUT HDA_BIT_CLK HDA_SYNC HDA_RST_L AUD_IPHS_SWITCH_EN
(NEED 2 TP)
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
8 37 9 37 38 39 37 38 36 37 57 18 37 18 37 68 18 37 68 18 37 68 18 37 68 8 37 37 41 37 41 37 48 19 37 37 41 37 41 17 37 37 48 71 37 48 71 19 37 68 19 37 68 19 37 68 19 37 68 19 37 68 19 37
=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS LPC_AD<3..0> SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS LPCPLUS_RESET_L SMC_TDO SMC_TRST_L SMC_MD1 SMC_TX_L LPC_CLK33M_LPCPLUS SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO
TRUE
8 40
TRUE
19 38 40 68
TRUE
40 68
TRUE
40 68
TRUE
19 38 40 68
TRUE
19 38 40
TRUE
38 39 40
TRUE
25 40
TRUE
38 39 40
TRUE
38 40
TRUE
38 40
TRUE
36 38 39 40
TRUE
25 40 68
TRUE
19 40 47
TRUE
40 68
TRUE
40 68
TRUE
19 38 40
TRUE
19 38 40
TRUE
38 39 40
TRUE
38 39 40
TRUE
38 39 40 50 38 40 36 38 39 40 19 40
PPVCORE_S0_CPU PPVCORE_S0_MCP PP1V05_S0 PP1V5_S0 PP3V3_S0 PP5V_S0 PP3V3_S3 PP5V_S3 PP0V9_S5 PP3V3_S5 PP3V42_G3H PPBUS_G3H PP3V3_WLAN_F PP3V3_S0_HDD_R PPDCIN_S5_S5 PPVOUT_SW_LCDBKLT PP3V3_SW_LCD PP1V5R1V35_S3 SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L PP0V9_ENET PP1V05_S0_MCP_PLL_UF PP3V3_ENET PP3V3_SW_DPPWR PP5V_S3_RTUSB_A_F PPBUS_G3H_ISNS
8 42 8 42 8 57 8 57 71 8 57 71 7 8 57 8 8 8 8 57 71 8 8 42 49 7 34 39 7 35 8 7 42 59 62 7 59 8 71 38 57 19 38 57 19 38 39 57
TRUE TRUE TRUE TRUE TRUE TRUE
8 8 8 61 36 8
I259
I260
7 42 59 (NEED 2 TP) 62 59 71 59 71 59 71 59 71 59 71
I261
I256
I257
I255
I252
DC POWER CONN
59 71 59 59 62 59 62 59 62 59 62 59 62 59 62 41 59 41 59
I253
I254
TRUE AIRPORT / BT TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
34 67 34 67 16 34 67 16 34 67 16 34 67 16 34 67 18 34 68 18 34 68 34 38 39 8 34
I251
=PP18V5_DCIN_CONN =PP5V_S3_LIO_CONN
(NEED 6 TP)
8 49 8 49
I313
I246
I247
I248
I249
I488 I489
HALL EFFECT CONN (PLACEHOLDER)
TRUE TRUE TRUE TRUE

8 49
I479 I480
TRUE TRUE
SMC_LID_R =PP3V42_G3H_HALL
49
TRUE
PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N USB_BT_P USB_BT_N WIFI_EVENT_L =PP3V3_S3_BT PP3V3_WLAN_F PCIE_WAKE_L AP_RESET_CONN_L AP_CLKREQ_Q_L
(NEED 6 TP) 7 34 39
16 34 34 34
FSB SIGNALS WITH NOTEST
B
10 14 65 10 14 65 10 14 65 10 14 65 10 14 65 10 14 65 10 14 65 10 14 65 10 14 65 10 14 65 10 14 65
SATA HDD TRUE TRUE TRUE TRUE TRUE TRUE TRUE
I319
I314
I315
I318
I317
I455
I456
PP3V3_S0_HDD_R SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SMC_HDD_OOB_TEMP SMC_HDD_TEMP_CTL

(NEED 5 TP)
7 35 35 67 35 67
IPD_FLEX_CONN
35 67 35 67 35 38 35 38
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
SMC_TPAD_RST_L SMC_LID SMC_ONOFF_L =I2C_TPAD_SCL =I2C_TPAD_SDA =PP3V42_G3H_TPAD PP3V3_TPAD_CONN PP5V_TPAD_FILT USB_TPAD_CONN_N USB_TPAD_CONN_P
39 46 38 39 46 49
NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE
FSB_A_L<35..3> FSB_ADS_L FSB_ADSTB_L<1..0> FSB_D_L<63..0> FSB_DINV_L<3..0> FSB_DSTB_L_N<3..0> FSB_DSTB_L_P<3..0> FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L<4..0>
38 39 46 41 46 41 46 8 46 46 46 46 71 46 71
BATT POWER CONN

I322
TRUE TRUE
41 70 41 70 49 49 50
TRUE TRUE TRUE TRUE
I321
I320
I305
SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SYS_DETECT_L PPVBAT_G3H_CONN
(NEED 4 TP)
SYNC_MASTER=K6_MLB
PAGE TITLE
(NEED TO ADD 4 GND TP NEAR J6950 AND 1 FOR SHIELD)
FUNCTIONAL TEST
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

7 OF 110
SHEET
7 OF 73
6
"S0,S0M" RAILS
4
"S3" RAILS
LVDDR (1.5V/1.35V) Rails
2
"G3H" RAILS
49 7 71
53
=PPVCORE_S0_CPU_REG
18 A
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE
7 42
58
=PP5V_S0_FET
0.100 A
PP5V_S0
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE
7 57
52
=PPDDR_S3_REG
11.30 A
PP1V5R1V35_S3
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE (OR 1.35V)
=PP3V42_G3H_REG
0.064
PP3V42_G3H
=PPVCORE_S0_CPU
11 12 64
D
55
=PPCPUVTT_S0_REG
9.40 A
PP1V05_S0
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
7 57
=PP1V05_S0_CPU =PP1V05_S0_MCP_FSB =PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_PLL_UF_R =PP1V05_SW_MCP_FSB =PP1V05_S0_MCP_PE_DVDD =PP1V05_S0_MCP_M2CLK_DLL =PP1V05_S0_MCP_DP0_VDD =PP1V05_S0_XDP
=PP5V_S0_LPCPLUS =PP5V_S0_FAN =PP5V_S0_CPU_IMVP =PP5VR3V3_S0_DPCADET =PP5V_S0_CPUVTTS0 =PP5V_S0_BKL =PP5V_S0_MCPREG =PP5V_S0_MCPFSBFET

10 11 12 14 20 23 23 20 23 56 20 23 58 20 23 15 23
7 40 45 53 61 55 62 54 22
0 mA 4250 mA
=PPLVDDR_S3_MEM_A =PPLVDDR_S3_MEM_B =PP1V5R1V35_S3_MCP_MEM =PP1V5R1V35_S0_MCPDDRFET =PPVIN_S0_DDRREG_LDO
26 27 30 28 29 31 15 21 52
58
=PP3V3_S3_FET
1.274 A
PP3V3_S3
=PPVIN_S5_SMCVREF =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD =PP3V42_G3H_HALL =PP3V3_S5_SMC =PP3V3_S5_LPCPLUS =PP3V42_G3H_BMON_ISNS =PP3V42_G3H_ONEWIRE PP3V3_G3_RTC
39 41 57 50 57 36 7 46 7 49 38 39 7 40 43 7 37 19 20 23
=PP3V3_S0_FET
3.30 A
PP3V3_S0
7 57 71
17 24 13
54
=PPMCPCORE_S0_REG
(MCP VCORE AFTER SENSE RES)
PPVCORE_S0_MCP
7 42
23.8 A
=PPVCORE_S0_MCP =PPVCORE_S0_MCPGFXFET
LVDDR VRef/VTT (0.75V/0.675V) Rails
20 23 22
52
=PPVTT_S0_DDR_LDO
1.20 A
PPDDRVTT_S0
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE
=PPDDRVTT_S0_MEM_A =PPDDRVTT_S0_MEM_B
32 32
52 33
=PPVTT_S3_DDR_BUF
PPDDRVREF_S3
=PP3V3_S0_XDP =PP3V3_S0_MCP =PP3V3_S0_P1V5S0 =PP3V3_S0_DEBUGROM =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMBUS_MCP_0 =PP3V3_S0_FAN =PP3V3_S0_AUDIO =PP3V3_S0_IMVP =PP3V3_S0_MCP_GPIO =PP3V3_S0_MCP_PLL_UF =PP3V3_S0_MCP_HVDD =PP3V3_S0_SMC =PP3V3_S0_MCPTHMSNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_PWRCTL =PP3V3_S0_SMBUS_MCP_1 =PP3V3_S0_HDD =PP3V3_S0_MCP_PLL_VLDO =PP3V3_S0_MCPCOREISNS =PP3V3_S0_MCPDDRISNS =PP3V3_S0_BKLTISNS =PP3V3_S0_CSREGISNS =PP3V3_S0_BKL_VDDIO =PP3V3_S0_DPCONN =PP3V3_S0_HDDISNS
13 20 23 56 40 41 41 41 45 7 37 53 17 18 19 23 20 23 39 44 44 57 41 35 56 43 43 42 43 62 61 42 51
=PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_PDCISENS =PP3V3_S3_VREFMRGN =PP3V3_S3_MCP_GPIO =PP3V3_S3_SMS =PP3V3_S3_1V5S3ISNS =PP3V3_S3_WLANISNS =PP3V3_S3_DBGLEDS =PP3V3_S3_BT =PP3V3_S3_WLAN =PP3V3_S3_TPAD
41 52 33 49 7 19
=PP18V5_DCIN_CONN
PPDCIN_S5_S5
MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V MAKE_BASE=TRUE
42 42 49
=PPDCIN_S5_CHGR
50
50 7 34 34 46
=PPBUS_G3H
PPBUS_G3H
7 42 49
=PPBUS_S0_LCDBKLT =PPVIN_S5_P5VP3V3 =PPBUS_G3H_R_IN =PPBUS_5V_S5
63
51 43 56
=PP5V_S3_REG
5.40 A
PP5V_S3
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE
C
43
=PP5V_S3_MCPDDRFET =PP5V_S3_SYSLED =PP5V_S3_TPAD =PP5V_S3_DDRREG =PP5V_S3_AUDIO_AMP =PP5V_S3_P5VS0FET =PP5V_S3_RTUSB =PP5V_S3_LIO_CONN
=PPBUS_G3H_R_OUT
PPBUS_G3H_ISNS
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 MM VOLTAGE=8.4V MAKE_BASE=TRUE
21 39 56 52 48 58 36 7 49
=PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP =PPVIN_S0_MCPCORE =PPVIN_S3_DDRREG
55 53 54 52
56
=PP1V5_S0_REG
.210 A
PP1V5_S0
7 57 71
=PP1V5_S0_CPU =PP1V5_S0_MCP_PLL_VLDO =PP1V8R1V5_S0_AUDIO =PP3V3R1V5_S0_MCP_HDA
11 12
56 7 37 19 23
B
9
"ENET" RAILS
"S5" RAILS
=PP3V3_ENET_FET_R
400mA
B
7 57 71
PP3V3_ENET
57 51
=PP3V3_S5_REG
1.07 A + S3 + S0
PP3V3_S5
56
=PP1V05_S0_MCP_PLL_OR
PP1V05_S0_MCP_PLL_UF
300mA ~100mA
=PP3V3_ENET_MCP_RMGT 18 20 =PP3V3_ENET_MCP_PLL_MAC
23 23
=PP1V05_S0_MCP_PLL_UF
23
58
=PP0V9_ENET_FET
PP0V9_ENET
=PP0V9_ENET_MCP_RMGT
20 23
=PP3V3_S5_MCP_GPIO =PP3V3_S5_ROM =PP3V3_S5_MCP =PP3V3_S5_MCPPWRGD =PP3V3_S5_P3V3S3FET =PP3V3_S5_P3V3S0FET =PP3V3_S5_P3V3ENETFET =PP3V3_S5_P0V9S5 =PP3V3_S5_VMON =PP3V3_S5_SMBUS_SMC_MGMT =PP3V3_S5_P0V9ENETFET =PP3V3_S5_TPAD =PP3V3_S5_DP_PORT_PWR =PP3V3_S0_LCD =PP3V3_SMC_PME
18 19 47 20 23 25 58 58 58 56 57 57 41 58 46 61 59 39
56
=PP0V9_S5_REG
0.290 A
105 mA/241 mA
PP0V9_S5
SYNC_MASTER=K6_MLB
PAGE TITLE
=PP0V9_S5_MCP_VDD_AUXC =PP0V9_ENET_P0V9ENETFET
20 23 58
Power Aliases
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

8 OF 110
SHEET
8 OF 73
8
Z0906
STDOFF-4.5OD1.8H-SM
1
7
HEAT SINK MOUNTING BOSSES
6
PCI-E ALIASES
5
UNUSED GPU LANES
4
LVDS ALIASES
3
65 10
2
CPU ALIASES
1
=MCP_BSEL<0:2> TP_CPU_PECI_MCP
MAKE_BASE=TRUE
BSEL<2..0> 14 FSB MHZ
Z0907
STDOFF-4.5OD1.8H-SM
1
Z0908
STDOFF-4.5OD1.8H-SM
1
16 16
CPU_BSEL<0:2>
MAKE_BASE=TRUE
=PEG_D2R_N<5:4> =PEG_D2R_P<5:4> =PEG_R2D_C_N<5:4> =PEG_R2D_C_P<5:4> PEG_CLK100M_P PEG_CLK100M_N PEG_CLKREQ_L ENET_CLKREQ_L

USB ALIASES
NC_PEG_D2RN<5:4>
NO_TEST=TRUE NO_TEST=TRUE
17 17 17 17
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

17 17 17 17
NC_PEG_D2RP<5:4> NC_PEG_R2DCN<5:4>
NO_TEST=TRUE
16
=MCP_IFPA_TXC_P =MCP_IFPA_TXC_N =MCP_IFPA_TXD_P<0..3> =MCP_IFPA_TXD_N<0..3>
NC_LVDS_IG_A_CLKP NO_TEST=TRUE MAKE_BASE=TRUE NC_LVDS_IG_A_CLKN NO_TEST=TRUE MAKE_BASE=TRUE NC_LVDS_IG_A_DATAP<0..3> NO_TEST=TRUE MAKE_BASE=TRUE NC_LVDS_IG_A_DATAN<0..3> NO_TEST=TRUE
MAKE_BASE=TRUE
14
CPU_PECI_MCP
Z0909
STDOFF-4.5OD1.8H-SM
1
Z0910
STDOFF-4.5OD1.8H-SM
1
Z0911
STDOFF-4.5OD1.8H-SM
1
16
NC_PEG_R2DCP<5:4>
NO_TEST=TRUE
MCP89 ALIASES
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
266 133 200 (166) 333 100 (400) (RSVD)
67 16
NC_PEG_CLK100MP
NO_TEST=TRUE
67 16
NC_PEG_CLK100MN
NO_TEST=TRUE
D
Z0912
STDOFF-4.5OD1.8H-SM
1
16
NC_PEG_CLKREQ_L
NO_TEST=TRUE
Z0913
STDOFF-4.5OD1.8H-SM
1
16
=MCP_IFPB_TXC_P =MCP_IFPB_TXC_N =MCP_IFPB_TXD_P<0..3> =MCP_IFPB_TXD_N<0..3>
NC_LVDS_IG_B_CLKP NO_TEST=TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKN NO_TEST=TRUE NC_LVDS_IG_B_DATAP<0..3> MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_DATAN<0..3> NO_TEST=TRUE
MAKE_BASE=TRUE
17
TP_MCP_RGB_DAC_VREF MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_B_CLK_P<1> MEM_B_CLK_N<1> MEM_A_A<15> MEM_B_A<15>
NC_MCP_RGB_DAC_VREF TP_MEM_A_CLKP<1> TP_MEM_A_CLKN<1> TP_MEM_B_CLKP<1> TP_MEM_B_CLKN<1> TP_MEM_A_A<15> TP_MEM_B_A<15>
66 15
NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
66 15 66 15
NC_ENET_CLKREQ_L
NO_TEST=TRUE
66 15
17 UNUSED USB PORTS 68 18 68 18 68 18 68 18 68 18 68 18
USB_SDCARD_P USB_SDCARD_N USB_MINI_P USB_MINI_N USB_EXTC_P USB_EXTC_N
NC_USB_SDCARDP NC_USB_SDCARDN NC_USB_MINIP NC_USB_MININ NC_USB_EXTCP NC_USB_EXTCN
59 17 9
NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE
17
LCD_IG_BKLT_PWM LCD_IG_PWR_EN LCD_IG_BKLT_EN =MCP_IFPAB_DDC_CLK =MCP_IFPAB_DDC_DATA
LCD_BKLT_PWM LCD_IG_PWR_EN LCD_BKLT_EN
62
MAKE_BASE=TRUE
9 17 59
66 15 66 15 63
MAKE_BASE=TRUE MAKE_BASE=TRUE
17 17
TP_LVDS_DDC_CLK MAKE_BASE=TRUE TP_LVDS_DDC_DATA

MAKE_BASE=TRUE
19
MCP_MEM_VDD_SEL_1V5
TP_MEM_VDD_SEL_1V5
MAKE_BASE=TRUE
FAN BOSS
SSD BOSS STDOFF-4.5OD1.9H-SM

1
X16 BOSS STDOFF-4.5OD1.9H-SM

1
Z0905
STDOFF-4.5OD1.8H-SM
1
Z0915
Z0914
ETHERNET ALIASES
PLACE_NEAR=U7980.A1:5MM
R0911
PP3V3_ENET_FET
58
=PP3V3_ENET_FET_ROUT
DISPLAY PORT ALIASES

8 67 17 67 17 17 67 17 67 17
=PP3V3_ENET_FET
5% 1/16W MF-LF 402
ENET_RXD_PD
MDP CONN METAL TAB

NOSTUFF STIFFENER-K16-K99
SM-SP
1
MAKE_BASE=TRUE
MT0900
ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3> ENET_CLK125M_RXCLK ENET_RX_CTRL ENET_MDIO MCP_RGMII_VREF
OUT OUT OUT OUT OUT OUT BI OUT OUT
18 69 18 69 18 69 18 69
60 60 60
DP_IG_ML0_P<0..3> DP_IG_ML0_N<0..3> DP_IG_HPD0 DP_IG_AUX_CH0_P DP_IG_AUX_CH0_N DP_AUX_CH_C_N DP_AUX_CH_C_P DP_CA_DET DP_IG_ML1_P<1:0> DP_IG_ML1_N<1:0> DP_IG_AUX_CH1_P DP_IG_AUX_CH1_N DP_IG_HPD1 DP_IG_ML1_P<3:2> DP_IG_ML1_N<3:2>
DP_EXT_ML_P<0..3> 61 71 MAKE_BASE=TRUE DP_EXT_ML_N<0..3> 61 71 MAKE_BASE=TRUE DP_EXT_HPD 61 DP_EXT_AUX_CH_P MAKE_BASE=TRUE 60 DP_EXT_AUX_CH_N MAKE_BASE=TRUE 60 MAKE_BASE=TRUE DP_EXT_AUX_CH_C_N 61 71 MAKE_BASE=TRUE DP_EXT_AUX_CH_C_P 61 71 MAKE_BASE=TRUE DP_EXT_CA_DET 61
MAKE_BASE=TRUE
ENET_RXCLK_PD
MAKE_BASE=TRUE
18 69
67 17 67 17
18 69
67 17 67 17
18 69
DP_INT_ML_P<1:0> 59 71 DP_INT_ML_N<1:0> MAKE_BASE=TRUE 59 71 MAKE_BASE=TRUE DP_INT_AUX_CH_P 59 71 DP_INT_AUX_CH_N MAKE_BASE=TRUE 59 71

MAKE_BASE=TRUE
18
17 17
R09801
5% 1/20W MF 201 2
R0981
10K
R09841
5% 1/20W MF 201 2
ENET_ENERGY_DET
18 17
DP_INT_HPD 59 MAKE_BASE=TRUE TP_DP_INT_MLP<3:2> MAKE_BASE=TRUE TP_DP_INT_MLN<3:2>

MAKE_BASE=TRUE
10K
5% 1/20W MF 2 201
10K
CHARGER SIGNAL
50
SATA ALIASES
1
IN
=CHGR_ACOK
SMC_BC_ACOK
MAKE_BASE=TRUE
OUT
7 37 38 39
R09821
5% 1/20W MF 201 2
R0985
10K
5% 1/20W MF
67 18 67 18 67 67 67 18 67 18
UNUSED SATA ODD SIGNALS
10K
R0983
10K
5% 1/20W MF 2 201
2 201
SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N
NC_SATA_ODD_R2DCP NC_SATA_ODD_R2DCN NC_SATA_ODD_R2DP NC_SATA_ODD_R2DN NC_SATA_ODD_D2RP NC_SATA_ODD_D2RN
NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE
MCPCOREISNS SIGNAL
54
MCPCORES0_VO
MAKE_BASE=TRUE
=MCPCOREISNS_N =MCPCOREISNS_P
43
54
MCPCORES0_ISP_R
MAKE_BASE=TRUE
43
EMI IO POGO PINS

CRITICAL CRITICAL
ZS0904
POGO-2.0OD-2.95H-K86-K87
SM
1
ZS0905
1.4DIA-SHORT-SILVER-K99
SM
1
CRITICAL
SM
1
ZS0906
POGO-2.0OD-3.6H-K86-K87
CRITICAL
ZS0907
POGO-2.0OD-3.6H-K86-K87
SM
1
A
GND
VOLTAGE=0V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
SYNC_MASTER=K6_MLB
PAGE TITLE
SIGNAL ALIAS
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

9 OF 110
SHEET
9 OF 73
8
65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7
7
OMIT_TABLE
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
6
ADS* BNR* BPRI* DEFER* DRDY* DBSY* BR0* IERR* INIT* LOCK* M4 J5 L5 N5 F38 J1 M2 B40 D8 N1
65
5
7 14 65 14 65 14 65
CDC-QKWH-QS-1.2-10W-800-R0-1M
65 14 7 65 14 7 65 14 7 65 14 7 65 14 7
FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_ADSTB_L<0> FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1> CPU_A20M_L CPU_FERR_L CPU_IGNNE_L CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L
P2 V4 W1 T4 AA1 AB4 T2 AC5 AD2 AD4 AA5 AE5 AB2 AC1 Y4
A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0*
U1000
BGA (1 OF 8) PENRYN-SFF
FSB_ADS_L FSB_BNR_L FSB_BPRI_L FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L FSB_BREQ0_L CPU_IERR_L CPU_INIT_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_TRDY_L FSB_HIT_L FSB_HITM_L XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L
BI BI BI
=PP1V05_S0_CPU
8 11 12
BI BI BI
14 65 14 65 14 65
R10001
54.9
1% 1/20W MF 201 2
BI
14 65
D
IN
14 65
BI
7 14 65
ADDR GROUP0
BI BI BI BI BI
CONTROL
65 14 7 65 14 7 65 14 7 65 14 7 65 14 7
R1 R5 U1 P4 W5
REQ0* REQ1* REQ2* REQ3* REQ4*
RESET* RS0* RS1* RS2* TRDY*
G5 K2 H4 K4 L1
IN IN IN IN IN
13 14 65 14 65 14 65 14 65 14 65
65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7
DATA GRP 0
65 14 7 65 14 7
DATA GRP 2
AN1 AK4 AG1 AT4 AK2 AT2 AH2 AF4 AJ5 AH4 AM4 AP4 AR5 AJ1 AL1 AM2 AU5 AP2 AR1 AN5 C7 D4 F10 F8 C9 C5 E5
A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* A20M* FERR* IGNNE*
HIT* HITM* BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* XDP/ITP SIGNALS
H2 F2 AY8 BA7 BA5 AY2 AV10 AV2 AV4 AW7 AU1 AW5 AV8
BI BI
7 14 65 7 14 65 65 14 7
OMIT_TABLE
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI BI BI
13 65 13 65 13 65 13 65 13 65
R10011
54.9
1% 1/20W MF 201 2
BI
13 65
65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7 65 14 7
IN IN OUT IN IN
10 13 65 10 13 65 10 13 65 10 13 65 10 13 65
R10021
68
THERMAL
5% 1/20W MF 201 2
65 14 7 65 14 7 65 14 7
PROCHOT* THRMDA THRMDC THERMTRIP* ICH
D38 BB34 BD34 B10
CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N PM_THRMTRIP_L
OUT OUT OUT

44 71 44 71
14 39 65
65 14 7 65 14 7
FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_DSTB_L_N<0> FSB_DSTB_L_P<0> FSB_DINV_L<0>
F40 G43 E43 J43 H40 H44 G39 E41 L41 K44 N41 T40 M40 G41 M44 L43 K40 J41 P40
D0* D1* BGA D2* (2 OF 8) D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0* CDC-QKWH-QS-1.2-10W-800-R0-1M PENRYN-SFF
U1000
D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2*
AP44 AR43 AH40 AF40 AJ43 AG41 AF44 AH44 AM44 AN43 AM40 AK40 AG43 AP40 AN41 AL41 AK44 AL43 AJ41
FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_DSTB_L_N<2> FSB_DSTB_L_P<2> FSB_DINV_L<2>
7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65
ADDR GROUP1
65 14 65 14 65 14
OUT IN
OUT
14 39 65
65 14 7 65 14 7 65 14 7
65 33
65 14 65 14 65 14 65 14
IN IN IN IN
STPCLK* LINT0 LINT1 SMI*
H CLK BCLK0 BCLK1 A35 C35
65 14 7 65 14 7
FSB_CLK_CPU_P FSB_CLK_CPU_N
IN IN
14 65 14 65
65 14 7 65 14 7 65 14 7 65 14 7
25 13
OUT
XDP_DBRESET_L
J7
65 14 7
DBR* RSVD7 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 J9 F4 H8 V2 Y2 AG5 AL5
10 10
10
CPU_TEST1 CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5 TP_CPU_TEST6
E37 TEST1 NEED_TP=TRUE D40 TEST2 NEED_TP=TRUE C43 TEST3 AE41 TEST4 AY10 TEST5 AC43 TEST6
TP_CPU_RSVD_J9 TP_CPU_RSVD_F4 TP_CPU_RSVD_H8 TP_CPU_RSVD_V2 TP_CPU_RSVD_Y2 TP_CPU_RSVD_AG5 TP_CPU_RSVD_AL5
65 14 7 65 14 7 65 14 7 65 14 7 65 14 7
R1005
1K PLACE_NEARs:
R1005.2: U1000.AW43:12.7 mm R1006.1: U1000.AW43:12.7 mm C1014.1: U1000.AE41:12.7 mm
65 14 7 65 14 7 65 14 7 65 14 7
CPU JTAG Support

65 13 10
R1090
1
1% 1/20W MF 2 201
FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_DSTB_L_N<1> FSB_DSTB_L_P<1> FSB_DINV_L<1> CPU_GTLREF
DATA GRP 3
IN
P44 V40 V44 AB44 R41 W41 N43 U41 AA41 AB40 AD40 AC41 AA43 Y40 Y44 T44 U43 W43 R43 AW43
D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* GTLREF
D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* COMP0 COMP1 COMP2 COMP3 DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI*
AV38 AT44 AV40 AU41 AW41 AR41 BA37 BB38 AY36 AT40 BC35 BC39 BA41 BB40 BA35 AU43 AY40 AY38 BC37 AE43 AD44 AE1 AF2 G7 B8 C41 E7 D10 BD10
65 65 65 65
FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63> FSB_DSTB_L_N<3> FSB_DSTB_L_P<3> FSB_DINV_L<3> CPU_COMP<0> CPU_COMP<1> CPU_COMP<2> CPU_COMP<3> CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L TP_CPU_PSI_L
DATA GRP1
7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65 7 14 65
XDP_TMS
54.9 2
1% 1/20W MF 201
R1091
65 13 10
XDP_TDI
54.9 2 1
1% 1/20W MF 201
R1006
2K NO STUFF
CPU_TEST1 CPU_TEST2 CPU_TEST4
10 10
MISC
R1092
1
65 13 10
XDP_TDO
54.9 2
1% 1/20W MF 201
1% 1/20W MF 2 201
10
C1014 1
NO STUFF 0.1UF
IN IN IN IN IN
14 53 65 14 65 14 65 13 14 65 14 65
R10231
54.9
1% 1/20W MF 201 2 1
R10211
54.9
1% 1/20W MF 201 2 1
PLACE_NEAR=J1300.52:12.7 mm
R1010
1
10% 6.3V 2 X5R 201
65 9 65 9 65 9
OUT OUT OUT
NO STUFF
R1093
65 13 10
R10111
1K
5% 1/20W MF 201 2
XDP_TCK
54.9 2 1
1% 1/20W MF 201
5% 1/20W MF 201
NO STUFF
1
CPU_BSEL<0> CPU_BSEL<1> CPU_BSEL<2>
A37 C37 B38
BSEL0 BSEL1 BSEL2
R1022
27.4
R1020
27.4
R1012
1K
R1094
65 13 10
5% 1/20W MF 2 201
1% 1/20W MF 2 201
1% 1/20W MF 2 201
XDP_TRST_L
54.9 2
1% 1/20W MF 201
PLACE_NEARs:
R1020.1: U1000.AE43:12.7 mm R1021.1: U1000.AD44:12.7 mm R1022.1: U1000.AE1:12.7 mm R1023.1: U1000.AF2:12.7 mm
SYNC_MASTER=K16_MLB
PAGE TITLE
CPU FSB
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

10 OF 110
SHEET
10 OF 73
7
(CPU CORE POWER)
=PPVCORE_S0_CPU
6
8 11 12 64
4
=PP1V05_S0_CPU OMIT_TABLE
AE37 AP38 AN37 AL37 C33 B32 H36 F36 G35 F34 E33 E35 D32 K36 N35 L35 J35 W35 V36 P36 U35 R35 AB36 AC35 AA35 AK36 AF36 AJ35 AG35 AE35 AP36 AN35 AL35 C13 B14 B12 H12 H14 G11 G13 F12 F14 E11 E13 D14 D12 K10 N11 N13 M14 L11 L13 K12 K14 J11 J13 V10 P10 W11 W13 V12 V14 U11 U13 T14 R11
8 10 11 12
OMIT_TABLE
BD30 BB28 BB30 B24 B22 H22 H24 F22 F24 D24 D22 M22 M24 K22 K24 V22 V24 T22 T24 P22 P24 AD22 AD24 AB22 AB24 Y22 Y24 AK22 AK24 AH22 AH24 AF22 AF24 AP22 AP24 AM22 AM24 AY22 AY24 AV22 AV24 AT22 AT24 BD22 BD24 BB22 BB24 B20 B18 B16 H20 F20 D20 H16 H18 F16 F18 D18 D16 M20
OMIT_TABLE
K20 M16 M18 K16 K18 V20 T20 P20 V16 V18 T16 T18 P16 P18 AD20 AB20 Y20 AD16 AD18 AB16 AB18 Y16 Y18 AK20 AK16 AK18 AH20 AF20 AH16 AH18 AF16 AF18 AP20 AM20 AP16 AP18 AM16 AM18 AY20 AV20 AT20 AY16 AY18 AV16 AV18 AT16 AT18 BD20 BB20 BD16 BD18 BB16 BB18 AP14 AM14 AY14 AV14 AT14 BD14 BB14 H32 G33 F32 N33 M32 L33 K32 J33 W33 V32 U33 T32 R33 P32 AD32 AC33 AB32 AA33 Y32 AK32 AJ33 AH32 AG33 AF32 AE33 AR33 AP32 AN33 AM32 AL33 AY32 AV32 AU33 AT32 AT34 BD32 BB32 B26 B30 B28 H26 F26 D26 H28 H30 F28 F30 D30 D28 M26 K26 M28 M30 K28 K30 V26 T26 P26 V28 V30 T28 T30 P28 P30 AD26 AB26 Y26
18 A (CULV Design Target) 17.6 A (CULV ICC_Max)

AD28 AD30 AB28 AB30 Y28 Y30 AK26 AH26 AF26 AK28 AK30 AH28 AH30 AF28 AF30 AP26 AM26 AP28 AP30 AM28 AM30 AY26 AV26 AT26 AY28 AY30 AV28 AV30 AT28 AT30 BD26 BB26 BD28 N37 L37 K38 J37 W37 V38 U37 R37 P38 AC37 AB38 AA37 AK38 AJ37 AG37 AF38 B34 D34 BD8 BC7 BB10 BB8 BC5 BB4 AY4 BD12 BC13
OMIT_TABLE
R13 P12 P14 AB10 AD14 AC11 AC13 AB12 AB14 AA11 AA13 Y14 AK10 AF10 AK12 AK14 AJ11 AJ13 AH14 AG11 AG13 AF12 AF14 AE11 AE13 AP10 AR11 AR13 AP12 AN11 AN13 AL11 AL13 AU11 AU13 N7 N9 L7 L9 W7 W9 U7 U9 R7 R9 AC7 AC9 AA7 AA9 AJ7 AJ9 AG7 AG9 AE7 AE9 AR7 AR9 AN7 AN9 AL7 AL9 A33 A13 B42 H42 F42 D42 D44 F44 M42 K42 V42 T42 P42 AD42 AB42 Y42 AK42 AH42 AF42 AP42 AM42 AY42 AV42 AT42 AV44 AY44 BB42 BA43 C39 H38 G37 E39 N39 M38 L39 J39 W39 U39 T38 R39 AD38 AC39 AA39 Y38 AJ39 AH38 AG39 AE39 AR37 AR39 AN39 AM38 AL39 AW37 AW39 AU37 AU39 AT38 BD38 BD40 BC41 BA39 B36 D36 H34 M36 M34 K34 T36 V34 T34 P34 AD36 Y36 AD34 AB34 Y34 AK34 AH36 AH34 AF34 AR35 AM36
OMIT_TABLE
AP34 AM34 AV36 AT36 AY34 AW33 AW35 AV34 AU35 BD36 BB36 BC33 BA33 C31 C29 C27 G31 E31 G27 G29 E27 E29 N31 L31 J31 N27 N29 L27 L29 J27 J29 W31 W27 W29 U31 R31 U27 U29 R27 R29 AC31 AA31 AC27 AC29 AA27 AA29 AJ31 AG31 AE31 AJ27 AJ29 AG27 AG29 AE27 AE29 AR31 AR27 AR29 AN31 AL31 AN27 AN29 AL27 AL29 AW31 AU31 AW27 AW29 AU27 AU29 BC31 BA31 BC27 BC29 BA27 BA29 C25 C23 C21 G21 G23 G25 E21 E23 E25 N21 N23 N25 L21 L23 L25 J21 J23 J25 W21 W23 W25 U21 U23 U25 R21 R23 R25 AC21 AC23 AC25 AA21 AA23 AA25 AJ21 AJ23 AJ25 AG21 AG23 AG25 AE21 AE23 AE25 AR21 AR23 AR25 AN21 AN23 AN25 AL21 AL23 AL25 AW21 AW23 AW25 AU21 AU23 AU25 BC21 BC23 BC25 BA21 BA23 BA25 C19 C17 G17 G19 E17 E19 N17 N19 L17 L19 J17 J19 W17 W19 U17 U19 R17 R19 AC17 AC19 AA17 AA19 AJ17 AJ19 AG17 AG19
OMIT_TABLE
AE17 AE19 AR17 AR19 AN17 AN19 AL17 AL19 AW17 AW19 AU17 AU19 BC17 BC19 BA17 BA19 C15 C11 H10 G15 E15 M10 N15 L15 J15 M12 T10 W15 U15 R15 T12 AD10 Y10 AC15 AA15 AD12 Y12 AH10 AJ15 AG15 AE15 AH12 AM10 AR15 AN15 AL15 AM12 AT10 AW15 AU15 AY12 AW11 AW13 AV12 AT12 BC15 BA15 BC11 BB12 BA11 BA13 B6 H6 G9 F6 E9 D6 M6 M8 K6 K8 U5 V6 V8 T6 T8 P6 P8 AD6 AD8 AB6 AB8 Y6 Y8 AK6 AK8 AH6 AH8 AF6 AF8 AP6 AP8 AM6 AM8 AY6 AW9 AU7 AV6 AU9 AT6 AT8 BD6 BC9 BB6 BA9 C3 B4 G3 E3 D2 N3 L3 J3 W3 U3 R3 AC3 AA3
U1000
BGA (7 OF 8)
U1000
BGA (3 OF 8)
U1000
BGA (8 OF 8)
U1000
PENRYN-SFF CDC-QKWH-QS-1.2-10W-800-R0-1M
BGA (4 OF 8)
U1000
BGA (5 OF 8)
U1000
BGA (6 OF 8)
VCC
VSS
VSS
VCC
VCC
VCCP
VCCP
AJ3 AG3 AE3 AR3 AN3 AL3 AW3 AU3 BD4 BC3 BB2 BA3 G1 E1 AW1 BA1 A39 A41 A31 A27 A29 A21 A23 A25 A17 A19 A15 A11 A9 A5 A7
VCC
(CPU IO POWER 1.05V)

=PP1V05_S0_CPU
8 10 11 12
4500 mA (before VCC stable) 2500 mA (after VCC stable)
VSS
VSS
VSS
VSS
VCCP
(CPU INTERNAL PLL POWER 1.5V)

=PP1V5_S0_CPU
8 12
VCCA
130 mA
CPU_VID<0> CPU_VID<1> CPU_VID<2> CPU_VID<3> CPU_VID<4> CPU_VID<5> CPU_VID<6>
OUT OUT OUT OUT OUT OUT OUT
12 53 65 12 53 65 12 53 65 12 53 65 12 53 65 12 53 65 12 53 65
=PPVCORE_S0_CPU
1
8 11 12 64
VID
R1100
100
VCCSENSE VSSSENSE
CPU_VCCSENSE_P CPU_VCCSENSE_N
1% 1/20W MF 2 201 PLACE_NEAR=U1000.BD12:25.4 mm

OUT
53 65
OUT
53 65
PLACE_NEAR=U1000.BC13:25.4 mm 1
R1101
100
1% 1/20W MF 2 201
SYNC_MASTER=K16_MLB
PAGE TITLE
CPU Power & Ground

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

11 OF 110
SHEET
11 OF 73
64 11 8
=PPVCORE_S0_CPU
CPU VCORE HF AND BULK DECOUPLING

4x 270uF. 32x 10uF 0603, 28x 2.2uF 0402 + 40x 2.2uF 0402
CRITICAL NOSTUFF
1
LAYOUT NOTE: PLACE ON OPPOSITE SIDE OF CPU
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
C1200
10UF
C1201
10UF
C1202
10UF
C1203
10UF
C1204
10UF
C1205
10UF
C1206
10UF
C1207
10UF
C1208
10UF
C1209
10UF
CPU VCORE VID CONNECTIONS

65 53 11
20% 2 6.3V X5R 603
20% 2 6.3V X5R 603
20% 2 6.3V X5R 603
20% 2 6.3V X5R 603
20% 2 6.3V X5R 603
20% 2 6.3V X5R 603
20% 2 6.3V X5R 603
20% 2 6.3V X5R 603
20% 2 6.3V X5R 603
20% 2 6.3V X5R 603
IN
CPU_VID<0..6>
MAKE_BASE=TRUE
IMVP6_VID<0..6>
OUT
65

1
CRITICAL OMIT_TABLE
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
CRITICAL OMIT_TABLE
1
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL NOSTUFF
1
C1210
10UF
C1211
10UF
C1212
10UF
C1213
10UF
C1214
10UF
C1215
10UF
C1216
10UF
C1217
10UF
C1218
10UF
C1219
10UF
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603

1
CRITICAL NOSTUFF
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
CRITICAL OMIT_TABLE
1
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL NOSTUFF
1
CRITICAL NOSTUFF
1
C1220
10UF
C1221
10UF
C1222
10UF
C1223
10UF
C1224
10UF
C1225
10UF
C1226
10UF
C1227
10UF
C1228
10UF
C1229
10UF
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
VCCA (CPU AVdd) DECOUPLING

C
11 8
=PP1V5_S0_CPU OMIT_TABLE
1x 10uF, 1x 0.01uF
1 1

1
CRITICAL OMIT_TABLE
CRITICAL NOSTUFF
1
C1230
10UF
C1231
10UF
C1280
10uF
C1281
0.01UF
LAYOUT NOTE: PLACE C1281 NEAR PIN B34 OF U1000
20% 2 6.3V X5R 603
20% 2 6.3V X5R 603
20% 6.3V 2 X5R 603
10% 2 10V X5R 201

1
CRITICAL OMIT_TABLE
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
C1240
2.2UF
C1241
2.2UF
C1242
2.2UF
C1243
2.2UF
C1244
2.2UF
C1245
2.2UF
C1246
2.2UF
C1247
2.2UF
C1248
2.2UF
C1249
2.2UF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
VCCP (CPU I/O) DECOUPLING

11 10 8
=PP1V05_S0_CPU
1x 270uF, 12x 2.2uF

OMIT_TABLE
1

1
CRITICAL OMIT_TABLE
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
OMIT_TABLE
1
OMIT_TABLE
1
OMIT_TABLE
1
OMIT_TABLE
1
OMIT_TABLE
1
C1283
2.2UF
C1284
2.2UF
C1285
2.2UF
C1286
2.2UF
C1287
2.2UF
C1288
2.2UF
C1250
2.2UF
C1251
2.2UF
C1252
2.2UF
C1253
2.2UF
C1254
2.2UF
C1255
2.2UF
C1256
2.2UF
C1257
2.2UF
C1258
2.2UF
C1259
2.2UF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF

1
CRITICAL OMIT_TABLE
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL OMIT_TABLE
1
CRITICAL
OMIT_TABLE
1
OMIT_TABLE
1
OMIT_TABLE
1
OMIT_TABLE
1
OMIT_TABLE
1
OMIT_TABLE
1
C1260
2.2UF
C1261
2.2UF
C1262
2.2UF
C1263
2.2UF
C1264
2.2UF
C1265
2.2UF
C1266
2.2UF
C1267
2.2UF
C1290 1
20% 2V TANT 2 CASE-B4-SM
C1291
2.2UF
C1292
2.2UF
C1293
2.2UF
C1294
2.2UF
C1295
2.2UF
C1296
2.2UF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
270UF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
LAYOUT NOTE: PLACE C1290 CLOSE TO CPU PLACE C1283-C1288 CLOSE TO FSB ADDRESS PINS PLACE C1291-C1296 CLOSE TO FSB DATA PINS LAYOUT NOTE: PLACE ON SAME SIDE AS CPU
1
CRITICAL
CRITICAL
1
CRITICAL
1
C1270
270UF
C1271
270UF
C1272
270UF
20% 2V 2 TANT CASE-B4-SM
20% 2 2V TANT CASE-B4-SM
20% 2V 2 TANT CASE-B4-SM
SYNC_MASTER=K16_MLB
PAGE TITLE
CPU Decoupling & VID

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

12 OF 110
SHEET
12 OF 73
Micro2-XDP Connector
NOTE: This is not the standard XDP pinout.
Use with 920-0782 Adapter Flex to support chipset debug.
8 8
=PP3V3_S0_XDP =PP1V05_S0_XDP XDP XDP_CONN CRITICAL
R13151
54.9
1% 1/20W MF 201 2
J1300
DF40C-60DS-0.4V
F-ST-SM-HF 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1
65 10 65 10
BI BI
XDP_BPM_L<5> XDP_BPM_L<4> XDP_BPM_L<3> XDP_BPM_L<2> XDP_BPM_L<1> XDP_BPM_L<0> TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1 TP_XDP_OBSDATA_B0 TP_XDP_OBSDATA_B1
OBSFN_A0 OBSFN_A1 OBSDATA_A0 OBSDATA_A1 OBSDATA_A2 OBSDATA_A3 OBSFN_B0 OBSFN_B1 OBSDATA_B0 OBSDATA_B1 OBSDATA_B2 OBSDATA_B3 XDP_OBS20 PWRGD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 SDA SCL TCK1 TCK0 XDP
OBSFN_C0 OBSFN_C1 OBSDATA_C0 OBSDATA_C1 OBSDATA_C2 OBSDATA_C3 OBSFN_D0 OBSFN_D1 OBSDATA_D0 OBSDATA_D1 OBSDATA_D2 OBSDATA_D3
JTAG_MCP_TDO JTAG_MCP_TRST_L TP_XDP_OBSDATA_C0 TP_XDP_OBSDATA_C1 TP_XDP_OBSDATA_C2 TP_XDP_OBSDATA_C3 JTAG_MCP_TDI JTAG_MCP_TMS TP_XDP_OBSDATA_D0 TP_XDP_OBSDATA_D1 TP_XDP_OBSDATA_D2 TP_XDP_OBSDATA_D3
IN
19
19
65 10 65 10
BI IN
65 10 65 10
IN IN
19 19
XDP
R1399
65 14 10
TP_XDP_OBSDATA_B2 TP_XDP_OBSDATA_B3 XDP_PWRGD
IN
CPU_PWRGD
1K
5% 1/20W MF 201
19
IN
19
PM_LATRIGGER_L JTAG_MCP_TCK =I2C_XDP_SDA =I2C_XDP_SCL XDP_TCK
41 41
BI BI
NC
65 10
OUT
FSB_CLK_ITP_P ITPCLK/HOOK4 IN 14 65 FSB_CLK_ITP_N ITPCLK#/HOOK5 IN 14 65 VCC_OBS_CD 65 XDP_CPURST_L RESET#/HOOK6 XDP_DBRESET_L DBR#/HOOK7 OUT 10 25 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. XDP_TDO TDO IN 10 65 XDP_TRST_L TRSTn OUT 10 65 XDP_TDI TDI OUT 10 65 XDP_TMS TMS OUT 10 65 XDP_PRESENT# XDP
XDP
R1303
1 2 FSB_CPURST_L IN 10 14 65 5% PLACEMENT_NOTE=Place close to CPU to minimize stub. 1/20W MF 201
1K
C1300 1
0.1UF
10% 6.3V 2 X5R 201
518S0774
C1301
0.1UF
10% 2 6.3V X5R 201
Direction of XDP adapter flex

Please place J1300 within 1" of board edge with odd-numbered pins facing edge. Avoid any tall components between J1300 and edge.
SYNC_MASTER=K16_MLB
PAGE TITLE
eXtended Debug Port (Micro-XDP)

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

13 OF 110
SHEET
13 OF 73
5
OMIT_TABLE
4
MCP89U-A01
BGA
U1400
65 10 7 65 10 7 65 10 7
BI BI BI BI BI BI BI BI BI BI BI BI
FSB_DSTB_L_P<0> FSB_DSTB_L_N<0> FSB_DINV_L<0> FSB_DSTB_L_P<1> FSB_DSTB_L_N<1> FSB_DINV_L<1> FSB_DSTB_L_P<2> FSB_DSTB_L_N<2> FSB_DINV_L<2> FSB_DSTB_L_P<3> FSB_DSTB_L_N<3> FSB_DINV_L<3> FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<0> FSB_ADSTB_L<1> FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4> FSB_ADS_L FSB_BNR_L FSB_BREQ0_L FSB_DBSY_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_TRDY_L CPU_PECI_MCP CPU_PROCHOT_L
J38 J39 F39 R34 R35 U36 J37 J36 L35 C37 C38 B35 U38 V37 Y36 V40 Y39 Y40 V39 AA39 AA36 AA37 Y38 AC36 AA40 AA38 AF39 AD38 AC38 AJ38 AD37 AJ39 AC40 AC37 AD40 AC39 AF36 AF40 AG39 AD39 AD36 AF37 AJ40 AG40 AG38 Y37 AF38 U40 U39 V38 U37 V36 AG33 AD35 AG34 AF35 U32 AD34 AD32 AG37 AG32 AG36 V32 V35 AC33 D35 E35 F35
65 10 7 65 10 7 65 10 7
65 10 7 65 10 7 65 10 7
65 10 7 65 10 7 65 10 7
65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7 65 10 7
65 10 7 65 10 7
65 10 7 65 10 7 65 10 7 65 10 7 65 10 7
BI BI BI BI BI
65 10 7 65 10
IN IN IN IN IN IN IN IN BI
B
23 20 14 8
65 10 65 10
=PP1V05_S0_MCP_FSB
65 10 65 10 7 65 10 7
R1410
54.9
R1415
62
65 10 7 65 10
1% 1/20W MF 201 2
65 39 10 65 10
5% 1/20W MF 2 201
9 65 39 10
OUT OUT
IN IN
PM_THRMTRIP_L CPU_FERR_L =MCP_BSEL<2> =MCP_BSEL<1> =MCP_BSEL<0>

65 10
9 9 9
IN IN IN
SYMBOL 1 OF 11 CPU_DSTBP0* CPU_D0* CPU_DSTBN0* CPU_D1* CPU_DBI0* CPU_D2* CPU_D3* CPU_DSTBP1* CPU_D4* CPU_DSTBN1* CPU_D5* CPU_DBI1* CPU_D6* CPU_DSTBP2* CPU_D7* CPU_DSTBN2* CPU_D8* CPU_D9* CPU_DBI2* CPU_D10* CPU_DSTBP3* CPU_D11* CPU_DSTBN3* CPU_D12* CPU_DBI3* CPU_D13* CPU_D14* CPU_A3* CPU_D15* CPU_A4* CPU_D16* CPU_A5* CPU_D17* CPU_A6* CPU_D18* CPU_A7* CPU_D19* CPU_A8* CPU_D20* CPU_A9* CPU_D21* CPU_A10* CPU_D22* CPU_A11* CPU_D23* CPU_A12* CPU_D24* CPU_A13* CPU_D25* CPU_A14* CPU_D26* CPU_A15* CPU_D27* CPU_A16* CPU_D28* CPU_A17* CPU_D29* CPU_A18* CPU_D30* CPU_A19* CPU_D31* CPU_A20* CPU_D32* CPU_A21* CPU_D33* CPU_A22* CPU_D34* CPU_A23* CPU_D35* CPU_A24* CPU_D36* CPU_A25* CPU_D37* CPU_A26* CPU_D38* CPU_A27* CPU_D39* CPU_A28* CPU_D40* CPU_A29* CPU_D41* CPU_A30* CPU_D42* CPU_A31* CPU_D43* CPU_A32* CPU_D44* CPU_A33* CPU_D45* CPU_A34* CPU_D46* CPU_A35* CPU_D47* CPU_ADSTB0* CPU_D48* CPU_ADSTB1* CPU_D49* CPU_D50* CPU_REQ0* CPU_D51* CPU_REQ1* CPU_D52* CPU_REQ2* CPU_D53* CPU_REQ3* CPU_D54* CPU_REQ4* CPU_D55* CPU_D56* CPU_ADS* CPU_D57* CPU_BNR* CPU_D58* CPU_BR0* CPU_D59* CPU_DBSY* CPU_D60* CPU_D61* CPU_DRDY* CPU_HIT* CPU_D62* CPU_HITM* CPU_D63* CPU_LOCK* CPU_TRDY* CPU_BPRI* CPU_DEFER* CPU_PECI CPU_PROCHOT* BCLK_OUT_CPU_P CPU_THERMTRIP* BCLK_OUT_CPU_N CPU_FERR* BCLK_OUT_ITP_P BCLK_OUT_ITP_N CPU_BSEL2 CPU_BSEL1 BCLK_OUT_NB_P CPU_BSEL0 BCLK_OUT_NB_N
M37 M39 P39 L38 L39 L40 M40 P40 H40 L37 F38 F40 H38 M38 H39 J40 U35 R36 R37 P35 R38 R33 U34 R40 P34 P37 P38 P36 P33 P32 R32 R39 H36 F36 L33 M35 L34 M33 M36 M32 J34 H35 H34 L36 M34 F37 H37 J35 D39 E36 D40 E40 C39 E38 A37 C36 B38 E37 C35 A35 B37 D36 A36 D38 AF32 AG35 AJ37 AJ36 AK32 AK33 AJ35 AJ34 AJ32 AJ33 AA33 V33 Y33 Y35 AA35 AC35 AA32 AC34 D2 V34 Y32 U33 Y34 AA34
65 65
FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63> FSB_BPRI_L FSB_DEFER_L FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65 7 10 65
FSB
OUT OUT
10 65 10 65
OUT OUT OUT OUT
10 65 10 65
13 65 13 65
OUT OUT OUT
R14301
49.9
1% 1/20W MF 201 2
R1435
49.9
65 10 65 10
FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2>
AF33 AD33 AF34
CPU_RS0* CPU_RS1* CPU_RS2*
Loop-back clock for delay matching.
BCLK_IN_N BCLK_IN_P
1% 1/20W MF 2 201
65 65
MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND
AK39 AK40 AK38 AK37
BCLK_VML_COMP_VDD BCLK_VML_COMP_GND CPU_COMP_VCC CPU_COMP_GND
A
R1431
49.9
1 1
65 65
R1436
49.9
1% 1/20W MF 201 2
1% 1/20W MF 2 201
CPU_A20M* CPU_IGNNE* CPU_INIT* CPU_INTR CPU_NMI CPU_SMI* CPU_PWRGD CPU_RESET* CPU_DPRSLPVR CPU_SLP* CPU_DPSLP* CPU_DPWR* CPU_STPCLK* CPU_DPRSTP*
CPU_A20M_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_SMI_L CPU_PWRGD FSB_CPURST_L PM_DPRSLPVR FSB_CPUSLP_L CPU_DPSLP_L FSB_DPWR_L CPU_STPCLK_L CPU_DPRSTP_L
OUT OUT OUT OUT OUT OUT
10 65 10 65 10 65 10 65 10 65 10 65
=PP1V05_S0_MCP_FSB NO STUFF
1
8 14 20 23
R1440
150
5% 1/20W MF 2 201
SYNC_MASTER=K16_MLB
OUT
10 13 65
PAGE TITLE
OUT OUT OUT OUT OUT OUT OUT
10 13 65 53 65 10 65 10 65 10 65 10 65 10 53 65
MCP CPU Interface

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

14 OF 110
SHEET
14 OF 73
7
OMIT_TABLE
3
OMIT_TABLE
U1400 MCP89U-A01 BGA

SYMBOL 2 OF 11
66 27 66 27 66 27 66 27
MCP89U-A01
BGA
SYMBOL 3 OF 11
U1400
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT
66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 27
66 27 66 27 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26
66 26 66 26 66 26 66 26 66 26 66 26 66 26
MEM_A_DQ<63> MEM_A_DQ<62> MEM_A_DQ<61> MEM_A_DQ<60> MEM_A_DQ<59> MEM_A_DQ<58> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<55> MEM_A_DQ<54> MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49> MEM_A_DQ<48> MEM_A_DQ<47> MEM_A_DQ<46> MEM_A_DQ<45> MEM_A_DQ<44> MEM_A_DQ<43> MEM_A_DQ<42> MEM_A_DQ<41> MEM_A_DQ<40> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<37> MEM_A_DQ<36> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<31> MEM_A_DQ<30> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<26> MEM_A_DQ<25> MEM_A_DQ<24> MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<21> MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<18> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<15> MEM_A_DQ<14> MEM_A_DQ<13> MEM_A_DQ<12> MEM_A_DQ<11> MEM_A_DQ<10> MEM_A_DQ<9> MEM_A_DQ<8> MEM_A_DQ<7> MEM_A_DQ<6> MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2> MEM_A_DQ<1> MEM_A_DQ<0> MEM_A_DM<7> MEM_A_DM<6> MEM_A_DM<5> MEM_A_DM<4> MEM_A_DM<3> MEM_A_DM<2> MEM_A_DM<1> MEM_A_DM<0>
AN6 AN4 AT4 AU3 AM7 AN7 AT5 AT3 AU5 AV5 AR6 AN9 AV3 AV4 AM8 AN8 AP8 AP9 AN12 AT11 AT8 AR8 AT9 AM12 AP12 AN14 AT14 AR14 AR11 AP11 AM15 AN15 AR27 AT27 AM30 AN30 AN27 AP27 AN29 AM29 AT30 AT32 AP33 AR33 AP30 AR30 AM33 AN33 AU35 AV35 AT37 AT38 AT33 AT35 AV37 AU38 AR35 AN36 AM35 AM34 AR36 AR37 AM36 AM37 AN5 AM9 AR9 AM14 AT29 AN32 AT36 AN37
MDQ0_63 MDQ0_62 MDQ0_61 MDQ0_60 MDQ0_59 MDQ0_58 MDQ0_57 MDQ0_56 MDQ0_55 MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50 MDQ0_49 MDQ0_48 MDQ0_47 MDQ0_46 MDQ0_45 MDQ0_44 MDQ0_43 MDQ0_42 MDQ0_41 MDQ0_40 MDQ0_39 MDQ0_38 MDQ0_37 MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29 MDQ0_28 MDQ0_27 MDQ0_26 MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22 MDQ0_21 MDQ0_20 MDQ0_19 MDQ0_18 MDQ0_17 MDQ0_16 MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12 MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7 MDQ0_6 MDQ0_5 MDQ0_4 MDQ0_3 MDQ0_2 MDQ0_1 MDQ0_0 MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4 MDQM0_3 MDQM0_2 MDQM0_1 MDQM0_0
MEMORY PARTITION 0
MDQS0_7_P MDQS0_7_N MDQS0_6_P MDQS0_6_N MDQS0_5_P MDQS0_5_N MDQS0_4_P MDQS0_4_N MDQS0_3_P MDQS0_3_N MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N
AR4 AR5 AT6 AU6 AN11 AM11 AT12 AR12 AR29 AP29 AR32 AP32 AV36 AU36 AN35 AN34 AR17 AM17 AM18 AR26 AR18 AP17 AN26 AP26 AR15 AR24 AP23 AP18 AP24 AN24 AR23 AM23 AM24 AN23 AR21 AP20 AP21 AR20 AJ30 AK30 AK31
MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_BA<2> MEM_A_BA<1> MEM_A_BA<0> MEM_A_A<15> MEM_A_A<14> MEM_A_A<13> MEM_A_A<12> MEM_A_A<11> MEM_A_A<10> MEM_A_A<9> MEM_A_A<8> MEM_A_A<7> MEM_A_A<6> MEM_A_A<5> MEM_A_A<4> MEM_A_A<3> MEM_A_A<2> MEM_A_A<1> MEM_A_A<0>
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
27 66 27 66 27 66 27 66 27 66 27 66 27 66 27 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66 26 66
66 29 66 29 66 29 66 29 66 29 66 29 66 29 66 29 66 29 66 29 66 29 66 29 66 29 66 29 66 29 66 29 66 29
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT
MRAS0* MCAS0* MWE0*
66 29
OUT OUT OUT
26 27 32 66 66 29 26 27 32 66 66 29 26 27 32 66 66 29 66 29
MBA0_2 MBA0_1 MBA0_0
OUT OUT OUT
26 27 32 66 26 27 32 66 26 27 32 66
66 29 66 29 66 29 66 29 66 29
MA0_15 MA0_14 MA0_13 MA0_12 MA0_11 MA0_10 MA0_9 MA0_8 MA0_7 MA0_6 MA0_5 MA0_4 MA0_3 MA0_2 MA0_1 MA0_0
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
9 66 66 29 26 27 32 66 66 29 26 27 32 66 66 29 26 27 32 66 66 29 26 27 32 66 66 29 26 27 32 66 66 28 26 27 32 66 66 28 26 27 32 66 66 28 26 27 32 66 66 28 26 27 32 66 66 28 26 27 32 66 66 28 26 27 32 66 66 28 26 27 32 66 66 28 26 27 32 66 66 28 26 27 32 66 66 28 26 27 32 66 66 28 8 23 66 28 66 28 66 28 66 28 23 66 28 66 28 66 28 66 28 66 28 66 28 66 28 66 28 66 28
+VIO_M2CLK_DLL +VIO_M2CLK_DLL +VIO_M2CLK_DLL +VIO_PLL_MEM +VIO_PLL_MEM +VIO_PLL_MEM +VIO_PLL_FSB +VIO_PLL_FSB +VIO_PLL_FSB +VIO_PLL_CPU +VIO_PLL_CPU +VIO_PLL_CPU
=PP1V05_S0_MCP_M2CLK_DLL 550 mA
PP1V05_S0_MCP_PLL_FSBMEM AH29 20 mA 70 mA AH30 AJ31 25 mA AF29 AF30 AF31 25 mA AG29 AG30 AG31 AM21 AN21 AM20 AN20 AP15 AN18 AP14 AN17 AM27 AM26 MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_CS_L<1> MEM_A_CS_L<0> MEM_A_ODT<1> MEM_A_ODT<0> MEM_A_CKE<1> MEM_A_CKE<0>
66 28 66 28 66 28 66 28
MCLK0A_1_P MCLK0A_1_N MCLK0A_0_P MCLK0A_0_N MCS0A_1* MCS0A_0* MODT0A_1 MODT0A_0 MCKE0A_1 MCKE0A_0
66 28
OUT OUT
9 66 66 28 9 66 66 28 66 28
MEM_B_DQ<63> MEM_B_DQ<62> MEM_B_DQ<61> MEM_B_DQ<60> MEM_B_DQ<59> MEM_B_DQ<58> MEM_B_DQ<57> MEM_B_DQ<56> MEM_B_DQ<55> MEM_B_DQ<54> MEM_B_DQ<53> MEM_B_DQ<52> MEM_B_DQ<51> MEM_B_DQ<50> MEM_B_DQ<49> MEM_B_DQ<48> MEM_B_DQ<47> MEM_B_DQ<46> MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<41> MEM_B_DQ<40> MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<33> MEM_B_DQ<32> MEM_B_DQ<31> MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<28> MEM_B_DQ<27> MEM_B_DQ<26> MEM_B_DQ<25> MEM_B_DQ<24> MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<20> MEM_B_DQ<19> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<16> MEM_B_DQ<15> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<12> MEM_B_DQ<11> MEM_B_DQ<10> MEM_B_DQ<9> MEM_B_DQ<8> MEM_B_DQ<7> MEM_B_DQ<6> MEM_B_DQ<5> MEM_B_DQ<4> MEM_B_DQ<3> MEM_B_DQ<2> MEM_B_DQ<1> MEM_B_DQ<0> MEM_B_DM<7> MEM_B_DM<6> MEM_B_DM<5> MEM_B_DM<4> MEM_B_DM<3> MEM_B_DM<2> MEM_B_DM<1> MEM_B_DM<0>
66 66
AM1 AN1 AT1 AU1 AM3 AM2 AR2 AR1 AW3 AW4 AU8 AV8 AU2 AV2 AW6 AV6 AY9 AW9 AY11 AY12 AW8 AY8 AU9 AU11 AU12 AU14 AV15 AU15 AW12 AV12 AY15 AW15 AW26 AY26 AV29 AW29 AU26 AV26 AU27 AU29 AW30 AV30 AY33 AW33 AY29 AY30 AU32 AY32 AW35 AY35 AV39 AU39 AV33 AU33 AW38 AV38 AR40 AR39 AM39 AM38 AT40 AU40 AN40 AM40 AR3 AY6 AV9 AY14 AV27 AU30 AW37 AR38
MDQ1_63 MDQ1_62 MDQ1_61 MDQ1_60 MDQ1_59 MDQ1_58 MDQ1_57 MDQ1_56 MDQ1_55 MDQ1_54 MDQ1_53 MDQ1_52 MDQ1_51 MDQ1_50 MDQ1_49 MDQ1_48 MDQ1_47 MDQ1_46 MDQ1_45 MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40 MDQ1_39 MDQ1_38 MDQ1_37 MDQ1_36 MDQ1_35 MDQ1_34 MDQ1_33 MDQ1_32 MDQ1_31 MDQ1_30 MDQ1_29 MDQ1_28 MDQ1_27 MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23 MDQ1_22 MDQ1_21 MDQ1_20 MDQ1_19 MDQ1_18 MDQ1_17 MDQ1_16 MDQ1_15 MDQ1_14 MDQ1_13 MDQ1_12 MDQ1_11 MDQ1_10 MDQ1_9 MDQ1_8 MDQ1_7 MDQ1_6 MDQ1_5 MDQ1_4 MDQ1_3 MDQ1_2 MDQ1_1 MDQ1_0 MDQM1_7 MDQM1_6 MDQM1_5 MDQM1_4 MDQM1_3 MDQM1_2 MDQM1_1 MDQM1_0
MDQS1_7_P MDQS1_7_N MDQS1_6_P MDQS1_6_N MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N MDQS1_0_P MDQS1_0_N
AN2 AN3 AY5 AY4 AV11 AW11 AV14 AW14 AW27 AY27 AV32 AW32 AY37 AY36 AN38 AN39 AW18 AV17 AY18 AW24 AT18 AV18 AU24 AV24 AU17 AY24 AW23 AU18 AY23 AU23 AV23 AT21 AT23 AU21 AV21 AY21 AW21 AY20
MEM_B_DQS_P<7> MEM_B_DQS_N<7> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_BA<2> MEM_B_BA<1> MEM_B_BA<0> MEM_B_A<15> MEM_B_A<14> MEM_B_A<13> MEM_B_A<12> MEM_B_A<11> MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> MEM_B_A<7> MEM_B_A<6> MEM_B_A<5> MEM_B_A<4> MEM_B_A<3> MEM_B_A<2> MEM_B_A<1> MEM_B_A<0>
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
29 66 29 66 29 66 29 66 29 66 29 66 29 66 29 66 28 66 28 66 28 66 28 66 28 66 28 66 28 66 28 66
MEMORY PARITION 1
MRAS1* MCAS1* MWE1*
OUT OUT OUT
28 29 32 66 28 29 32 66 28 29 32 66
MBA1_2 MBA1_1 MBA1_0
OUT OUT OUT
28 29 32 66 28 29 32 66 28 29 32 66
MA1_15 MA1_14 MA1_13 MA1_12 MA1_11 MA1_10 MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
9 66 28 29 32 66 28 29 32 66 28 29 32 66 28 29 32 66 28 29 32 66 28 29 32 66 28 29 32 66 28 29 32 66 28 29 32 66 28 29 32 66 28 29 32 66 28 29 32 66 28 29 32 66 28 29 32 66 28 29 32 66
=PP1V5R1V35_S3_MCP_MEM
1
R1520
1K
5% 1/20W MF 2 201
MRESET0* MCLK1A_1_P MCLK1A_1_N MCLK1A_0_P MCLK1A_0_N MCS1A_1* MCS1A_0* MODT1A_1 MODT1A_0 MCKE1A_1 MCKE1A_0
AM6 AV20 AW20 AT20 AU20 AT15 AY17 AT17 AW17 AT24 AT26
MEM_RESET_L MEM_B_CLK_P<1> MEM_B_CLK_N<1> MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_CS_L<1> MEM_B_CS_L<0> MEM_B_ODT<1> MEM_B_ODT<0> MEM_B_CKE<1> MEM_B_CKE<0>
OUT
26 27 28 29
OUT OUT
9 66 9 66
OUT OUT
28 29 32 66 28 29 32 66
OUT OUT
26 27 32 66 26 27 32 66 66 29 66 29
66 27 66 27 66 27 66 27 66 26 66 26 66 26 66 26
OUT OUT
28 29 32 66 28 29 32 66
OUT OUT
26 27 32 66 26 27 32 66 23 21 20
66 29
=PP1V5R1V35_SW_MCP_MEM
66 29 66 28
OUT OUT
28 29 32 66 28 29 32 66
OUT OUT
26 27 32 66 26 27 32 66
R15101
40.2
1% 1/20W MF 201 2
66 28 66 28 66 28
OUT OUT
21 28 29 32 66 21 28 29 32 66
OUT OUT
21 26 27 32 66 21 26 27 32 66
AL23 MCP_MEM_COMP_GNDMEM_COMP_GND AL24 MCP_MEM_COMP_VDDMEM_COMP_VDD
R15111
40.2
1% 1/20W MF 201 2
SYNC_MASTER=K16_MLB
PAGE TITLE
MCP Memory Interface

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

15 OF 110
SHEET
Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009).
K6/K69 EDP currents used.
15 OF 73
OMIT_TABLE
MCP89U-A01
9
U1400
BGA
IN
PEG_CLKREQ_L AP_CLKREQ_L ENET_CLKREQ_L PCIE_WAKE_L =PEG_D2R_P<4> =PEG_D2R_N<4> =PEG_D2R_P<5> =PEG_D2R_N<5> PCIE_AP_D2R_P PCIE_AP_D2R_N TP_PCIE_PE1_D2RP TP_PCIE_PE1_D2RN PP3V3_S0_MCP_PLL_HVDD
V1 U1 U4 U7 Y4 Y5 AA9 AA8 AA4 AA5 Y7 Y6 W10
34
IN
IN
34 7
IN
SYMBOL 4 OF 11 PEA_CLKREQ*/GPIO_49 PE0_REFCLK_P PE0_REFCLK_N PEB_CLKREQ*/GPIO_50 PE1_REFCLK_P PE1_REFCLK_N PEC_CLKREQ*/GPIO_51 PE2_REFCLK_P PE_WAKE* PE2_REFCLK_N
V5 V4 V2 V3 U3 U2 Y3 Y2 AA7 AA6 AA2 AA3 Y8 Y9 U6

1
PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N TP_PCIE_CLK100M_PE2P TP_PCIE_CLK100M_PE2N =PEG_R2D_C_P<4> =PEG_R2D_C_N<4> =PEG_R2D_C_P<5> =PEG_R2D_C_N<5> PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN PCIE_RESET_L
OUT OUT OUT OUT
9 67 9 67
7 34 67 7 34 67
D
PE0 ports are Gen2-capable. PE1 ports are Gen1-only. 4 RCs: 4x, x2, x1, x1 2 RCs: x1, x1
9 9
IN IN IN IN
PE0_RX4_P PE0_RX4_N PE0_RX5_P PE0_RX5_N PE1_RX0_P PE1_RX0_N PE1_RX1_P PE1_RX1_N +3.3V_PLL_HVDD +VIO_PLL_PE +VIO_PLL_PE +VIO_PLL_PE +VIO_PLL_XREF_XS +VIO_PLL_XREF_XS +VIO_PLL_XREF_XS +VIO_PLL_SATA +VIO_PLL_SATA +VIO_PLL_SATA +VIO_PLL_H +VIO_PLL_H
PCI EXPRESS
PE0_TX4_P PE0_TX4_N PE0_TX5_P PE0_TX5_N PE1_TX0_P PE1_TX0_N PE1_TX1_P PE1_TX1_N PEX_RST*
OUT OUT OUT OUT
9 9
9 9
9 9
If PE0[3:0] are not used, +VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND
67 34 7 67 34 7
IN IN
OUT OUT
34 67 34 67
If PE0[4:5] and PE1[0:1] are not used, +VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND
23
OUT
25
23
PP1V05_S0_MCP_PLL_PEXSATA
AG10 AG11 AG12 AH10 AH11 AH12
R1600
22K
5% 1/20W MF 2 201
AE10 AE11 AF12 AF10 AF11
C
PEX0_TERM_P
U5
67
MCP_PEX0_TERMP
R16101
2.49K
1% 1/20W MF 201 2
PLACE_NEAR=U1400.U5:12.7 mm
SYNC_MASTER=K16_MLB
PAGE TITLE
MCP PCIe Interfaces

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

16 OF 110
SHEET
16 OF 73
OMIT_TABLE
D
24
MCP89U-A01
BGA
SYMBOL 5 OF 11
U1400
D
G30 F30 AUD_IP_PERIPHERAL_DET MIKEY_MIC_LOAD_DET
IN IN
7 17 37 17
K30 J29
+3.3V_RGBDAC RGB_DAC_VREF
RGB
PP3V3_S0_MCP_DAC 140 mA TP_MCP_RGB_DAC_VREF
DDC_CLK0/GPIO_38 DDC_DATA0/GPIO_39
RGB DAC Disable: Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required Connect +3.3V_RGBDAC pin to GND. (or use as GPIOs).
NOTE: No Composite/S-Video/Component Video support on MCP89

67 9 67 9
OUT OUT OUT OUT OUT OUT OUT OUT
DP_IG_ML0_P<3> DP_IG_ML0_N<3> DP_IG_ML0_P<2> DP_IG_ML0_N<2> DP_IG_ML0_P<1> DP_IG_ML0_N<1> DP_IG_ML0_P<0> DP_IG_ML0_N<0> DP_IG_ML1_P<3> DP_IG_ML1_N<3> DP_IG_ML1_P<2> DP_IG_ML1_N<2> DP_IG_ML1_P<1> DP_IG_ML1_N<1> DP_IG_ML1_P<0> DP_IG_ML1_N<0> DP_IG_HPD0 DP_IG_HPD1 SATARDRVR_A_EN DP_IG_AUX_CH0_P DP_IG_AUX_CH0_N DP_IG_AUX_CH1_P DP_IG_AUX_CH1_N PP3V3_S0_MCP_PLL_DP_USB 210 mA 180 mA
H27 J27 D26 C26 F26 E26 H26 G26 F27 G27 E27 D27 C27 B27 A29 B29
DP0_3_P/TMDS0_TXC_P DP0_3_N/TMDS0_TXC_N DP0_2_P/TMDS0_TX0_P DP0_2_N/TMDS0_TX0_N
IFPA_TXC_P IFPA_TXC_N IFPA_TXD0_P IFPA_TXD0_N
K24 K23 B23 C23 D23 E23 F23 G23 H23 J23 J24 H24 G24 F24 E24 D24 C24 B24 J26 K26 J30 H30
=MCP_IFPA_TXC_P =MCP_IFPA_TXC_N =MCP_IFPA_TXD_P<0> =MCP_IFPA_TXD_N<0> =MCP_IFPA_TXD_P<1> =MCP_IFPA_TXD_N<1> =MCP_IFPA_TXD_P<2> =MCP_IFPA_TXD_N<2> =MCP_IFPA_TXD_P<3> =MCP_IFPA_TXD_N<3> =MCP_IFPB_TXC_P =MCP_IFPB_TXC_N =MCP_IFPB_TXD_P<0> =MCP_IFPB_TXD_N<0> =MCP_IFPB_TXD_P<1> =MCP_IFPB_TXD_N<1> =MCP_IFPB_TXD_P<2> =MCP_IFPB_TXD_N<2> =MCP_IFPB_TXD_P<3> =MCP_IFPB_TXD_N<3> =MCP_IFPAB_DDC_CLK =MCP_IFPAB_DDC_DATA
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
9 9
Interface Mode MCP Signal TMDS/HDMI TMDS_IG_TXC_P/N TMDS_IG_TXD_P/N<0> TMDS_IG_TXD_P/N<1> TMDS_IG_TXD_P/N<2> (UNUSED) (UNUSED) TMDS_IG_TXD_P/N<3> TMDS_IG_TXD_P/N<4> TMDS_IG_TXD_P/N<5> (UNUSED) TMDS_IG_DDC_CLK TMDS_IG_DDC_DATA LVDS LVDS_IG_A_CLK_P/N LVDS_IG_A_DATA_P/N<0> LVDS_IG_A_DATA_P/N<1> LVDS_IG_A_DATA_P/N<2> LVDS_IG_A_DATA_P/N<3> LVDS_IG_B_CLK_P/N LVDS_IG_B_DATA_P/N<0> LVDS_IG_B_DATA_P/N<1> LVDS_IG_B_DATA_P/N<2> LVDS_IG_B_DATA_P/N<3> LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA
67 9 67 9
9 9
67 9 67 9
DP0_1_P/TMDS0_TX1_P DP0_1_N/TMDS0_TX1_N DP0_0_P/TMDS0_TX2_P DP0_0_N/TMDS0_TX2_N DP1_3_P/TMDS0B_TXC_P DP1_3_N/TMDS0B_TXC_N DP1_2_P/TMDS0_TX3_P DP1_2_N/TMDS0_TX3_N DP1_1_P/TMDS0_TX4_P DP1_1_N/TMDS0_TX4_N DP1_0_P/TMDS0_TX5_P DP1_0_N/TMDS0_TX5_N
FLAT PANEL
IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N IFPB_TXC_P IFPB_TXC_N IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N
9 9
67 9 67 9
9 9
9 9
9 9
OUT OUT OUT OUT OUT OUT OUT OUT
9 9
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
9 9
=MCP_IFPA_TXC_P/N =MCP_IFPA_TXD_P/N<0> =MCP_IFPA_TXD_P/N<1> =MCP_IFPA_TXD_P/N<2> =MCP_IFPA_TXD_P/N<3> =MCP_IFPB_TXC_P/N =MCP_IFPB_TXD_P/N<0> =MCP_IFPB_TXD_P/N<1> =MCP_IFPB_TXD_P/N<2> =MCP_IFPB_TXD_P/N<3> =MCP_IFPAB_DDC_CLK =MCP_IFPAB_DDC_DATA
67 9 67 9
9 9
LVDS: Power +VDD_IFPx at 1.8V TMDS: Power +VDD_IFPx at 3.3V
67 9 67 9
9 9
9 9
NOTE: 100K pull-downs required if HPLUG_DET0/HPLUG_DET1 are not used.
9 9 17
IN IN OUT
C29 D30 E30 E29 D29 G29 F29 L23 M23 L22 M22 L25 M25 L26 M26 L27 M27 L28 M28 L24 M24 A23 A24 B26 A27 A26
HPLUG_DET0/GPIO_20 HPLUG_DET1/GPIO_21 HPLUG_DET2/GPIO_22 DDC_CLK2/DP_AUX_CH0_P DDC_DATA2/DP_AUX_CH0_N DDC_CLK3/DP_AUX_CH1_P DDC_DATA3/DP_AUX_CH1_N +3.3V_PLL_DP0 +3.3V_PLL_DP0 +3.3V_PLL_USB +3.3V_PLL_USB +VIO_PLL_IFPAB +VIO_PLL_IFPAB +VIO_PLL_CORE_LEG +VIO_PLL_CORE_LEG +VIO_PLL_SPPLL0 +VIO_PLL_SPPLL0 +VIO_PLL_V +VIO_PLL_V +VIO_PLL_NV +VIO_PLL_NV +VDD_IFPA +VDD_IFPB +VIO_DP0 +VIO_DP0 +VIO_DP0
9 9
67 17 9 67 17 9
BI BI
DDC_CLK1/GPIO_40 DDC_DATA1/GPIO_41
OUT BI
9 9
67 17 9 67 17 9
BI BI
23
LCD_BKL_CTL/GPIO_57 LCD_BKL_ON/GPIO_59 LCD_PANEL_PWR/GPIO_58
B30 C30 A30
(GMUX_INT) LCD_IG_BKLT_PWM LCD_IG_BKLT_EN LCD_IG_PWR_EN
OUT OUT OUT
9 9 9 59
30 mA
24
=PP1V05_S0_MCP_PLL_IFP 60 mA PP1V05_S0_MCP_PLL_CORE 160 mA 40 mA 60 mA 40 mA 20 mA
23
B
IFPAB_VPROBE IFPAB_RSET
C21 B21
MCP_IFPAB_VPROBE MCP_IFPAB_RSET
OUT OUT
24 67
24 67
24
=PP3V3R1V8_S0_MCP_IFP_VDD 180 mA CKPLUS_WAIVE=PwrTerm2Gnd

CKPLUS_WAIVE=PwrTerm2Gnd
24 8
=PP1V05_S0_MCP_DP0_VDD 160 mA
DDC Mode Pull-downs

NOTE: DP_AUX_CH1 also requires pull-downs if used for dual-mode DisplayPort (DP++). If unused no pulls are necessary, if used for TMDS/HDMI only then only pull-ups are necessary.
TMDS0_VPROBE TMDS0_RSET
H29 K27
MCP_TMDS0_VPROBE MCP_TMDS0_RSET
OUT OUT
24 67
24 67
R1710 100K R1711 100K
1 1
2 2
5% 5%
1/20W 1/20W
MF MF
201 201
DP_IG_AUX_CH0_P DP_IG_AUX_CH0_N DP_IG_AUX_CH1_P DP_IG_AUX_CH1_N
9 17 67 9 17 67
R1712 100K 1 R1713 100K 1
2 2 5%
5%
9 17 67 9 17 67
1/20W 1/20W
MF MF
201 201
SYNC_MASTER=K16_MLB
PAGE TITLE
MCP Graphics
DRAWING NUMBER SIZE
=PP3V3_S0_MCP_GPIO
GPIO Pull-Ups
8 18 19
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE
R1780 R1781 R1782
10K 10K 10K
1 1 1
2 2 2
5% 5% 5%
1/20W 1/20W 1/20W
MF MF MF
201 201 201
SATARDRVR_A_EN AUD_IP_PERIPHERAL_DET MIKEY_MIC_LOAD_DET

17 7 17 37 17
17 OF 110
SHEET
17 OF 73
4
OMIT_TABLE
MCP89U-A01
BGA
67 35 67 35
U1400
OUT OUT
SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_D2R_N SATA_HDD_D2R_P
AF1 AG1 AG3 AG2
SYMBOL 6 OF 11
OHCI0/EHCI0
SATA_A0_TX_P SATA_A0_TX_N
USB0_P USB0_N USB1_P USB1_N USB2_P USB2_N USB3_P USB3_N USB4_P USB4_N
67 35
Internal 19.5K Pull-Downs on all USB pairs
67 35
IN IN
SATA_A0_RX_N SATA_A0_RX_P
67 9
OUT OUT
19 17 8
=PP3V3_S0_MCP_GPIO
SATA USB
67 9
SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_D2R_N SATA_ODD_D2R_P
AF2 AF3 AF5 AF4
SATA_A1_TX_P SATA_A1_TX_N SATA_A1_RX_N SATA_A1_RX_P
R1800
100K
67 9 67 9
IN IN
OHCI1/EHCI1
5% 1/20W MF 201 2
MXM_GOOD_L
67
AG5 MCP_SATA_TERMP AG4
SATA_LED*/GPIO_30 SATA_TERMP
USB5_P USB5_N USB6_P USB6_N USB7_P USB7_N USB_OC0*/GPIO_25 USB_OC1*/GPIO_26 USB_RBIAS_GND
Only USB8-11 support nV USB JTAG in S3/S4/S5.
R1805
2.49K G5 V6 AM4 H15 AK36
1% 1/20W MF 2 201
External A USB_EXTA_P USB_EXTA_N AirPort (PCIe Mini-Card) F21 USB_MINI_P G21 USB_MINI_N Geyser Trackpad/Keyboard E20 USB_TPAD_P D20 USB_TPAD_N External C L21 USB_EXTC_P K21 USB_EXTC_N Bluetooth A20 USB_BT_P A21 USB_BT_N Camera/External E H21 USB_CAMERA_P J21 USB_CAMERA_N SD Card/ExpressCard G20 USB_SDCARD_P F20 USB_SDCARD_N EXTERNAL D H20 USB_EXTD_P J20 USB_EXTD_N E21 D21 H14 G12 L19 B15 F15 F17 J17 D15 G14 C14 E15 H18 J14 G17
68
BI BI
36 68 36 68
BI BI
9 68 9 68
BI BI
46 68 71 46 68 71
BI BI
9 68 9 68
BI BI
7 34 68 7 34 68
=PP3V3_S5_MCP_GPIO
1
8 19
R1851
8.2K
BI BI
7 37 68 7 37 68
5% 1/20W MF 2 201
BI BI
9 68 9 68
R18501
8.2K
5% 1/20W MF 201 2
BI BI
7 37 68 7 37 68
NC
USB_EXTA_OC_L USB_EXTD_OC_L MCP_USB_RBIAS_GND MCP_RGMII_VREF TP_ENET_TXD<0> TP_ENET_TXD<1> TP_ENET_TXD<2> TP_ENET_TXD<3> TP_ENET_CLK125M_TXCLK TP_ENET_TX_CTRL TP_ENET_MDC ENET_MDIO TP_MCP_CLK25M_BUF0_R TP_ENET_RESET_L
1
IN
9
36 7 37
C
69 9 69 9 69 9 69 9
RGMII_VREF RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3 RGMII_TXCLK RGMII_TXCTL RGMII_MDC RGMII_MDIO BUF_25MHZ RGMII_RESET*
R1860
887
IN IN IN IN IN IN
ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3> ENET_CLK125M_RXCLK ENET_RX_CTRL ENET_ENERGY_DET PP3V3_ENET_MCP_PLL_MAC 20 mA MCP_MII_COMP_VDD MCP_MII_COMP_GND
C15 H17 C17 G15 D17 A15 E17 J18 K15 K14
RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 RGMII_RXD3 RGMII_RXCLK RGMII_RXCTL RGMII_INTR/GPIO_35
1% 1/20W MF 2 201
23 20 8
=PP3V3_ENET_MCP_RMGT
69 9 69 9
LAN
R18101
49.9
1% 1/20W MF 201 2
IN
23
BI
9 69
+3.3V_PLL_MAC_DUAL RGMII_COMP_VDD RGMII_COMP_GND
69 69
R18111
49.9
1% 1/20W MF 201 2
Internal MAC Disable: Connect RGMII_RXD<0:3> together to 10K pull-down. Connect RGMII_RXCLK to 10K pull-down. Connect RGMII_RXCTL to 10K pull-down. Connect RGMII_INTR to 10K pull-down (if not used as GPIO). +3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail. RGMII_COMP_VDD/_GND must remain connected as shown. Connect RGMII_VREF to 10K pull-down. Connect RGMII_MDIO to 10K pull-down. All other pins can be left TP or NC.
SYNC_MASTER=K16_MLB
PAGE TITLE
MCP SATA, USB & Ethernet

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

18 OF 110
SHEET
18 OF 73
4
=PP3V3_S0_MCP_GPIO OMIT_TABLE
2
3
8 17 18 19
MCP89U-A01
23 8
U1400
BGA
R1961
10K
5% 1/20W MF 201
=PP3V3R1V5_S0_MCP_HDA 70 mA 70 mA
J12
+VDD_HDA
HDA_SDATA_OUT
B3
SYMBOL 7 OF 11
R1950
HDA_SDOUT_R
1
22
68 19
HDA_SDOUT
OUT
7 37 68
R19001
49.9
1% 1/20W MF 201 2
R1951
68 37 7
IN
HDA_SDIN0
C3
HDA_SDATA_IN0 (IPD)
HDA
HDA_BITCLK
B4
68 19
HDA_BIT_CLK_R
22
5% 1/20W MF 201
HDA_BIT_CLK
D
OUT
7 37 68
5% 1/20W MF 201
R1952
1
68
MCP_HDA_PULLDN_COMP
A5
HDA_PULLDN_COMP (IPD)
HDA_RESET*
C4
68 19
HDA_RST_R_L
22
HDA_RST_L
OUT
7 37 68
R1953
HDA_SYNC
A4
68 19
HDA_SYNC_R
22
5% 1/20W MF 201
HDA_SYNC
OUT
7 37 68
BUF_SIO_CLK Frequency
Frequency HDA_SYNC 1 0 24 MHz 14.31818 MHz
5% 1/20W MF 201
68 40 38 7 68 40 38 7 68 40 38 7 68 40 38 7
BI BI BI BI
LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3>
R1910 R1911 R1912 R1913
22 22 22 22
1 1 1 1
2 2 2 2
5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
201 201 201 201

19
LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3> MLB_RAM_CFG1 PM_CLKRUN_L SMC_WAKE_SCI_L PM_LATRIGGER_L AUD_I2C_INT_L SMC_RUNTIME_SCI_L PM_PWRBTN_L PM_SYSRST_DEBOUNCE_L RTC_RST_L
H1 H2 H3 H4 F2 F1 D14 J11 F6 D3 H12 F12 D18 F18 E9 E18 A9 B11 C11 G18 D5 E6 F9 G9 D12 C12 B12 E12 A12 A14 B14 B18 C18
1
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
(IPU) (IPU) (IPU) (IPU)
LPC_SERIRQ (IPU)
H5
LPC_SERIRQ
BI
7 38 40
R1960
LPC
(IPU-S5) (IPU)
LPC_FRAME*
F3
LPC_FRAME_R_L
22
LPC_FRAME_L
OUT
7 38 40 68
LPC_DRQ0*/GPIO_43 (IPU) LPC_CLKRUN*/GPIO_42 (IPU)
5% 1/20W MF 201
(IPD) LPC_RESET* LPC_CLK0
F5 F4 A11 F14 E11 F11 G11 D11 D8 E8 F8 G7 A8 C9 B8 E3 E4 E5 D6 H10 G8 B9 E14 E1 C2 D1 C5 C8 B6 C6 D9 H9 A6 B20 C20
1
LPC_RESET_L LPC_CLK33M_SMC_R MCP_CPU_VTT_EN_L MLB_RAM_CFG0 MLB_RAM_CFG2 SMC_ADAPTER_EN LPCPLUS_GPIO MCP_MEM_VDD_SEL_1V5 MLB_RAM_CFG3 MEM_EVENT_L ENET_LOW_PWR SDCARD_RESET PM_SLP_S3_L PM_SLP_RMGT_L PM_SLP_S4_L MCP_VID<0> MCP_VID<1> MCP_VID<2> MCP_VID<3> SPI_CS0_R_L SPI_CLK_R SPI_MISO SPI_MOSI_R MCP_SPKR MCP_THMDIODE_P MCP_THMDIODE_N SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA AP_PWR_EN PM_CLK32K_SUSCLK_R MCP_TEST_MODE_EN NO STUFF
19 8 19 19 19
OUT OUT
19 25 68
BIOS Boot Select

I/F LPC SPI LPC_FRAME# 0 1
40 38 7
IN
25 68
23 20 8
PP3V3_G3_RTC
38 13 37 7
IN OUT IN IN
R19201
R1921
49.9K
38
SIO_PME*/GPIO_31 EXT_SMI*/GPIO_32 A20GATE/GPIO_55 KBRDRSTIN*/GPIO_56
49.9K
1% 1/20W MF 201 2
1% 1/20W MF 2 201
38 25
IN IN
PWRBTN* (IPU-S5) RSTBTN* (IPU-S5)
MISC_VDDEN0/GPIO_47 MISC_VDDEN1/GPIO_48 MISC_VDDEN2/GPIO_17 MISC_VDDEN3/GPIO_18 MISC_VDDEN4/GPIO_19 MEM_VDD_SEL/GPIO_46
IN BI OUT
19
38 39 57 7 19 40 9
RTC_RST* PWRGD_SB PWRGD
FANCTL0/GPIO_61 FANRPM0/GPIO_60/MGPIO_2 FANCTL1/GPIO_62 FANRPM1/GPIO_63/MGPIO_3 (IPD) SLP_S3* (IPD) SLP_RMGT* (IPD) SLP_S5* MCP_VID0/GPIO_13 MCP_VID1/GPIO_14 MCP_VID2/GPIO_15 MCP_VID3/GPIO_16 SPI_CS0*/GPIO_10 SPI_CLK/GPIO_11 SPI_DI/GPIO_08 SPI_DO/GPIO_09 SPKR/GPIO_1 THERM_DIODE_P THERM_DIODE_N SMB_CLK0 SMB_DATA0 SMB_CLK1/MSMB_CLK SMB_DATA1/MSMB_DATA SMB_ALERT*/GPIO_64 SUS_CLK/GPIO_34
NOTE: MCP89 does not support FWH, only LPC ROMs. So Apple designs will not use LPC for BootROM override.
IN OUT IN OUT OUT OUT OUT OUT OUT OUT OUT OUT IN OUT
19 38 19 19
SPI Frequency Select

Frequency SPI_DO SPI_CLK
NOTE: MCP SLP_S5# pin has the behavior of Intels SLP_S4# signal.
38 25
IN IN
PM_RSMRST_L MCP_PS_PWRGD MCP_WAKE_REQ_L PM_BATLOW_L MCP_MEM_VDD_EN MCP_MEM_VTT_EN SM_INTRUDER_L
7 38 39 57 57 7 19 38 57
25.0 MHz 31.2 MHz 42.7 MHz 62.5 MHz
0 0 1 1
0 1 0 1
39
OUT IN OUT OUT
MCP_WAKE_REQ* MCP_WAKE_DIS* (IPU-S5) MCP_MEMVDD_EN/GPIO_44 MEMVTT_EN/GPIO_45 INTRUDER*
19 54 19 54 19 54 19 54
HDA Output Caps

For EMI Reduction on HDA interface HDA_SDOUT_R HDA_BIT_CLK_R HDA_RST_R_L HDA_SYNC_R
19 68 19 68 19 68 19 68
38
57 21
21
40 68 40 68 19 40 68 40 68
FIXME: AUD_IPHS_SWITCH_EN WAS GPIO_2

39 19 37 19 7 22 19
MISC
OUT OUT OUT BI
C1950
10PF
C1952
10PF
47 40 19 7
SMC_IG_THROTTLE_L AUD_IPHS_SWITCH_EN GFXVCORE_PWR_EN SPIROM_USE_MLB JTAG_MCP_TDI JTAG_MCP_TDO JTAG_MCP_TMS JTAG_MCP_TRST_L JTAG_MCP_TCK MCP_CLK25M_XTALIN MCP_CLK25M_XTALOUT RTC_CLK32K_XTALIN RTC_CLK32K_XTALOUT
MGPU_PIO0/GPIO_6 MGPU_PIO1/GPIO_7 MGPU_PIO2/GPIO_23 MGPU_PIO3/GPIO_24 JTAG_TDI (IPU) JTAG_TDO JTAG_TMS (IPU) JTAG_TRST* (IPD) JTAG_TCK XTALIN XTALOUT XTALIN_RTC XTALOUT_RTC
NOTE: 42 & 62 MHz use FAST_READ command. Straps not provided on this page.
OUT
39
OUT OUT OUT BI OUT BI OUT OUT
44 71 44 71
R1970
10K MCP_SPKR: 0 = USER mode (Normal boot mode) 1 = SAFE mode (For ROMSIP recovery) Connects to SMC for automatic recovery.
5% 25V 2 NPO 201 1
5% 25V 2 NPO 201 1
41 68 41 68 41 68 41 68 19 34 57
13 13 13
IN OUT IN IN IN
5% 1/20W MF 2 201
C1951
10PF
C1953
10PF
13 13
5% 2 25V NPO 201
5% 2 25V NPO 201
25 68
25 25
IN OUT
TEST_MODE_EN PKG_TEST PKG_TEST2
=PP3V3_S3_MCP_GPIO DRAM_CFG3:H DRAM_CFG2:H

1
25 25
IN OUT
R1959
10K
R1966
10K
R1975
1K
DRAM_CFG0:H
1
GPIO Pull-Ups/Downs
=PP3V3_S5_MCP_GPIO =PP3V3_S3_MCP_GPIO =PP3V3_S0_MCP_GPIO
8 18 8 19 8 17 18 19
R19301
10K
5% 1/20W MF 201 2
R1931
100K
5% 1/20W MF 2 201
5% 1/20W MF 2 201
5% 1/20W MF 2 201
1% 1/20W MF 2 201
R19761
5% 1/20W MF 2012
19 19
R1978
10K
10K
5% 1/20W MF 2201
GPIO43 has internal ~9K pull-up.
R1957
10K
5% 1/20W MF
2201
R1991 10K R1981 10K R1999 100K R1986 100K R1983 10K R1987 100K R1989 R1990 R1980
10K 10K 10K
1 1
1
2 2
2
1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2
5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF MF MF MF MF MF MF MF MF MF MF
201 201 201 201 201 201 201 201 201 201 201 201 201 201
SMC_IG_THROTTLE_L AUD_IPHS_SWITCH_EN GFXVCORE_PWR_EN SPIROM_USE_MLB MCP_CPU_VTT_EN_L LPCPLUS_GPIO MEM_EVENT_L ENET_LOW_PWR SDCARD_RESET MCP_VID<0> MCP_VID<1> MCP_VID<2> MCP_VID<3> SPI_MISO AP_PWR_EN
19 19 39 19 7 19 37 19 22 7 19 40 47
MLB_RAM_CFG3 MLB_RAM_CFG2 MLB_RAM_CFG1 MLB_RAM_CFG0 DRAM_CFG3:L
DRAM_CFG2:L DRAM_CFG1:L
1
DRAM_CFG0:L
1
R19771
R1979
10K
R19561
5% 1/20W MF 2012
R1958
10K
5% 1/20W MF
19 7 19 40
Platform-Specific Connections
R1965
68 25 19
5% 1/20W MF 2012
10K
5% 1/20W MF 2201
470
2201
19 38 19 19
IN
LPC_RESET_L
33
LPC_PWRDWN_L
OUT
7 38 40
5% 1/20W MF 201
57 38 19 7
R1992 100K R1993 100K R1994 100K R1995 100K R1998 R1996
20K 10K
SYNC_MASTER=K16_MLB
19 54 19 54 19 54 19 54
IN
PM_SLP_S4_L
MAKE_BASE=TRUE
PM_SLP_S5_L
PAGE TITLE OUT

38
MCP HDA, LPC & MISC

DRAWING NUMBER SIZE
NOTE: MCP SLP_S5# signal has the behavior of Intes SLP_S4# signal
R
Apple Inc.
051-8379
REVISION
19 40 68
4.4.0
BRANCH PAGE
2 5% 201
19 34 57
19 OF 110
SHEET
19 OF 73
5
OMIT_TABLE
4 U1400 MCP89U-A01
3
OMIT_TABLE
2 U1400 MCP89U-A01
1
OMIT_TABLE
NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.
OMIT_TABLE
MCP89U-A01
23 8
U1400
BGA
23 8
=PP1V05_SW_MCP_FSB 2000 mA
SYMBOL 8 OF 11 +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU +VTT_CPU2 +VTT_CPU2 +VTT_CPU2 +VTT_CPU2 +VTT_CPU2 +VTT_CPU2 +VTT_CPU2 +VTT_CPU2 +3.3V_HVDD +3.3V +3.3V +3.3V +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM
23 14 8
C32 E33 L29 AA29 E32 AA30 L31 T30 N30 M31 F33 H33 J32 B33 G33 B32 J33 F32 H32 G32 A33 D32 AB30 AB29 C33 D33 A32 M29 M30 R30 P30 L32 T29 L30 U30 P29 R29 V30 U29 V29 Y30 Y29 W29 W30 N29 K31 =PP1V05_S0_MCP_FSB AC29 200 mA AD29 AC30 AD30 AB31 AC31 AD31 AC32 =PP3V3_S0_MCP_HVDD 30 mA =PP3V3_S0_MCP 250 mA V9 V10 H11 K29
23 8
B
23 8
23 8
L18 =PP0V9_S5_MCP_VDD_AUXC K18 150 mA PP3V3_G3_RTC ?? uA (G3) L20 5 mA (S0) 200 mA K20 J15 A18
+VDD_DUAL_AUXC +VDD_DUAL_AUXC +3.3V_VBAT +3.3V_DUAL_USB +3.3V_DUAL_USB +3.3V_DUAL
23 19 8
AK19 AJ23 AJ24 AK21 AJ17 AK15 AK5 AJ26 AK13 AK16 AJ19 AK12 AK4 AK26 AK20 AJ27 AJ10 AJ12 AK17 AK23 AJ2 AK3 AJ22 AJ21 AK14 AK22 AK8 AK27 AJ4 AK29 AK18 AK24 AJ9 AK11 AK6 AK2 AK25 AJ28 AK9 AK28 AJ11 AJ5 AJ29 AJ3 AJ20 AK10 AJ18 AK1 AJ1 AJ7 AJ8 AJ25 AJ16 AJ15 AK7 AJ6 AJ13 AJ14 AL11 AL12 AL14 AL15 AL17 AL18 AL20 AL21 AL26 AL27 AL29 AL30 K17 L17 A17 B17
=PP1V5R1V35_SW_MCP_MEM 4300 mA
=PPVCORE_S0_MCP 8450 mA (0.85V)
BGA
15 21 23
NOTE: VDD_COREx_SENSE signals should NOT be used for remote sensing unless COREA/COREB are powered by separate regulators. Instead connect regulator sense point as close to COREB FET as possible.
N7 N2 N11 R12 P9 R8 N4 R5 R3 P3 P4 P8 R2 P1 R9 N5 N10 P10 R1 P2 R4 N8 R10 P5 AD24 R7 P6 R6 AB24 AC24 P11 P12 P7 R11 AD23 Y24 AA24 N12 AD17 AD18 AD19 AD20 AD21 AD22 U24 V24 W24 T11 T12 U11 V11 U9 U8 AD8 AD6 AC8 AC9 AD9 AC7 AC10 AD7 AD11 AD10 AC11 AC12 AD12 AE12 AA10 U12 AB10 V12 W11 W12 Y11 Y12 AA11 AA12 AB11 AB12
23
TP_MCP_VDDCOREA_SENSEP TP_MCP_VDDCOREA_SENSEN =PP1V05_S0_MCP_PE_DVDD 8 400 MA (PE0[5:0] PE1[1:0])
SYMBOL 9 OF 11 +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREB +VDD_COREA +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREB +VDD_COREA +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREA +VDD_COREB +VDD_COREB +VDD_COREA_SENSE +VDD_COREB GND_COREA_SENSE +VDD_COREB +VDD_COREB +VDD_COREB +VIO_PE_DVDD +VIO_PE_DVDD +VDD_COREB +VDD_COREB +VIO_PE_DVDD +VDD_COREB +VIO_PE_DVDD +VDD_COREB +VIO_PE_DVDD +VDD_COREB +VIO_PE_DVDD +VDD_COREB +VIO_PE_DVDD +VDD_COREB +VIO_PE_DVDD +VIO_PE_DVDD +VIO_PE_DVDD +VIO_PE_DVDD +VDD_COREB_SENSE +VIO_PE_DVDD GND_COREB_SENSE +VIO_PE_DVDD +VIO_PE_DVDD
M9 K2 L7 M7 Y23 M2 AB23 M11 M12 L8 M8 M10 L10 M6 L12 K10 K7 M1 K8 K5 L9 M3 J4 M4 L11 L5 J2 J1 J7 M5 L4 L3 J3 K11 J6 L2 L1 J5 L6 K4 V23 V17 V19 V18 V20 V21 V22 AB21 Y17 Y18 Y19 Y20 Y21 Y22 AB22 AB17 AB18 AB19 AB20 L13 L14 M13 M14
=PPVCORE_SW_MCP_GFX 15350 mA (0.85V)
BGA
U1400 MCP89U-A01
BGA
G13 E10 B10 AM32 AU25 AY38 W4 AU10 D10 H31 AL31 U31 AT31 AH31 AN25 AC21 AA22 AN16 AE31 AU34 AW19 G10 B22 B19 B34 E22 AC18 K34 AL22 AP36 G34 P31 U21 H25 B31 AU4 AA19 W8 AT19 AT13 AH2 AP19 A38 AT34 AE39 AA18 AT25 AW31 U23 D22 W36 W39 W37 AC23 AP22 AN13 AP31 AU31 AL19 AL2 AA20 E28 AH34 B28 AV40 D28 H28 G36 AE36 B16 E16 AP16 AL36 G19 AA21 K16 K28 D25 AL16 AP4 G25 K25 E31 G16 AP13 U22 AP28 AT28 H16 AH33 AT22 AL8 AA1 AP37 W22 H19 A3 AH8 G28 R31 AW25 AP39 AB33 B25 U10 W34 U19 K12 E34 AL28 AE34 AT39 AP5 W21 D34 E25 K36 D19 Y1 W23 AC22 H22 H8 K19 G2 E2 T5 AC19 AN31 AL37 AU16 AB34 U20 G22 AW36 AL4 C1 E39 D37
SYMBOL 11 OF 11
22 24
SYMBOL 10 OF 11
J9 J8
TP_MCP_VDDCOREB_SENSEP TP_MCP_VDDCOREB_SENSEN PP1V05_S0_MCP_SATA_AVDD 300 mA

23
AL34 AT10 AE4 K37 AL25 T36 T37 AB2 AB4 C40 B5 G4 AE8 AW34 AC20 AE5 W18 AT16 AB5 N34 AT2 W20 AW16 D7 B2 G37 D16 K39 G31 B7 L15 W19 Y10 AW2 AH7 B13 AE37 AV1 AN19 AP10 W33 AB36 K13 AU13 AA23 AA31 Y31 AE33 AY3 N33 T2 B39 T4 AH37 V31 AU37 AW5 AU7 AT7 AN28 D4 AU19 AP25 AU22 AW13 T33 E7 AW7 H13
GND
GND GND
GND
GND GND
23
PP1V05_S0_MCP_PE_AVDD 1000 MA (PE0[5:0], PE1[1:0])
B36 AB37 AE2 AL7 D13 T39 AH4 AB7 AH36 AC17 AH5 AL33 AW10 W17 G39 AB39 AH39 AL5 AW39 AN10 AB8 N39 N36 N37 AE29 AW28 AU28 E19 L16 K22 AW22 T34 AN22 D31 AE30 T8 M16 M15 M17 M18 M19 M20 M21 AE7 W5 W7 AP2 AL10 AP34 U18 T7 W31 AL39 T31 N31 AA17 T10 K33 E13 AL13 AP7 U17 W2 AK34 AK35 H6 H7 V7 V8 AM5
POWER I
POWER II
23 8
=PP3V3_S5_MCP 240 mA 40 mA
+VDD_DUAL_RMGT +VDD_DUAL_RMGT +3.3V_DUAL_RMGT +3.3V_DUAL_RMGT
=PP0V9_ENET_MCP_RMGT 140 mA =PP3V3_ENET_MCP_RMGT 300 mA
8 23
8 18 23
+VIO_PE_AVDD +VIO_PE_AVDD +VIO_PE_AVDD +VIO_PE_AVDD +VIO_PE_AVDD +VIO_PE_AVDD +VIO_PE_AVDD +VIO_PE_AVDD +VIO_PE_AVDD +VIO_PE_AVDD +VIO_PE_AVDD +VIO_PE_AVDD
+VIO_SATA_AVDD +VIO_SATA_AVDD +VIO_SATA_AVDD +VIO_SATA_AVDD +VIO_SATA_AVDD +VIO_SATA_AVDD +VIO_SATA_AVDD +VIO_SATA_AVDD
AF6 AG8 AF7 AF8 AG9 AG6 AF9 AG7 AD1 AD2 AD3 AD4 AC3 AC4 AC5 AD5 AC6 AC1 AC2
+VIO_SATA_DVDD +VIO_SATA_DVDD +VIO_SATA_DVDD +VIO_SATA_DVDD +VIO_SATA_DVDD +VIO_SATA_DVDD +VIO_SATA_DVDD +VIO_SATA_DVDD +VIO_SATA_DVDD +VIO_SATA_DVDD +VIO_SATA_DVDD
=PP1V05_S0_MCP_SATA_DVDD 100 mA
8 23
SYNC_MASTER=K16_MLB
PAGE TITLE
MCP Power & Ground

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

20 OF 110
SHEET
20 OF 73
C2300 helps reduce input rail droop during Q2300 turn-on.

8
=PP1V5R1V35_S0_MCPDDRFET
PLACE_NEAR=Q2300.9:2 mm
CRITICAL
C2300
100UF
Q2300
1
20% 6.3V CERM-X5R 2 1206-1
CRITICAL
9
Part Type Rds(on) Loading

NC
STMFS4854N N-Channel 10 mOhm @3.2V 4.3 A (EDP)
STMFS4855NS
DFN
NC 8
Q2300
D
21 8
=PP5V_S3_MCPDDRFET
4 G
SENSE S
KELVIN 6
MCPDDRFET_KELVIN
OUT
43
C
57 19
VCC
C2305
0.1UF
K1
U2305
SLG5AP031
IN
20% 2 10V CERM 402
2 3
C
MCPDDRFET_SENSE PP1V5R1V35_SW_MCP
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE (OR 1.35V)
OUT
43
NC
MCP_MEM_VDD_EN MCPMEM_CNFG
1
EN
TDFN
D 5 G S
7 6 8
CRITICAL
3
CNFG
MCPMEM_GATE (G driven to VCC) TP_MCPMEM_DONE
R2305
4
1% 1/20W MF 2 201
560K
GND
DONE THRM PAD
=PP1V5R1V35_SW_MCP_MEM 4250 mA
15 20 23
<R1>
Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)
NV Requirements: - Min Ramp-Up Time: 20 uS (10% to 90%) - Max Ramp-Up Time: 65 uS (ENABLE to 90%) - FET Ron <= 3.8 mOhms NOTE: nVidia recommends Infineon BSC030N03MS for Q2300. Gated Rail Savings: 120mW
DIMM CKE Clamps

B
21 8
=PP5V_S3_MCPDDRFET
R23501
10K
5% 1/20W MF 201 2
CKE must be held low to keep memory in self-refresh. Clamps enable before MCP89 MEMVDD rail switched off. Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89. Q2355 Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM. NTUD3170NZXXG Q2355/Q2356 chosen for low output capacitance. SOT-963
CRITICAL 3
D
MEM_A_CKE<0>
BI
15 26 27 32 66
MEMVTT_EN_L
5 4
G S
Q2350
SSM3K15FV
SOD-VESM-HF
D 3
6
D
MEM_A_CKE<1>
BI
15 26 27 32 66
1 G
19
S 2
2 1
G S
IN
MCP_MEM_VTT_EN
NO STUBS on CKE signals!

CRITICAL
NTUD3170NZXXG
SOT-963 3
D
Q2356
MEM_B_CKE<0>
BI
15 28 29 32 66
5 4
G S
SYNC_MASTER=K16_MLB
PAGE TITLE
MCP89 Memory Rail Gating

6
MEM_B_CKE<1>
DRAWING NUMBER BI
15 28 29 32 66
SIZE
D
R
Apple Inc.
051-8379
REVISION
4.4.0
BRANCH PAGE
2 1
G S
23 OF 110
SHEET
21 OF 73
C2400 helps reduce input rail droop during Q2400 turn-on.

PLACE_NEAR=C2400.1:1 mm
8
=PPVCORE_S0_MCPGFXFET
XW2400 SM
1 2
MCPCORES0_VSEN_P
OUT
54 71
CRITICAL
1
C2400
100UF
20% 2 6.3V CERM-X5R 1206-1
XW2401 SM
1 2
MCPCORES0_VSEN_N
OUT
54 71
8
=PP5V_S0_MCPFSBFET
5 6 7 8 1
Q2400
Part CRITICAL
D
Si4838BDY N-Channel 3.2 mOhm @2.5V 15.35 A (EDP)
C
19
VCC
C2405
0.1UF
4
G
Type Rds(on) Loading
U2405
SLG5AP033
IN
20% 2 10V CERM 402
Q2400
SI4838BDY
SO-8
GFXVCORE_PWR_EN MCPGFX_CNFG
1
EN
TDFN
D 5 G S
7 6 8
CRITICAL
3
CNFG
MCPGFX_GATE (G driven to VCC) TP_MCPGFX_DONE
1 2 3
PPVCORE_SW_MCP_GFX
C2406
820PF
GND
4
10% 50V 2 CERM 402
DONE THRM PAD

9
=PPVCORE_SW_MCP_GFX
20 24
<C1>
Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)
NV Requirements: - Min Ramp-Up Time: 100 uS (10% to 90%) - Max Ramp-Up Time: 1500 uS (ENABLE to 90%) - FET Ron <= 2.5 mOhms NOTE: nVidia recommends Infineon BSC020N03MS for Q2400. Gated Rail Savings: 860mW
SYNC_MASTER=K16_MLB
PAGE TITLE
MCP89 GFX Core Rail Gating

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

24 OF 110
SHEET
22 OF 73
8
MCP Non-GFX Core Power
20 8
5
8
4
=PP1V05_S0_MCP_AVDD_UF 800 mA 30-OHM-5A
1 0603 2
3
L2560
1
MCP 1.05V PCIe Analog Power
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM500 VOLTAGE=1.05V
=PPVCORE_S0_MCP 8450 mA (0.85V) OMIT_TABLE
PP1V05_S0_MCP_PE_AVDD mA
20
C2500 1
10UF
20% 6.3V 2 X5R 603-1
C2501
4.7UF
C2502
1.0UF
C2503
0.22UF
C2504
0.1UF
C2505
0.1UF
C2506
0.1UF
C2507
0.1UF
C2508
0.1UF
OMIT_TABLE
C2560 1
10UF
20% 6.3V 2 X5R 603-1
C2561
4.7UF
1 C2559
20% 2 4V X5R-1 402
20% 2 6.3V X5R 0201
20% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
20% 2 4V X5R-1 402
4.7UF
20% 4V X5R-1 402
C2562
1.0UF
C2563
1.0UF
C2564
0.1UF
C2565
0.1UF
C2566
0.1UF
20% 6.3V 2 X5R 0201
20% 6.3V 2 X5R 0201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
D
21 20 15
MCP Memory Power =PP1V5R1V35_SW_MCP_MEM 4300 mA (1.5V)

1
30-OHM-5A
2 0603
L2567
MCP 1.05V SATA Analog Power

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
1
PP1V05_S0_MCP_SATA_AVDD 300 mA
20
C2510
4.7UF
C2511
0.1UF
C2512
0.1UF
C2513
0.1UF
C2514
0.1UF
C2515
0.1UF
C2516
0.1UF
C2517
0.1UF
C2518
0.1UF
C2519
0.1UF
OMIT_TABLE
C2567 1
10UF
20% 6.3V 2 X5R 603-1
C2568
4.7UF
C2569
0.1UF
20% 4V X5R-1 2 402
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
20% 4V 2 X5R-1 402
10% 6.3V 2 X5R 201
MCP CPU FSB (VTT) Power

20 8
MCP S0 FSB (VTT) Power

20 14 8
CRITICAL
8
=PP1V05_SW_MCP_FSB 2000 mA OMIT_TABLE
=PP1V05_S0_MCP_FSB 200 mA
=PP1V05_S0_MCP_PLL_UF 555 mA
220-OHM-2.2A
1 0603 2
L2570
MCP 1.05V CPU/FSB/MEM PLL Power

1
PP1V05_S0_MCP_PLL_FSBMEM 70 mA
15
C2520 1
10UF
20% 6.3V 2 X5R 603-1
C2521
4.7UF
C2522
1.0UF
C2523
1.0UF
C2524
4.7UF
C2525
1.0UF
C2570 1
20% 4V X5R-1 2 PLACE_NEAR=R2570.1:50 mil 402
20% 4V 2 X5R-1 402
20% 6.3V 2 X5R 0201
20% 6.3V 2 X5R 0201
20% 4V X5R-1 2 402
20% 6.3V 2 X5R 0201
4.7UF
C2571
0.1UF
C2572
0.1UF
C2573
0.1UF
R2570
1
GND_MCP_PLL_FSB
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=0V
0.33 2
5% 1/16W MF 0402
10% 6.3V 2 X5R 201
10% 6.3V 2 X5R 201
10% 6.3V 2 X5R 201
MCP 0.9V AUX Core Power

20 8
MCP 0.9V MAC/SMU Power

20 8
CRITICAL
=PP0V9_S5_MCP_VDD_AUXC 150 mA
1
=PP0V9_ENET_MCP_RMGT 140 mA
220-OHM-2.2A
1 0603 1 1 2
L2575
MCP 1.05V PCIe/SATA PLL Power

1
PP1V05_S0_MCP_PLL_PEXSATA 325 mA
16
C2526
0.1UF
C2527
0.1UF
C2528
4.7UF
C2529
0.1UF
C2575 1
4.7UF
20% 4V X5R-1 2 402
C2576
0.1UF
C2577
0.1UF
C2578
0.1UF
C2579
0.1UF
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
20% 4V X5R-1 2 402
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
MCP 1.05V PCIE Digital Power

20 8
MCP 1.05V SATA Digital Power

20 8
CRITICAL 220-OHM-2.2A
1 0603 2
L2580
MCP 1.05V Core/Misc PLL Power

1
=PP1V05_S0_MCP_PE_DVDD 200 mA
=PP1V05_S0_MCP_SATA_DVDD 100 mA
PP1V05_S0_MCP_PLL_CORE 160 mA
17
C2530 1 C2538 1
4.7UF
20% 4V X5R-1 2 402
4.7UF
20% 4V X5R-1 402
C2531
1.0UF
C2532
1.0UF
1 1 C2533 C2534 C2535
20% 6.3V 2 X5R 0201
20% 2 6.3V X5R 0201
10% 2 6.3V X5R 201
0.1UF
10% 2 6.3V X5R 201
0.1UF
10% 2 6.3V X5R 201
0.1UF
C2536
4.7UF
C2537
0.1UF
C2580 1
4.7UF
20% 4V X5R-1 2 402
C2581
0.1UF
C2582
0.1UF
C2583
0.1UF
C2584
0.1UF
20% 4V X5R-1 2 402
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
MCP 3.3V PCIe/SATA I/O PLL Power MCP 1.05V Memory DLL Power
20 8 15 8
MCPHVDD:P3V3 CRITICAL
8
=PP1V05_S0_MCP_M2CLK_DLL 550 mA
=PP3V3_S0_MCP_HVDD 30 mA
=PP3V3_S0_MCP_PLL_UF 260 mA MCPHVDD:P2V5
FERR-240-OHM-200MA
1 0402 2
L2590
MCP 3.3V PLL Power PP3V3_S0_MCP_PLL_HVDD MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 50 mA

VOLTAGE=3.3V
16
C2540 1
4.7UF
20% 4V X5R-1 2 402
C2541
4.7UF
C2542
0.1uF
MCPHVDD:P2V5
20% 6.3V 2 CERM 603
20% 2 10V CERM 402
R25901
10K
5% 1/20W MF 201 2
C2592 1
1.0UF
20% 6.3V 2 X5R 0201
CRITICAL OMIT_TABLE
HVDDLDO:ADJ
C2590
4.7UF
C2591
0.1UF
R25911
665K
U2590
MIC5365-2.5V 1 VIN SC70 VOUT 5 3 EN GND 2 NC 4
B
MCP 3.3V I/O Power
20 8
<Ra>
P2V8HVDD_FB HVDDLDO:ADJ
1% 1/20W MF 201 2
20% 6.3V 2 CERM 603
20% 2 10V CERM 402
MCP 3.3V/1.5V HDA Power

19 8
P2V8HVDD_EN
=PP3V3_S0_MCP 250 mA
=PP3V3R1V5_S0_MCP_HDA 70 mA
R25921
316K
C2543 1
4.7uF
20% 6.3V 2 CERM 603
C2544
0.1uF
C2545
0.1uF
C2546
0.1uF
C2547
0.1uF
C2548
4.7UF
C2549
0.1UF
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 10V 2 CERM 402
20% 6.3V 2 CERM 603
10% 2 6.3V X5R 201
<Rb> Vout = 0.8V * (Ra + Rb) / Rb, Rb ~ 320kOhms

PART NUMBER 353S2988 QTY 1 1 DESCRIPTION
IC,MIC5366,LDO REG,2.5V,150MA,SC70
1% 1/20W MF 201 2
REFERENCE DES U2590 U2590
CRITICAL CRITICAL CRITICAL
BOM OPTION HVDDLDO:FIXED HVDDLDO:ADJ
MCP 3.3V AUX/USB Power

20 8
353S2979
MCP 2.0V-3.3V RTC Power
20 19 8
IC,LDO,TPS717,ADJ,150MA,3%,SC70,HF
=PP3V3_S5_MCP 240 mA
CRITICAL 220-OHM-2.2A
C2550 1
4.7uF
20% 6.3V 2 CERM 603
C2551
0.1uF
PP3V3_G3_RTC ? uA (G3) 5 mA (S0)
L2595
0603
MCP 3.3V DP & USB PLL Power

2
C2552
4.7UF

1
PP3V3_S0_MCP_PLL_DP_USB 210 mA
17
20% 2 10V CERM 402
20% 6.3V 2 CERM 603
C2595 1
20% 6.3V 2 PLACE_NEAR=R2595.1:50 mil CERM 603
4.7UF
C2596
0.1UF
C2597
0.1uF
R2595
1
MCP 3.3V MAC/SMU Power
GND_MCP_PLL_DP_USB MCP 3.3V MAC PLL POWER

8
0.33 2
5% 1/16W MF 0402
20% 2 10V CERM 402
20% 2 10V CERM 402
20 18 8
=PP3V3_ENET_MCP_RMGT 300 mA
CRITICAL FERR-240-OHM-200MA
1
0402
L2555
SYNC_MASTER=K16_MLB
PAGE TITLE
C2553 1
4.7uF
20% 6.3V 2 CERM 603
C2554
0.1uF
=PP3V3_ENET_MCP_PLL_MAC 20 mA
PP3V3_ENET_MCP_PLL_MAC 20 mA 0.1UF
18
MCP Standard Decoupling

DRAWING NUMBER SIZE
20% 10V 2 CERM 402
C2555 1
4.7UF
20% 6.3V CERM 603
1 C2556 2
20% 10V CERM 402
R
Apple Inc.
051-8379
REVISION
4.4.0
BRANCH PAGE
25 OF 110
SHEET
23 OF 73
8
MCP GFX Core Power
22 20
=PPVCORE_SW_MCP_GFX 15350 mA (0.85V) OMIT_TABLE
C2600 1
10UF
20% 6.3V 2 X5R 603-1
C2601
4.7UF
C2602
1.0UF
C2603
1.0UF
C2604
0.22UF
C2605
0.22UF
C2606
0.1UF
C2607
0.1UF
C2608
0.1UF
C2609
0.1UF
C2610
0.1UF
C2611
0.1UF
C2612
0.1UF GND_MCP_DAC_P3V3
MCP 3.3V RGBDAC Power

1 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V MAKE_BASE=TRUE
20% 2 4V X5R-1 402
20% 2 6.3V X5R 0201
20% 2 6.3V X5R 0201
20% 2 6.3V X5R 201
20% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
10% 2 6.3V X5R 201
R2670
0
PP3V3_S0_MCP_DAC 140 mA
17
5% 1/20W MF 201 2
If RGBDAC is used, requires ferrite (155S0382) plus 1x 4.7uF 0603 & 1x 0.1uF 0402 cap. If RGBDAC is not used, tie to GND.
=PP3V3R1V8_S0_MCP_IFP_VDD
17
=PP1V05_S0_MCP_PLL_IFP
17
MCP 1.05V DisplayPort Power

17 8
=PP1V05_S0_MCP_DP0_VDD 160 mA
C2640 1
4.7UF
20% 4V X5R-1 2 402
C2641
0.1UF
10% 6.3V 2 X5R 201
67 17 67 17
MCP_TMDS0_RSET MCP_TMDS0_VPROBE NO STUFF
67 17 67 17
C2650
0.1UF
R2650
1K
MCP_IFPAB_RSET MCP_IFPAB_VPROBE NO STUFF
NO STUFF
1
10% 6.3V 2 X5R 201
1% 1/20W MF 2 201
C2655
0.1UF
R2655
1K
10% 6.3V 2 X5R 201
1% 1/20W MF 2 201
SYNC_MASTER=K16_MLB
PAGE TITLE
MCP Graphics Support

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

26 OF 110
SHEET
24 OF 73
RTC Crystal
C2810 R2810
0
19
Platform Reset Connections

LPC Reset (Unbuffered)
R2881
CRITICAL
4
12PF
2
IN
RTC_CLK32K_XTALOUT NO STUFF
1 5% 1/20W MF 201
RTC_CLK32K_XTALOUT_R
R2811
D
19
10.0M
5% 1/20W MF 0201
Y2810
32.768K
7X1.5X1.4-SM 1
5% 25V NP0-C0G 201
PLACEMENT_NOTE=Place close to U1400
33
1 5% 1/20W MF 201 1 2
68 19
IN
LPC_RESET_L
LPCPLUS_RESET_L
OUT
7 40
R2883
33
2 5% 1/20W MF 201
D
38
C2811
12PF
1 2
SMC_LRESET_L
OUT
OUT
RTC_CLK32K_XTALIN
5% 25V NP0-C0G 201
MCP 25MHz Crystal

R2815
0
19
C2815
12PF
2
PCIE Reset (Unbuffered)

R2891
IN
MCP_CLK25M_XTALOUT NO STUFF
1 5% 1/20W MF 201
MCP_CLK25M_XTALOUT_R
R2816
1M
5% 1/20W MF 201
CRITICAL
Y2815
25.0000M
SM-3.2X2.5MM 1 2 2
NC NC
5% 25V NP0-C0G 201
0
16
IN
PCIE_RESET_L
MAKE_BASE=TRUE
1 5% 1/20W MF 201 2 5% 1/20W MF 201 1 5% 1/20W MF 201
PCA9557D_RESET_L
OUT
33
C2816
12PF
1 2 1
R2893
0
BKLT_PLT_RST_L
OUT
63
19
OUT
MCP_CLK25M_XTALIN
5% 25V NP0-C0G 201
R2894
0
2
AP_RESET_L
OUT
34
R2825
33
1 5% 1/20W MF 201 1 5% 1/20W MF 201 2
68 19
IN
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
OUT
38 68
R2826
33
2
LPC_CLK33M_LPCPLUS
OUT
7 40 68
B
R2829
22
68 19
IN
PM_CLK32K_SUSCLK_R
1 PLACEMENT_NOTE=Place close to U1400 5% 1/20W MF 201
PM_CLK32K_SUSCLK
OUT
38 68
MCP S0 PWRGD & CPU_VLD

8
=PP3V3_S5_MCPPWRGD
System Reset Circuit

1
C2850
0.1UF
10% 6.3V X5R 201
38
IN
PM_SYSRST_L XDP
A
5
57 49 38
R2896
0
13 10
R2899
33
2
1 2
10K pull-up to 3.3V S0 inside MCP PM_SYSRST_DEBOUNCE_L NO STUFF

1
IN
XDP_DBRESET_L
1 5% 1/20W MF 201
SYNC_MASTER=K6_MLB
OUT
19
PAGE TITLE
OMIT
5% 1/20W 1 MF 201
IN
ALL_SYS_PWRGD
74LVC1G08GW
SOT353
R2897
0
5% 1/16W MF-LF 402
C2899
1.0UF
20% 6.3V
SB Misc
DRAWING NUMBER SIZE
B A
3
U2850 Y
53
MCP_PS_PWRGD
OUT
19
X5R 0201
Apple Inc.
R
051-8379
REVISION
IN
VR_PWRGOOD_DELAY
SILK_PART=SYS RST PLACEMENT_NOTE=Place R2897 on BOTTOM
4.4.0
BRANCH PAGE

28 OF 110
SHEET
25 OF 73
33 29 28 27 26
PPVREF_S3_MEM_VREFCA
33 29 28 27 26
33 29 28 27 26
PPVREF_S3_MEM_VREFCA PPVREF_S3_MEM_VREFDQ
33 29 28 27 26
33 29 28 27 26
PPVREF_S3_MEM_VREFDQ
=PPLVDDR_S3_MEM_A
33 29 28 27 26
=PPLVDDR_S3_MEM_A
33 29 28 27 26
E1
J8
A2 A9 D7 G2 G8 K1 K9 M1 M9
B9 C1 E2 E9
=PPLVDDR_S3_MEM_A B9 C1 E2 E9
1 2
33 29 28 27 26
1 2
E1
J8
A2 A9 D7 G2 G8 K1 K9 M1 M9
E1
J8
A2 A9 D7 G2 G8 K1 K9 M1 M9
E1
J8
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
201 4V
201 4V
0.47UF 0.47UF 2 2 CERM-X5R-1 CERM-X5R-1

201 4V 201 4V
U3100
128MX8-SDRAM-1066MHZ
FBGA

201 4V 201 4V
20%
20%
VDD
VDDQ
VREFCA
20%
20%
VDD
VDDQ
0.47UF 20%
1 1 C3110 C3111
20% 20%
4V CERM-X5R-1 201
VDD
VDDQ
0.47UF
1 1 C3120 C3121
C3122
0.47UF 20%
4V CERM-X5R-1 201
A2 A9 D7 G2 G8 K1 K9 M1 M9
1 1 C3100 C3101
B9 C1 E2 E9
C3102
C3112
20% 4V CERM-X5R-1 201
1 1 C3130 C3131 0.47UF 0.47UF 2 2 CERM-X5R-1 CERM-X5R-1

201 4V 201 4V 20% 20%
C3132
0.47UF 20%
4V CERM-X5R-1 201
VDD
VDDQ
U3110
FBGA
MT41J128M8HX-187E
MEM_RESET_L N2 29 28 27 26 15 R3100 240 2 MEM_A_ZQ0 1 H8 MF 1%1/20W 201 K3 MEM_A_A<0> 66 32 27 26 15 L7 66 32 27 26 15 MEM_A_A<1> L3 66 32 27 26 15 MEM_A_A<2> K2 66 32 27 26 15 MEM_A_A<3> L8 66 32 27 26 15 MEM_A_A<4> L2 66 32 27 26 15 MEM_A_A<5> M8 66 32 27 26 15 MEM_A_A<6> M2 MEM_A_A<7> 66 32 27 26 15 N8 66 32 27 26 15 MEM_A_A<8> M3 66 32 27 26 15 MEM_A_A<9> H7 66 32 27 26 15 MEM_A_A<10> M7 66 32 27 26 15 MEM_A_A<11> K7 66 32 27 26 15 MEM_A_A<12> N3 66 32 27 26 15 MEM_A_A<13>
66 32 27 26 15 66 32 27 26 15 66 32 27 26 15
66 32 27 26 15
66 32 27 26 15
RESET* ZQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DQS* DM/TDQS TDQS*
B3MEM_A_DQ<7> C7MEM_A_DQ<1> C2MEM_A_DQ<0> C8MEM_A_DQ<3> E3MEM_A_DQ<4> E8MEM_A_DQ<2> D2MEM_A_DQ<5> E7MEM_A_DQ<6>
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66
C3MEM_A_DQS_P<0> D3MEM_A_DQS_N<0> B7MEM_A_DM<0> A7 NC A3 NC

15 66
15 66
15 66
MEM_RESET_L RESET* N2 R3110 240 2 MEM_A_ZQ1 ZQ 1 H8 MF 1%1/20W 201 K3 A0 66 32 27 26 15 MEM_A_A<0> L7 A1 66 32 27 26 15 MEM_A_A<1> L3 A2 66 32 27 26 15 MEM_A_A<2> K2 A3 MEM_A_A<3> 66 32 27 26 15 L8 A4 66 32 27 26 15 MEM_A_A<4> L2 A5 66 32 27 26 15 MEM_A_A<5> M8 A6 66 32 27 26 15 MEM_A_A<6> M2 A7 66 32 27 26 15 MEM_A_A<7> N8 A8 66 32 27 26 15 MEM_A_A<8> M3 A9 66 32 27 26 15 MEM_A_A<9> H7 MEM_A_A<10> A10/AP 66 32 27 26 15 M7 A11 66 32 27 26 15 MEM_A_A<11> K7 A12/BC* 66 32 27 26 15 MEM_A_A<12> N3 A13 66 32 27 26 15 MEM_A_A<13>
29 28 27 26 15 66 32 27 26 15 66 32 27 26 15 66 32 27 26 15
B3MEM_A_DQ<8> 15 66 C7MEM_A_DQ<14> 15 66 C2MEM_A_DQ<9> 15 66 C8MEM_A_DQ<12> 15 66 E3MEM_A_DQ<10> 15 66 E8MEM_A_DQ<11> 15 66 D2MEM_A_DQ<13> 15 66 E7MEM_A_DQ<15> 15 66 C3MEM_A_DQS_P<1> D3MEM_A_DQS_N<1> B7MEM_A_DM<1> A7 NC A3 NC
15 66 15 66
15 66
J2 MEM_A_BA<0> BA0 K8 MEM_A_BA<1> BA1 J3 MEM_A_BA<2> BA2 G9 MEM_A_CKE<0> CKE F7 CK MEM_A_CLK_P<0> G7 CK* MEM_A_CLK_N<0> H2 MEM_A_CS_L<0>CS*
MEM_A_CS_L<1>NC H1 MEM_A_RAS_L RAS* F3 MEM_A_CAS_L CAS* G3
MEM_RESET_L RESET* N2 R3120 240 2MEM_A_ZQ2 ZQ 1 H8 MF 1%1/20W 201 K3 A0 66 32 27 26 15 MEM_A_A<0> L7 A1 66 32 27 26 15 MEM_A_A<1> L3 A2 66 32 27 26 15 MEM_A_A<2> K2 A3 66 32 27 26 15 MEM_A_A<3> L8 A4 66 32 27 26 15 MEM_A_A<4> L2 A5 66 32 27 26 15 MEM_A_A<5> M8 A6 MEM_A_A<6> 66 32 27 26 15 M2 A7 66 32 27 26 15 MEM_A_A<7> N8 A8 66 32 27 26 15 MEM_A_A<8> M3 A9 66 32 27 26 15 MEM_A_A<9> H7 A10/AP 66 32 27 26 15 MEM_A_A<10> M7 A11 66 32 27 26 15 MEM_A_A<11> K7 A12/BC* 66 32 27 26 15 MEM_A_A<12> N3 MEM_A_A<13> A13 66 32 27 26 15
29 28 27 26 15 66 32 27 26 15 66 32 27 26 15 66 32 27 26 15
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66

15 66
15 66
15 66
MEM_RESET_L RESET* N2 R3130 240 2 MEM_A_ZQ3 ZQ 1 H8 MF 1%1/20W 201 K3 A0 66 32 27 26 15 MEM_A_A<0> L7 A1 66 32 27 26 15 MEM_A_A<1> L3 A2 66 32 27 26 15 MEM_A_A<2> K2 A3 66 32 27 26 15 MEM_A_A<3> L8 A4 66 32 27 26 15 MEM_A_A<4> L2 A5 66 32 27 26 15 MEM_A_A<5> M8 A6 MEM_A_A<6> 66 32 27 26 15 M2 A7 66 32 27 26 15 MEM_A_A<7> N8 A8 66 32 27 26 15 MEM_A_A<8> M3 A9 66 32 27 26 15 MEM_A_A<9> H7 A10/AP 66 32 27 26 15 MEM_A_A<10> M7 A11 66 32 27 26 15 MEM_A_A<11> K7 A12/BC* 66 32 27 26 15 MEM_A_A<12> N3 MEM_A_A<13> A13 66 32 27 26 15
29 28 27 26 15 66 32 27 26 15 66 32 27 26 15 66 32 27 26 15
MT41J128M8HX-187E
66 32 27 26 15
MT41J128M8HX-187E
66 32 27 26 15
MT41J128M8HX-187E
MEM_A_ODT<0> ODT G1
OMIT_TABLE
U3120
FBGA OMIT_TABLE
U3130
FBGA OMIT_TABLE
MEM_A_ODT<0> ODT G1
OMIT_TABLE
MEM_A_ODT<0> ODT G1
MEM_A_ODT<0> ODT G1
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66

15 66
15 66
15 66
MEM_A_CS_L<1>NC H1 MEM_A_RAS_L RAS* F3
J2 MEM_A_BA<0> BA0 K8 MEM_A_BA<1> BA1 J3 MEM_A_BA<2> BA2 G9 MEM_A_CKE<0> CKE F7 CK MEM_A_CLK_P<0> G7 CK* MEM_A_CLK_N<0>
MEM_A_CS_L<0>CS* H2 MEM_A_CS_L<1>NC H1
MEM_A_CS_L<0>CS* H2 MEM_A_CS_L<1>NC H1 MEM_A_RAS_L RAS* F3 MEM_A_CAS_L CAS* G3
32 27 26 21 15 66 66 32 27 26 15 66 32 27 26 15
66 32 27 26 21 15
66 32 27 26 21 15 66 32 27 26 15
66 32 27 26 21 15
NC
66 32 27 26 15
66 32 27 26 15
66 32 27 26 15
F1 MEM_A_ODT<1> 15 26 F9 MEM_A_CKE<1> 15 21 H9 MEM_A_ZQ0 26 N7 J7 NC MEM_A_A<14> 15
66 32 27 26 15
66 32 27 26 15
27 32 66
27 26 15 66 32
NC
26 27 32 66 66 32 27 26 15
66 32 27 26 15 26 27 32 66 66 32 27 26 15
F1 MEM_A_ODT<1> 15 26 F9 MEM_A_CKE<1> 15 21 H9 MEM_A_ZQ1 26 N7 J7 NC MEM_A_A<14> 15
27 32 66 66 32 27 26 15 26 27 32 66 66 32 27 26 15
NC
66 32 27 26 15 26 27 32 66 66 32 27 26 15
F3 MEM_A_RAS_L RAS*
MEM_A_CAS_L CAS* G3 MEM_A_WE_L H3 WE*
VSS VSSQ
66 32 27 26 15
66 32 27 26 15 66 32 27 26 15
G3 MEM_A_CAS_L CAS*
66 32 27 26 15
F1 MEM_A_ODT<1> 15 26 F9 MEM_A_CKE<1> 15 21 27 32 H9 MEM_A_ZQ2 26 N7 J7 NC MEM_A_A<14> 15 27
66 32 27 26 15 27 32 66 26 66 32 27 26 15 66 66 32 27 26 15
NC
26 66 32 27 26 15 32 66 66 32 27 26 15
F1 MEM_A_ODT<1> 15 26 32 66 F9 MEM_A_CKE<1> 15 21 27 32 H9 MEM_A_ZQ3 26 N7 66 J7 NC MEM_A_A<14> 15 27
27 26 66
26 32
MEM_A_WE_L H3 WE*
66 32 27 26 15
H3 WE* MEM_A_WE_L
66 32 27 26 15
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
VSS
VSSQ VSS VSSQ
66 32 27 26 15
H3 WE* MEM_A_WE_L
VSS VSSQ
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
A14/A15 FOR 2G/4G MONO ONLY CS1 IS FOR 2G DDP RANK CONTROL
B2 B8 C9 D1 D9
SYNC_MASTER=K16_MLB
PAGE TITLE

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
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=PPLVDDR_S3_MEM_A
33 29 28 27 26
30 27 26 8
=PPLVDDR_S3_MEM_A
33 29 28 27 26
E1
J8
A2 A9 D7 G2 G8 K1 K9 M1 M9
B9 C1 E2 E9
1 2
33 29 28 27 26
1 2
E1
J8
A2 A9 D7 G2 G8 K1 K9 M1 M9
E1
J8
A2 A9 D7 G2 G8 K1 K9 M1 M9
E1
J8
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
201 4V
201 4V

201 4V 201 4V
U3200
FBGA
4V CERM-X5R-1 201

201 4V 201 4V
20%
20%
VDD
VDDQ
VREFCA
20%
20%
VDD
VDDQ
0.47UF 20%
1 1 C3210 C3211
20% 20%
4V CERM-X5R-1 201
VDD
VDDQ
0.47UF 20%
1 1 C3220 C3221
C3222
0.47UF
20% 4V CERM-X5R-1 201
A2 A9 D7 G2 G8 K1 K9 M1 M9
1 1 C3200 C3201
B9 C1 E2 E9
C3202
C3212

201 4V 201 4V 20% 20%
C3232
0.47UF
20% 4V CERM-X5R-1 201
VDD
VDDQ
U3210
FBGA
MT41J128M8HX-187E
MEM_RESET_L RESET* N2 29 28 27 26 15 R3200 240 2 MEM_A_ZQ8 ZQ 1 H8 MF 1%1/20W 201 K3 A0 66 32 27 26 15 MEM_A_A<0> L7 A1 66 32 27 26 15 MEM_A_A<1> L3 A2 66 32 27 26 15 MEM_A_A<2> K2 A3 66 32 27 26 15 MEM_A_A<3> L8 A4 MEM_A_A<4> 66 32 27 26 15 L2 A5 66 32 27 26 15 MEM_A_A<5> M8 A6 66 32 27 26 15 MEM_A_A<6> M2 A7 66 32 27 26 15 MEM_A_A<7> N8 A8 66 32 27 26 15 MEM_A_A<8> M3 A9 66 32 27 26 15 MEM_A_A<9> H7 A10/AP 66 32 27 26 15 MEM_A_A<10> M7 MEM_A_A<11> A11 66 32 27 26 15 K7 A12/BC* 66 32 27 26 15 MEM_A_A<12> N3 A13 66 32 27 26 15 MEM_A_A<13>
66 32 27 26 15 66 32 27 26 15 66 32 27 26 15
66 32 27 26 15
66 32 27 26 15
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66
C3MEM_A_DQS_P<4> D3MEM_A_DQS_N<4> B7MEM_A_DM<4> A7 NC NC A3 NC NC NC NC F1 MEM_A_ODT<1> F9 MEM_A_CKE<1> H9 MEM_A_ZQ8 27 N7 J7 NC

15 66
15 66
15 66
MEM_RESET_L N2 R3210 240 2MEM_A_ZQ9 1 H8 MF 1%1/20W 201 K3 MEM_A_A<0> 66 32 27 26 15 L7 66 32 27 26 15 MEM_A_A<1> L3 66 32 27 26 15 MEM_A_A<2> K2 66 32 27 26 15 MEM_A_A<3> L8 66 32 27 26 15 MEM_A_A<4> L2 66 32 27 26 15 MEM_A_A<5> M8 66 32 27 26 15 MEM_A_A<6> M2 MEM_A_A<7> 66 32 27 26 15 N8 66 32 27 26 15 MEM_A_A<8> M3 66 32 27 26 15 MEM_A_A<9> H7 66 32 27 26 15 MEM_A_A<10> M7 66 32 27 26 15 MEM_A_A<11> K7 66 32 27 26 15 MEM_A_A<12> N3 66 32 27 26 15 MEM_A_A<13>
29 28 27 26 15 66 32 27 26 15 66 32 27 26 15 66 32 27 26 15
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66
C3MEM_A_DQS_P<5> D3MEM_A_DQS_N<5> B7MEM_A_DM<5> A7 NC NC A3 NC NC NC NC F1 MEM_A_ODT<1> 15 F9 MEM_A_CKE<1> 15 H9 MEM_A_ZQ9 27 N7 J7 NC

15 66
15 66
15 66
MEM_A_CS_L<0>CS* H2 MEM_A_CS_L<1>NC H1 MEM_A_RAS_L RAS* F3
29 28 27 26 15 66 32 27 26 15 66 32 27 26 15 66 32 27 26 15
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66
C3MEM_A_DQS_P<6> D3MEM_A_DQS_N<6> B7MEM_A_DM<6> A7 NC NC A3 NC NC NC NC

15 66
15 66
15 66
29 28 27 26 15 66 32 27 26 15 66 32 27 26 15 66 32 27 26 15
MT41J128M8HX-187E
66 32 27 26 15
MT41J128M8HX-187E
66 32 27 26 15
MT41J128M8HX-187E
MEM_A_ODT<0> ODT G1
OMIT_TABLE
U3220
FBGA OMIT_TABLE
U3230
FBGA OMIT_TABLE
MEM_A_ODT<0> ODT G1
OMIT_TABLE
MEM_A_ODT<0> ODT G1
MEM_A_ODT<0> ODT G1
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66
C3MEM_A_DQS_P<7> D3MEM_A_DQS_N<7> B7MEM_A_DM<7> A7 NC NC A3 NC NC NC NC

15 66
15 66
15 66
MEM_A_CS_L<1>NC H1
66 32 27 26 21 15
66 32 27 26 21 15
66 32 27 26 21 15
66 32 27 26 21 15
66 32 27 26 15 66 32 27 26 15
66 32 27 26 15 15 26 27 66 32 27 26 15 32 66 15 21 26 27 32 66 66 32 27 26 15
NC
66 32 27 26 15 26 27 32 66 66 32 27 26 15 21 26 27 32 66 66 32 27 26 15
66 32 27 26 15 66 32 27 26 15 15 26 27 32 66 15 21 26 27 32 66 26 15 66 32 27 66 32 27 26 15
NC
66 32 27 26 15
NC
66 32 27 26 15
66 32 27 26 15
66 32 27 26 15
66 32 27 26 15
66 32 27 26 15
G3 MEM_A_CAS_L CAS*
MEM_A_WE_L H3 WE*
VSS VSSQ
MEM_A_A<14> 15
66 32 27 26 15 26 27 32 66 66 32 27 26 15
F3 MEM_A_RAS_L RAS*
MEM_A_CAS_L CAS* G3 MEM_A_WE_L H3 WE*
MEM_A_A<14> 15
66 32 27 26 15 26 27 32 66 66 32 27 26 15
F1 MEM_A_ODT<1> F9 MEM_A_CKE<1> H9 MEM_A_ZQ10 27 N7 J7 NC
NC
66 32 27 26 15 26 27 32 66 66 32 27 26 15
F1 MEM_A_ODT<1> 15 66 F9 MEM_A_CKE<1> 15 32 H9 MEM_A_ZQ11 27 N7 J7 NC
26 27 32 21 26 27 66
G3 MEM_A_CAS_L CAS* H3 WE* MEM_A_WE_L

VSS VSSQ
MEM_A_A<14> 15
G3 MEM_A_CAS_L CAS* H3 WE* MEM_A_WE_L

VSS VSSQ
MEM_A_A<14> 15
26 27 32 66
66 32 27 26 15
66 32 27 26 15
66 32 27 26 15
66 32 27 26 15
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
VSS
VSSQ
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
SYNC_MASTER=K16_MLB
PAGE TITLE

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

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=PPLVDDR_S3_MEM_B
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=PPLVDDR_S3_MEM_B
33 29 28 27 26
=PPLVDDR_S3_MEM_B B9 C1 E2 E9
1 2
E1
J8
A2 A9 D7 G2 G8 K1 K9 M1 M9
B9 C1 E2 E9
E1
J8
A2 A9 D7 G2 G8 K1 K9 M1 M9
E1
J8
A2 A9 D7 G2 G8 K1 K9 M1 M9
B9 C1 E2 E9
E1
J8
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
201 4V
201 4V

201 4V 201 4V
U3300
FBGA

201 4V 201 4V
20%
20%
VDD
VDDQ
VREFCA
20%
20%
VDD
VDDQ
0.47UF 20%
1 1 C3310 C3311
20% 20%
4V CERM-X5R-1 201
VDD
VDDQ
0.47UF
1 1 C3320 C3321
1 2
C3322
0.47UF 20%
4V CERM-X5R-1 201
A2 A9 D7 G2 G8 K1 K9 M1 M9
1 1 C3300 C3301
B9 C1 E2 E9
C3302
C3312
20% 4V CERM-X5R-1 201

201 4V 201 4V 20% 20%
C3332
0.47UF 20%
4V CERM-X5R-1 201
VDD
VDDQ
U3310
FBGA
MT41J128M8HX-187E
MEM_RESET_L N2 29 28 27 26 15 R3300 240 2 MEM_B_ZQ0 1 H8 MF 1%1/20W 201 K3 MEM_B_A<0> 66 32 29 28 15 L7 66 32 29 28 15 MEM_B_A<1> L3 66 32 29 28 15 MEM_B_A<2> K2 MEM_B_A<3> 66 32 29 28 15 L8 66 32 29 28 15 MEM_B_A<4> L2 66 32 29 28 15 MEM_B_A<5> M8 66 32 29 28 15 MEM_B_A<6> M2 MEM_B_A<7> 66 32 29 28 15 N8 66 32 29 28 15 MEM_B_A<8> M3 66 32 29 28 15 MEM_B_A<9> H7 66 32 29 28 15 MEM_B_A<10> M7 66 32 29 28 15 MEM_B_A<11> K7 66 32 29 28 15 MEM_B_A<12> N3 66 32 29 28 15 MEM_B_A<13>
66 32 29 28 15 66 32 29 28 15 66 32 29 28 15
66 32 29 28 15
66 32 29 28 15
B3MEM_B_DQ<1> C7MEM_B_DQ<4> C2MEM_B_DQ<2> C8MEM_B_DQ<3> E3MEM_B_DQ<0> E8MEM_B_DQ<5> D2MEM_B_DQ<6> E7MEM_B_DQ<7>
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66
C3MEM_B_DQS_P<0> D3MEM_B_DQS_N<0> B7MEM_B_DM<0> A7 NC A3 NC

15 66
15 66
15 66
MEM_RESET_L RESET* N2 R3310 240 2 MEM_B_ZQ1 ZQ 1 H8 MF 1%1/20W 201 K3 A0 66 32 29 28 15 MEM_B_A<0> L7 A1 66 32 29 28 15 MEM_B_A<1> L3 A2 66 32 29 28 15 MEM_B_A<2> K2 A3 MEM_B_A<3> 66 32 29 28 15 L8 A4 66 32 29 28 15 MEM_B_A<4> L2 A5 66 32 29 28 15 MEM_B_A<5> M8 A6 66 32 29 28 15 MEM_B_A<6> M2 A7 66 32 29 28 15 MEM_B_A<7> N8 A8 66 32 29 28 15 MEM_B_A<8> M3 A9 66 32 29 28 15 MEM_B_A<9> H7 MEM_B_A<10> A10/AP 66 32 29 28 15 M7 A11 66 32 29 28 15 MEM_B_A<11> K7 A12/BC* 66 32 29 28 15 MEM_B_A<12> N3 A13 66 32 29 28 15 MEM_B_A<13>
29 28 27 26 15 66 32 29 28 15 66 32 29 28 15 66 32 29 28 15
B3MEM_B_DQ<14> 15 66 C7MEM_B_DQ<9> 15 66 C2MEM_B_DQ<8> 15 66 C8MEM_B_DQ<12> 15 66 E3MEM_B_DQ<10> 15 66 E8MEM_B_DQ<13> 15 66 D2MEM_B_DQ<11> 15 66 E7MEM_B_DQ<15> 15 66 C3MEM_B_DQS_P<1> D3MEM_B_DQS_N<1> B7MEM_B_DM<1> A7 NC A3 NC
15 66 15 66
15 66
J2 MEM_B_BA<0> BA0 K8 MEM_B_BA<1> BA1 J3 MEM_B_BA<2> BA2 G9 MEM_B_CKE<0> CKE F7 CK MEM_B_CLK_P<0> G7 CK* MEM_B_CLK_N<0> H2 MEM_B_CS_L<0>CS*
MEM_B_CS_L<1>NC H1 MEM_B_RAS_L RAS* F3 MEM_B_CAS_L CAS* G3
MEM_RESET_L RESET* N2 R3320 240 2MEM_B_ZQ2 ZQ 1 H8 MF 1%1/20W 201 K3 A0 66 32 29 28 15 MEM_B_A<0> L7 A1 66 32 29 28 15 MEM_B_A<1> L3 A2 66 32 29 28 15 MEM_B_A<2> K2 A3 66 32 29 28 15 MEM_B_A<3> L8 A4 66 32 29 28 15 MEM_B_A<4> L2 A5 66 32 29 28 15 MEM_B_A<5> M8 A6 MEM_B_A<6> 66 32 29 28 15 M2 A7 66 32 29 28 15 MEM_B_A<7> N8 A8 66 32 29 28 15 MEM_B_A<8> M3 A9 66 32 29 28 15 MEM_B_A<9> H7 A10/AP 66 32 29 28 15 MEM_B_A<10> M7 A11 66 32 29 28 15 MEM_B_A<11> K7 A12/BC* 66 32 29 28 15 MEM_B_A<12> N3 MEM_B_A<13> A13 66 32 29 28 15
29 28 27 26 15 66 32 29 28 15 66 32 29 28 15 66 32 29 28 15
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66

15 66
15 66
15 66
MEM_RESET_L RESET* N2 R3330 240 2 MEM_B_ZQ3 ZQ 1 H8 MF 1%1/20W 201 K3 A0 66 32 29 28 15 MEM_B_A<0> L7 A1 66 32 29 28 15 MEM_B_A<1> L3 A2 66 32 29 28 15 MEM_B_A<2> K2 A3 66 32 29 28 15 MEM_B_A<3> L8 A4 66 32 29 28 15 MEM_B_A<4> L2 A5 66 32 29 28 15 MEM_B_A<5> M8 A6 MEM_B_A<6> 66 32 29 28 15 M2 A7 66 32 29 28 15 MEM_B_A<7> N8 A8 66 32 29 28 15 MEM_B_A<8> M3 A9 66 32 29 28 15 MEM_B_A<9> H7 A10/AP 66 32 29 28 15 MEM_B_A<10> M7 A11 66 32 29 28 15 MEM_B_A<11> K7 A12/BC* 66 32 29 28 15 MEM_B_A<12> N3 MEM_B_A<13> A13 66 32 29 28 15
29 28 27 26 15 66 32 29 28 15 66 32 29 28 15 66 32 29 28 15
MT41J128M8HX-187E
66 32 29 28 15
MT41J128M8HX-187E
66 32 29 28 15
MT41J128M8HX-187E
MEM_B_ODT<0> ODT G1
OMIT_TABLE
U3320
FBGA OMIT_TABLE
U3330
FBGA OMIT_TABLE
MEM_B_ODT<0> ODT G1
OMIT_TABLE
MEM_B_ODT<0> ODT G1
MEM_B_ODT<0> ODT G1
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66

15 66
15 66
15 66
MEM_B_CS_L<1>NC H1 MEM_B_RAS_L RAS* F3
J2 MEM_B_BA<0> BA0 K8 MEM_B_BA<1> BA1 J3 MEM_B_BA<2> BA2 G9 MEM_B_CKE<0> CKE F7 CK MEM_B_CLK_P<0> G7 CK* MEM_B_CLK_N<0>
MEM_B_CS_L<0>CS* H2 MEM_B_CS_L<1>NC H1 MEM_B_RAS_L RAS* F3 MEM_B_CAS_L CAS* G3
MEM_B_CS_L<0>CS* H2 MEM_B_CS_L<1>NC H1 MEM_B_RAS_L RAS* F3 MEM_B_CAS_L CAS* G3
32 29 28 21 15 66 66 32 29 28 15 66 32 29 28 15
66 32 29 28 21 15
66 32 29 28 21 15 66 32 29 28 15
66 32 29 28 21 15
NC
66 32 29 28 15
66 32 29 28 15
66 32 29 28 15
F1 MEM_B_ODT<1> 15 28 F9 MEM_B_CKE<1> 15 21 H9 MEM_B_ZQ0 28 N7 J7 NC MEM_B_A<14> 15
66 32 29 28 15
66 32 29 28 15
29 32 66
29 28 15 66 32
NC
28 29 32 66 66 32 29 28 15
66 32 29 28 15 28 29 32 66 66 32 29 28 15
29 32 66 66 32 29 28 15 28 29 32 66 66 32 29 28 15
NC
66 32 29 28 15 28 29 32 66 66 32 29 28 15
66 32 29 28 15
66 32 29 28 15 29 32 66 28 29 32 66 28 15 66 32 29 66 32 29 28 15
NC
66 32 29 28 15 66 32 29 28 15
G3 MEM_B_CAS_L CAS*
66 32 29 28 15
28 29 32 66 28 15 66 32 29 66 32 29 28 15
F1 MEM_B_ODT<1> 15 28 F9 MEM_B_CKE<1> 32 66 15 21 29 32 H9 MEM_B_ZQ3 28 N7 66 J7 NC MEM_B_A<14> 15 29
29 28 66
28 32
MEM_B_WE_L H3 WE*
66 32 29 28 15
H3 WE* MEM_B_WE_L
66 32 29 28 15
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
VSS
VSSQ VSS VSSQ
H3 WE* MEM_B_WE_L
VSS VSSQ
66 32 29 28 15
H3 WE* MEM_B_WE_L
VSS VSSQ
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
SYNC_MASTER=K16_MLB
PAGE TITLE

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

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=PPLVDDR_S3_MEM_B
33 29 28 27 26
31 29 28 8
=PPLVDDR_S3_MEM_B
33 29 28 27 26
E1
J8
A2 A9 D7 G2 G8 K1 K9 M1 M9
B9 C1 E2 E9
=PPLVDDR_S3_MEM_B B9 C1 E2 E9
1 2
=PPLVDDR_S3_MEM_B
1 2
33 29 28 27 26
E1
J8
A2 A9 D7 G2 G8 K1 K9 M1 M9
E1
J8
A2 A9 D7 G2 G8 K1 K9 M1 M9
E1
J8
A2 A9 D7 G2 G8 K1 K9 M1 M9
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
201 4V
201 4V

201 4V 201 4V
U3400
FBGA
4V CERM-X5R-1 201

201 4V 201 4V
20%
20%
VDD
VDDQ
VREFCA
20%
20%
VDD
VDDQ
0.47UF 20%
1 C3410
20%
1 C3411
20%
4V CERM-X5R-1 201
VDD
VDDQ
0.47UF 20%
1 1 C3420 C3421
C3422
0.47UF
20% 4V CERM-X5R-1 201
B9 C1 E2 E9
1 1 C3400 C3401
B9 C1 E2 E9
C3402
C3412

201 4V 201 4V 20% 20%
C3432
0.47UF
20% 4V CERM-X5R-1 201
VDD
VDDQ
U3410
FBGA
MT41J128M8HX-187E
MEM_RESET_L RESET* N2 29 28 27 26 15 R3400 240 2 MEM_B_ZQ8 ZQ 1 H8 MF 1%1/20W 201 K3 A0 66 32 29 28 15 MEM_B_A<0> L7 A1 66 32 29 28 15 MEM_B_A<1> L3 A2 66 32 29 28 15 MEM_B_A<2> K2 A3 66 32 29 28 15 MEM_B_A<3> L8 A4 MEM_B_A<4> 66 32 29 28 15 L2 A5 66 32 29 28 15 MEM_B_A<5> M8 A6 66 32 29 28 15 MEM_B_A<6> M2 A7 66 32 29 28 15 MEM_B_A<7> N8 A8 66 32 29 28 15 MEM_B_A<8> M3 A9 66 32 29 28 15 MEM_B_A<9> H7 A10/AP 66 32 29 28 15 MEM_B_A<10> M7 MEM_B_A<11> A11 66 32 29 28 15 K7 A12/BC* 66 32 29 28 15 MEM_B_A<12> N3 A13 66 32 29 28 15 MEM_B_A<13>
66 32 29 28 15 66 32 29 28 15 66 32 29 28 15
66 32 29 28 15
66 32 29 28 15
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66

15 66
15 66
15 66
MEM_RESET_L N2 R3410 240 2MEM_B_ZQ9 1 H8 MF 1%1/20W 201 K3 MEM_B_A<0> 66 32 29 28 15 L7 66 32 29 28 15 MEM_B_A<1> L3 66 32 29 28 15 MEM_B_A<2> K2 66 32 29 28 15 MEM_B_A<3> L8 66 32 29 28 15 MEM_B_A<4> L2 66 32 29 28 15 MEM_B_A<5> M8 66 32 29 28 15 MEM_B_A<6> M2 MEM_B_A<7> 66 32 29 28 15 N8 66 32 29 28 15 MEM_B_A<8> M3 66 32 29 28 15 MEM_B_A<9> H7 66 32 29 28 15 MEM_B_A<10> M7 66 32 29 28 15 MEM_B_A<11> K7 66 32 29 28 15 MEM_B_A<12> N3 66 32 29 28 15 MEM_B_A<13>
29 28 27 26 15 66 32 29 28 15 66 32 29 28 15 66 32 29 28 15
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66

15 66
15 66
15 66
MEM_B_CS_L<0>CS* H2 MEM_B_CS_L<1>NC H1 MEM_B_RAS_L RAS* F3
29 28 27 26 15 66 32 29 28 15 66 32 29 28 15 66 32 29 28 15
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66

15 66
15 66
15 66
29 28 27 26 15 66 32 29 28 15 66 32 29 28 15 66 32 29 28 15
MT41J128M8HX-187E
66 32 29 28 15
MT41J128M8HX-187E
66 32 29 28 15
MT41J128M8HX-187E
MEM_B_ODT<0> ODT G1
OMIT_TABLE
U3420
FBGA OMIT_TABLE
U3430
FBGA OMIT_TABLE
MEM_B_ODT<0> ODT G1
OMIT_TABLE
MEM_B_ODT<0> ODT G1
MEM_B_ODT<0> ODT G1
15 66 15 66 15 66 15 66 15 66 15 66 15 66 15 66

15 66
15 66
15 66
MEM_B_CS_L<1>NC H1 MEM_B_RAS_L RAS* F3 MEM_B_CAS_L CAS* G3 MEM_B_WE_L H3 WE*
66 32 29 28 21 15
66 32 29 28 21 15 66 32 29 28 15 66 32 29 28 15
66 32 29 28 21 15 66 32 29 28 15
66 32 29 28 21 15
NC
66 32 29 28 15
66 32 29 28 15
66 32 29 28 15
F1 MEM_B_ODT<1> F9 MEM_B_CKE<1> H9 MEM_B_ZQ8 29 N7 J7 NC
66 32 29 28 15
66 32 29 28 15
15 28 29 32 66
29 28 15 66 32
NC
15 21 28 29 32 66 66 32 29 28 15
66 32 29 28 15
66 32 29 28 15
G3 MEM_B_CAS_L CAS*
MEM_B_WE_L H3 WE*
VSS VSSQ
MEM_B_A<14> 15
66 32 29 28 15 28 29 32 66 66 32 29 28 15
F1 MEM_B_ODT<1> 15 F9 MEM_B_CKE<1> 15 H9 MEM_B_ZQ9 29 N7 J7 NC
28 29 32 66 66 32 29 28 15 21 28 29 32 66 66 32 29 28 15
NC
66 32 29 28 15
MEM_B_A<14> 15
66 32 29 28 15 28 29 32 66 66 32 29 28 15
F1 MEM_B_ODT<1> F9 MEM_B_CKE<1> H9 MEM_B_ZQ10 29 N7 J7 NC
66 32 29 28 15 15 28 29 32 66 15 21 28 66 32 29 28 15 29 32 66 66 32 29 28 15
NC
66 32 29 28 15 28 29 32 66 66 32 29 28 15
F1 MEM_B_ODT<1> 15 66 F9 MEM_B_CKE<1> 15 32 H9 MEM_B_ZQ11 29 N7 J7 NC
28 29 32 21 28 29 66
G3 MEM_B_CAS_L CAS* H3 WE* MEM_B_WE_L

VSS VSSQ
MEM_B_A<14> 15
G3 MEM_B_CAS_L CAS* H3 WE* MEM_B_WE_L

VSS VSSQ
MEM_B_A<14> 15
28 29 32 66
66 32 29 28 15
66 32 29 28 15
66 32 29 28 15
66 32 29 28 15
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
VSS
VSSQ
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9
B2 B8 C9 D1 D9
SYNC_MASTER=K16_MLB
PAGE TITLE

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

34 OF 110
SHEET
29 OF 73
30 27 26 8
=PPLVDDR_S3_MEM_A
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
30 27 26 8
=PPLVDDR_S3_MEM_A
1
D
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
C3500 2.2UF C3501 2.2UF
20% 2 6.3V CERM 402-LF 1
C3510 2.2UF C3511 2.2UF C3512 2.2UF
OMIT_TABLE
1
OMIT_TABLE
20% 2 6.3V CERM 402-LF 1
C3520 2.2UF
OMIT_TABLE
20% 2 6.3V CERM 402-LF 1
C3530 2.2UF C3531 2.2UF
OMIT_TABLE
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
C3540 2.2UF C3541 2.2UF C3542 2.2UF
C3550 2.2UF
OMIT_TABLE
OMIT_TABLE
20% 6.3V 2 CERM 402-LF
OMIT_TABLE
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
C3521 2.2UF
OMIT_TABLE
20% 6.3V 2 CERM 402-LF
OMIT_TABLE
20% 6.3V 2 CERM 402-LF
20% 6.3V 2 CERM 402-LF
C3551 2.2UF
OMIT_TABLE
1 1
OMIT_TABLE
20% 2 6.3V CERM 402-LF
2 CAPS ALONG PACKAGE EDGE
20% 2 6.3V CERM 402-LF
C
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
C
C3504 2.2UF C3505 2.2UF
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
C3514 2.2UF C3515 2.2UF C3516 2.2UF
20% 2 6.3V CERM 402-LF 1
C3524 2.2UF C3525 2.2UF
OMIT_TABLE
1
OMIT_TABLE
20% 2 6.3V CERM 402-LF 1
C3534 2.2UF C3535 2.2UF
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
C3544 2.2UF C3545 2.2UF C3546 2.2UF
C3554 2.2UF
OMIT_TABLE
OMIT_TABLE
20% 2 6.3V CERM 402-LF
OMIT_TABLE
20% 2 6.3V CERM 402-LF
OMIT_TABLE
OMIT_TABLE
20% 2 6.3V CERM 402-LF
OMIT_TABLE
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
C3555 2.2UF
OMIT_TABLE
1 1 20% 2 6.3V CERM 402-LF
OMIT_TABLE
20% 2 6.3V CERM 402-LF
COLUMN OF THREE CAPS BETWEEN PACKAGES
SYNC_MASTER=K16_MLB
PAGE TITLE
DDR BYPASSING 1
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

35 OF 110
SHEET
30 OF 73
31 29 28 8
=PPLVDDR_S3_MEM_B
OMIT_TABLE OMIT_TABLE OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
31 29 28 8
=PPLVDDR_S3_MEM_B
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
D
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
OMIT_TABLE
1
C3600 2.2UF
20% 6.3V CERM 402-LF 1
20% 2 6.3V CERM 402-LF 1
C3610 2.2UF
OMIT_TABLE
C3620 2.2UF
OMIT_TABLE
C3630 2.2UF
OMIT_TABLE
C3640 2.2UF
OMIT_TABLE
20% 2 6.3V CERM 402-LF 1
C3650 2.2UF
OMIT_TABLE
OMIT_TABLE
20% 6.3V 2 CERM 402-LF
C3601 2.2UF
20% 2 6.3V CERM 402-LF
C3611 2.2UF C3612 2.2UF
20% 6.3V 2 CERM 402-LF
C3621 2.2UF
20% 6.3V 2 CERM 402-LF
C3631 2.2UF
20% 2 6.3V CERM 402-LF
C3641 2.2UF
OMIT_TABLE
20% 6.3V 2 CERM 402-LF
C3651 2.2UF
OMIT_TABLE
1 1
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
C3642 2.2UF
C
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
C
C3604 2.2UF C3605 2.2UF
1 20% 2 6.3V CERM 402-LF 1
C3614 2.2UF C3615 2.2UF
OMIT_TABLE
1
OMIT_TABLE
20% 2 6.3V CERM 402-LF 1
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF 1
C3624 2.2UF C3625 2.2UF
C3634 2.2UF
OMIT_TABLE
C3644 2.2UF
OMIT_TABLE
C3654 2.2UF
OMIT_TABLE
OMIT_TABLE
20% 2 6.3V CERM 402-LF
OMIT_TABLE
20% 2 6.3V CERM 402-LF
OMIT_TABLE
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
C3635 2.2UF
20% 2 6.3V CERM 402-LF
C3645 2.2UF C3646 2.2UF
20% 2 6.3V CERM 402-LF
C3655 2.2UF
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF
OMIT_TABLE
1 20% 2 6.3V CERM 402-LF
C3616 2.2UF
SYNC_MASTER=K16_MLB
PAGE TITLE
DDR BYPASSING 2
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

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SHEET
31 OF 73
7
MEM CLOCK TERMINATION
JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE
8
Place RC end termination after last DRAM Place Source Cterm at neckdown at first DRAM
1 2
66 27 26 15
=PPDDRVTT_S0_MEM_A
8 7 5 6 8 6 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 1
MEM_A_CLK_N<0> 1 C3704 3.3PF
R3700 30
1 2 5% 1/20W MF 201
C3700
0.1UF 10%
X5R 201 6.3V
66 27 26 21 15 66 27 26 15 66 27 26 15 66 27 26 15 66 27 26 15 66 27 26 15
IN IN IN IN IN IN
MEM_A_CLK_TERM_R
VOLTAGE=0V
D
66 27 26 15
5% 25V 2 CERM 201 MEM_A_CLK_P<0>
R3701 30
1 2 5% 1/20W MF 201
MEM_A_CKE<1> MEM_A_WE_L MEM_A_A<6> MEM_A_BA<2> MEM_A_ODT<1> MEM_A_ODT<0> MEM_A_A<10> MEM_A_A<13> MEM_A_A<2> MEM_A_A<3> MEM_A_A<11> MEM_A_A<5> MEM_A_CKE<0> MEM_A_A<1> MEM_A_A<12> MEM_A_BA<1> MEM_A_A<8> MEM_A_A<0> MEM_A_BA<0> MEM_A_A<14>
RP3702 RP3702 RP3706 RP3702 RP3701 RP3701
36 1 36 2 36 4 36 3 36 1 36 3
20% 2 4V CERM-X5R-1 201
C3710 0.47UF
66 27 26 15 66 27 26 15 66 27 26 15 66 27 26 15
IN IN IN IN IN IN IN IN IN IN IN IN IN IN
66 29 28 15
MEM_B_CLK_N<0> 1 C3706 3.3PF
2MEM_B_CLK_TERM_R
VOLTAGE=0V
R3704 30
5% 1/20W MF 201
C3702
0.1UF 10%
X5R 201 6.3V
66 27 26 15 66 27 26 15 66 27 26 21 15 66 27 26 15 66 27 26 15 66 27 26 15 66 27 26 15 66 27 26 15 66 27 26 15 66 27 26 15
66 29 28 15
5% 25V 2 CERM 201 MEM_B_CLK_P<0>
R3705 30
1 2 5% 1/20W MF 201
RP3702 36 4 RP3707 36 3 RP3704 36 1 R3792 36 1 RP3707 36 2 R3793 36 1 RP3703 36 2 RP3704 36 3 RP3703 36 4 RP3704 36 2 RP3706 36 3 RP3703 36 3 RP3703 36 1 RP3704 36 4 R3790 R3791 RP3706 RP3706 RP3701 RP3701 RP3707
36 1 36 1 36 2 36 1 36 4 36 2 36 1
5 5% 1/32W 4X0201 6 5% 1/32W4X0201 8 1/32W 4X0201 2 5% 1/20W 201 5% 7 5% 1/32W 4X0201 2 1/20W 201 7 5% 5% 1/32W 4X0201 6 5% 1/32W 4X0201 5 5% 1/32W4X0201 7 5% 1/32W 4X0201 6 5% 1/32W 4X0201 6 5% 1/32W 4X0201 8 5% 1/32W 4X0201 5 5% 1/32W 4X0201
20% 20% 2 4V 2 4V CERM-X5R-1 CERM-X5R-1 201 201 1
C37121 C3713 0.47UF 0.47UF C37141 C3715 0.47UF 0.47UF C37161 C3717 0.47UF 0.47UF C3718 0.47UF C3720 0.47UF
20% 2 4V 2 CERM-X5R-1 201
20% 4V CERM-X5R-1 201
20% 2 4V 2 CERM-X5R-1 201
20% 4V CERM-X5R-1 201
66 27 26 15
IN IN
66 27 26 15 66 27 26 15 66 27 26 15 66 27 26 15
IN IN IN IN IN
66 27 26 15
MEM_A_CS_L<0> MEM_A_CS_L<1> MEM_A_A<4> MEM_A_A<7> MEM_A_CAS_L MEM_A_RAS_L MEM_A_A<9>
2 2 7 8 5 7 8
1 1/20W 201 5% 1/20W 201 5% 5% 1/32W4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201
20% 2 4V CERM-X5R-1 201
20% 2 4V CERM-X5R-1 201
=PPDDRVTT_S0_MEM_B
8 66 29 28 15 66 29 28 15 66 29 28 15 66 29 28 15 66 29 28 15 66 29 28 15
IN IN IN IN IN IN
MEM_B_ODT<0> MEM_B_CAS_L MEM_B_A<8> MEM_B_BA<2> MEM_B_RAS_L MEM_B_ODT<1> MEM_B_BA<0> MEM_B_A<7> MEM_B_A<0> MEM_B_A<10> MEM_B_A<5> MEM_B_CKE<0> MEM_B_A<6> MEM_B_A<12> MEM_B_CS_L<1> MEM_B_A<2> MEM_B_CS_L<0> MEM_B_A<14> MEM_B_A<4> MEM_B_BA<1> MEM_B_A<13> MEM_B_A<3> MEM_B_A<1> MEM_B_WE_L MEM_B_CKE<1> MEM_B_A<9> MEM_B_A<11>
RP3715 RP3715 RP3711 RP3709 RP3715 RP3715 RP3709 RP3710 RP3708 RP3709 RP3711 RP3709 RP3711 RP3708 RP3713 RP3708 RP3713 RP3710 RP3710 RP3708 RP3710 RP3714 RP3714 RP3713 RP3713 RP3714 RP3714
36 3 36 4 36 1 36 1 36 2 36 1 36 3 36 3 36 1 36 2 36 2 36 4 36 3 36 2 36 1 36 3 36 4 36 2 36 4 36 4 36 1 36 1 36 2 36 3 36 2 36 3 36 4
6 5 8 8 7 8 6 6 8 7 7 5 6 7 8 6 5 7 5 5 8
5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W4X0201 5% 1/32W4X0201 5% 1/32W 4X0201 5% 1/32W4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201
20% 2 4V CERM-X5R-1 201
C3722 0.47UF C3724 0.47UF
66 29 28 15 66 29 28 15 66 29 28 15 66 29 28 15 66 29 28 15 66 29 28 21 15
IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN
20% 2 4V CERM-X5R-1 201
66 29 28 15 66 29 28 15 66 29 28 15 66 29 28 15 66 29 28 15 66 29 28 15 66 29 28 15 66 29 28 15 66 29 28 15
20% 20% 2 4V 2 4V CERM-X5R-1 CERM-X5R-1 201 201
C37261 C3727 0.47UF 0.47UF C37281 C3729 0.47UF 0.47UF C3730 0.47UF
20% 20% 2 4V 2 4V CERM-X5R-1 CERM-X5R-1 201 201 1
66 29 28 15 66 29 28 15 66 29 28 15 66 29 28 21 15 66 29 28 15 66 29 28 15
IN IN IN IN IN IN
8 7 6 7 6 5
5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201 5% 1/32W 4X0201
20% 2 4V CERM-X5R-1 201 1
20% 20% 2 4V 2 4V CERM-X5R-1 CERM-X5R-1 201 201
C37321 C3733 0.47UF 0.47UF
SYNC_MASTER=K16_MLB
PAGE TITLE
Memory Active Termination

DRAWING NUMBER SIZE
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051-8379
REVISION
4.4.0
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SHEET
32 OF 73
8
8
=PP3V3_S3_VREFMRGN OMIT
NOTE: Must not enable more than two SO-DIMM margining buffers at once or VRef source may be overloaded.
R3900
1
VREFMRGN:YES PP3V3_S3_VREFMRGN_DAC
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
52 8
SHORT 2
NONE NONE NONE 402
=PPVTT_S3_DDR_BUF 10mA max load
R3921
1
200
PLACE_NEAR=U3230.E1.1:2.54MM
VREFMRGN:YES
VREFMRGN:YES
1
C3900 1
2.2UF
20% 6.3V 2 CERM 402-LF
C3901
0.1UF CRITICAL VREFMRGN:YES
8 VDD
VREFMRGN:YES
D
41
10% 6.3V 2 X5R 201
C3920 1
0.1UF
10% 6.3V 2 X5R 201 A2
CRITICAL
B1
V+
1% 1/20W MF 201
MAX4253
UCSP A1 A4
U3920
VREFMRGN:YES
26 27 28 29
U3900
VREFMRGN_DQ_DRAM
VOUTB 2 VOUTC 4 VOUTD 5
R3922
1
IN BI
=I2C_VREFDACS_SCL =I2C_VREFDACS_SDA
6 SCL 7 SDA 9 A0
1 MSOP VOUTA
A3
VREFMRGN_DQ_BUF VREFMRGN:YES
133
2 PLACE_NEAR=R3921.2:1MM
V-
41
DAC5574
B4
1% 1/20W MF 201
VREFMRGN_CA_DRAM VREFMRGN_MEMVREG_FBVREF NOTE: MEMVREG and FRAMEBUF share a DAC output, cannot enable both at the same time!
1
Addr=0x98(WR)/0x99(RD)
10 A1
VREFMRGN:YES
R3923
VREFMRGN:YES
1
GND 3
200
2 PLACE_NEAR=U3230.J8:2.54MM
R3920
100K
5% 1/20W MF 201
C2
B1
V+
MAX4253
UCSP C1 C4
U3920
CRITICAL VREFMRGN_CA_BUF VREFMRGN:YES
1% 1/20W MF 201
VREFMRGN:YES
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.15 MM VOLTAGE=0.75V
26 27 28 29
OMIT
R3924
1
133
2 PLACE_NEAR=R3923.2:1MM
R3910
SHORT 1 2
NONE NONE NONE 402
PP3V3_S3_VREFMRGN_CTRL
C3
V-
B4 16
1% 1/20W MF 201
VREFMRGN:YES
C3910 1
0.1UF
10% 6.3V 2 X5R 201 3 A0 4 A1 5 A2
CRITICAL VREFMRGN:YES VREFMRGN:YES

1
VCC
U3910
PCA9557
QFN (OD) P0 6 P1 7 P2 9 P3 10 P4 11 P5 12 P6 13 P7 14
R3925
100K
NC NC NC
VREFMRGN_DQ_DRAM_EN VREFMRGN_CA_DRAM_EN VREFMRGN_MEMVREG_EN VREFMRGN_CPUGTLREF_EN
5% 1/20W MF 2 201
Addr=0x30(WR)/0x31(RD)
41 41
IN BI
=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA
1 SCL 2 SDA
THRM
NC(RSVD for FBVREF)
RESET* 15 GND
8
PAD 17
25
IN
PCA9557D_RESET_L
RST* on platform reset so that system watchdog will disable margining. NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.
Required zero ohm resistors when no VREF margining circuit stuffed

PART NUMBER
117S0002
QTY
2
DESCRIPTION
RES,MF,1/20W,0.0 OHM,5,0201,SMD
REFERENCE DES
R3921,R3923
CRITICAL
BOM OPTION
VREFMRGN:NO
VREFMRGN:YES
C3940 1
0.1UF
10% 6.3V 2 X5R 201 C2
CRITICAL
B1
V+
MAX4253
UCSP C1 C4
U3940
VREFMRGN:YES
R3942
1
C3
VREFMRGN_MEMVREG_BUF VREFMRGN:YES
22.6K 2
1% 1/20W MF 201
DDRREG_FB
PLACE_NEAR=R7320.2:1mm
OUT
52
V-
B4
Page Notes
Power aliases required by this page: - =PP3V3_S3_VREFMRGN - =PPVTT_S3_DDR_BUF Signal aliases required by this page: - =I2C_VREFDACS_SCL - =I2C_VREFDACS_SDA - =I2C_PCA9557D_SCL - =I2C_PCA9557D_SDA BOM options provided by this page: VREFMRGN:YES - Stuffs VREF Margining Circuitry. VREFMRGN:NO - Bypasses VREF Margining Circuitry.
VREFMRGN:YES
1
R3940
100K
A2 B1
V+
CRITICAL MAX4253
UCSP A1 A4
V-
5% 1/20W MF 2 201
U3940
VREFMRGN:YES
R3944
1
A3
VREFMRGN_CPUGTLREF_BUF VREFMRGN:YES
267
CPU_GTLREF
PLACE_NEAR=R1005.2:1mm
OUT
10 65
B4
1% 1/20W MF 201
VREFMRGN:YES
1
R3945
100K
5% 1/20W MF 2 201
A
DAC Channel: PCA9557D Pin: Nominal value Margined target: DAC range: VRef current: DAC step size:
MEM VREF DQ A 1
MEM VREF CA C 3 0.75V (DAC: 0x3A) 0.300V - 1.200V (+/- 450mV) 0.000V - 1.501V (0x00 - 0x74) +3.4mA - -3.4mA (- = sourced) 7.69mV / step @ output
MEM VREG D 5 1.5V (DAC: 0x3A) 1.998V - 1.002V (+/- 498mV) 0.000V - 1.501V (0x00 - 0x74) +33uA - -33uA (- = sourced) 8.59mV / step @ output
CPU GTLREF (FSB) D 7 0.7V (DAC: 0x8B) 0.200V - 1.050V (+/- 500mV) 0.000V - 1.191V (0x00 - 0x5C) +750uA - -528uA (- = sourced) 9.24mV / step @ output
SYNC_MASTER=K16_MLB
PAGE TITLE
FSB/DDR3 Vref Margining

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051-8379
REVISION
4.4.0
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3
3V S3 WLAN FET
MOSFET CHANNEL RDS(ON) LOADING TPCP8102 P-TYPE 20-30 MOHM @2.5V 0.750 A (EDP)
D
CRITICAL
MIN_LINE_WIDTH=1 mm VOLTAGE=3.3V
39 7
D
CRITICAL TPCP8102
5 6 7 8 1 2 3
AIRPORT
J4001
F-RT-SM1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
MIN_NECK_WIDTH=0.25 mm
23V1K-SM 1% MIN_LINE_WIDTH=1 mm 0.25W MIN_NECK_WIDTH=0.25 mm MF-LF 805 VOLTAGE=3.3V 1 PP3V3_WLAN_F 2PP3V3_WLAN_R 3 4

D S
R4052 0.020
Q4050
=PP3V3_S3_WLAN
1 5% 1/20W MF 2201
C4021 1 0.1UF
CRITICAL 10% 6.3V 2 X5R 201
20% 2 10V X5R 805
C4020 10UF
C4050 0.1UF
1 2 10% 16V X5R 402
0.033UF 10%
C4051 1
16V 2 X5R 402
R4051 10K
PM_WLAN_EN_L IN
57
4G
SSD-K99 WIFI_EVENT_L OUT

67 7 7 38 39
1 P3V3WLAN_SS
R4050 100K
2 5% 1/20W MF 201
PLACEMENT_NOTE=Place close to Q4050. PLACEMENT_NOTE=Place close to Q4050.
PCIE_AP_R2D_N
1 2 0.1UF 10% 6.3V 201 X5R
PCIE_AP_R2D_C_N IN
PLACEMENT_NOTE=Place close to J4001.
16 67
ISNS_AIRPORT_P OUT ISNS_AIRPORT_N OUT
42 71 42 71
C4030
PLACEMENT_NOTE=Place close to J4001.
67 7
PCIE_AP_R2D_P
C4031 1 2
0.1UF10%
6.3VX5R 201
PCIE_AP_R2D_C_P IN
16 67
PCIE_CLK100M_AP_N IN PCIE_CLK100M_AP_P IN
7 16 67
7 16 67
PCIE_AP_D2R_P OUT PCIE_AP_D2R_N OUT PCIE_WAKE_L OUT
7 16 67 7 16 67
7 16
514S0335
BLUETOOTH
B
1
USB_BT_N BI USB_BT_P BI
7 18 68 7 18 68
=PP3V3_S3_BT
10% 2 6.3V X5R 201
7 8
C4032 0.1UF
=PP3V3_S3_WLAN
DLY = 60 MS +/- 20%
8 34
PLACE_NEAR=J4001.27:1.5mm
C4053 1 0.1UF
VDD
CRITICAL
10% 6.3V 2 X5R 201
R40531R40541 100K 232K

5% 1/20W MF 2012 1% 1/20W MF 2012
7
SLG4AP016V
TDFN 2
SENSE + 0.7V DLY MR* EN OUT
(OD)
U4002
AP_RESET_L IN AP_PWR_EN IN
3 6 8
25
19 57
P3V3WLAN_VMON 4 AP_RESET_CONN_LRESET*
7
AP_CLKREQ_L OUT
16
AP_CLKREQ_Q_L
IN THRM PAD GND
R4055 100K
SYNC_MASTER=K16_MLB
PAGE TITLE
1% 1/20W MF 2012
X21 WIRELESS CONNECTOR

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
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40 OF 110
SHEET
34 OF 73
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501
20% 10V 2 CERM 402
C4501 0.1UF
PP3V3_S0_HDD_R
R4599 0.003
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=5V 2 4 1% 1W MF 0612 1 3
CRITICAL
SATA SSD
C
CRITICAL SSD-K99
F-RT-SM1 1 2 3 4 5 6 7 8 9 10 11 12 13 NC 14 NC 15 16 17 18 19 20 21
=PP3V3_S0_HDD ISNS_HDD_POUT ISNS_HDD_N OUT
C
42 71 42 71
J4501
TP_SSD_RSRVD
67 7
SATA_HDD_D2R_C_P
C4516 1
0.01UF
67 7
SATA_HDD_D2R_C_N
PLACE_NEAR=J4501.3:1.5MM C4515 2 1
10V 0.01UF 10% X5R 201 PLACE_NEAR=J4501.4:1.5MM 10% 10V X5R 201
SATA_HDD_D2R_P OUT SATA_HDD_D2R_N OUT
18 67
18 67
PLACE_NEAR=J4501.7:1.5MM
67 7
SATA_HDD_R2D_N SATA_HDD_R2D_P
R4510 0 2
5% 1/20W MF
201
C4511 1
0.01UF
2 SATA_HDD_R2D_C_N 18 IN 10% 10V X5R 201 2 SATA_HDD_R2D_C_P IN 10% 10V X5R 201
67
67 7
C4510 1
0.01UF SMC_HDD_OOB_TEMP
7 38
18 67
SMC_HDD_OOB_TEMP_CONN
SMC_HDD_TEMP_CTL_CONN
R4511 0 1 2
5%
1/20W MF 201
SMC_HDD_TEMP_CTL
B
7 38
SYNC_MASTER=K16_MLB
PAGE TITLE
SATA CONNECTOR
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

45 OF 110
SHEET
35 OF 73
Port Power Switch

CRITICAL
8
CRITICAL FERR-220-OHM-2.5A 1 2 7 PP5V_S3_RTUSB_A_F PP5V_S3_RTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V 0603
=PP5V_S3_RTUSB
OUT IN
U4690
TPS2052B 2 IN 7 OUT1 MSOP 8 OC1* 3 EN1 OUT2 6 5 OC2* 4 EN2 1
L4605
Right USB Port

CRITICAL
18 57 37 7
USB_EXTA_OC_L =USB_PWR_EN CRITICAL OMIT_TABLE
C4605 1
0.01uF
20% 16V CERM 2 402
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V PLACE_NEAR=J4600.1:3 mm
OMIT_TABLE
1
CRITICAL 90-OHM-100MA
DLP11S SYM_VER-1
J4600
USB-RIGHT-K99
F-RT-TH 5 1 VBUS 2
DD+ GND
C4696 1
100UF
20% 6.3V POLY-TANT CASE-B2-SM
C4690 1
10UF
20% 6.3V 2 X5R 603
C4691
0.1UF
GND TPAD
C4695
10UF
71 68
L4600
20% 2 10V CERM 402
20% 2 6.3V X5R 603
USB_EXTA_MUXED_N USB_EXTA_MUXED_P
PLACE_NEAR=D4600.2:2 mm 3 71 USB_LT1_N
71 68
71
USB_LT1_P
4 3 5 2 IO NC IO NC VBUS 6 GND 1
3 4
PLACE_NEAR=D4600.3:2 mm
USB/SMC Debug Mux

8
514-0740
=PP3V42_G3H_SMCUSBMUX SMC_DEBUG:YES
D4600
RCLAMP0502N
SLP1210N6 1
D4600.4 PLACE_NEAR=J4600.3:2 mm D4600.5 PLACE_NEAR=J4600.2:2 mm
C4650 1
0.1UF
10% 6.3V 2 X5R 201 5 M+ 4 M7 D+ 6 D8 OE* 9
R4650
10K
CRITICAL
CRITICAL SMC_DEBUG:YES
Y+ 1
VCC
Y- 2
5% 1/20W MF 2 201
40 39 38 7 40 39 38 7
IN OUT
SMC_RX_L SMC_TX_L USB_EXTA_P USB_EXTA_N
U4650
TQFN
(USB_EXTA_MUXED_P) (USB_EXTA_MUXED_N)
PI3USB102ZLE
68 18 68 18
BI BI
SEL 10 GND 3 SIGNAL_MODEL=USB_MUX
USB_DEBUGPRT_EN_L SEL=0 Choose SMC SEL=1 Choose USB
IN
38
SMC_DEBUG:NO
R4651
1
5% 1/20W MF 201
SMC_DEBUG:NO
R4652
1
5% 1/20W MF 201
SYNC_MASTER=K16_MLB
PAGE TITLE
External USB Connectors

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

46 OF 110
SHEET
36 OF 73
LIO CONNECTOR
AXK736327G
F-ST-SM 37 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 38 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
J4700
68 19 7 68 19 7
HDA_SYNC HDA_SDIN0 HDA_BIT_CLK HDA_SDOUT =I2C_MIKEY_SCL =I2C_MIKEY_SDA =I2C_LIO_SCL =I2C_LIO_SDA AUD_I2C_INT_L AUD_IP_PERIPHERAL_DET AUD_IPHS_SWITCH_EN AUD_GPIO_3 HDA_RST_L
USB_EXTD_P USB_EXTD_N USB_CAMERA_P USB_CAMERA_N SPKRAMP_INR_P SPKRAMP_INR_N
7 18 68 7 18 68
C
=PP3V3_S0_AUDIO
C4700 1
0.1UF
10% 6.3V X5R 201
68 19 7 68 19 7
7 18 68 7 18 68
7 8
41 7 41 7 41 7 41 7 19 7 17 7 19 7 48 7 68 19 7
7 48 71 7 48 71
USB_EXTD_OC_L 7 18 =USB_PWR_EN 7 36 57 SMC_BC_ACOK 7 9 38 39 SYS_ONEWIRE 7 38 =PP1V8R1V5_S0_AUDIO

C4720 1
0.1UF
10% 6.3V X5R 201
=PP3V42_G3H_ONEWIRE
C4710 1
0.1UF
10% 6.3V X5R 201
7 8
7 8
516S0862
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
LIO CONNECTORS
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

47 OF 110
SHEET
37 OF 73
NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.
39 39 8
PP3V3_S5_AVREF_SMC =PP3V3_S5_SMC OMIT_TABLE
D
U4900
B12 A13 A12 B13 D11 C13 C12 D10 D13 E11 D12 F11 E13 E12 F13 E10 A9 D9 C8 B7 A8 D8 D7 D6 D4 A5 B4 A1 C2 B2 C1 C3 G2 F3 E4 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52
D
1
C4902 1
20% 6.3V X5R-CERM-1 2 603 P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P84 P85 P86 P90 P91 P92 P93 P94 P95 P96 P97 L13 K12 K11 J12 K13 J10 J11 H12 N10 M11 L10 N11 N12 M13 N13 L12 A7 B6 C7 D5 A6 B5 C6 J4 G3 H2 G1 H4 G4 F4 F1
22UF
C4903
0.1UF
C4904
0.1UF
C4905
0.1UF
C4906
0.1UF
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
(EXCARD_PWR_EN)
39 57 49 25 57
39
OUT IN IN
SMC_P10 SMC_RSTGATE_L ALL_SYS_PWRGD RSMRST_PWRGD PM_RSMRST_L IMVP_VR_ON PM_PWRBTN_L

NC
H8S2117
LGA-HF (1 OF 3)
SMC_PM_G2_EN
NC NC NC NC
OUT
7 57
BYPASS=U4900.E1:D2:5 mm
R4999 PLACE_NEAR=C4920.1:2
1
mm
SMC_VCL
M12 B1 M1 H10 L11
4.7
OMIT_TABLE
PP3V3_S5_SMC_AVCC
19 53 19
OUT OUT OUT
C4920 1
0.1UF
E1
SMC_ADAPTER_EN SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L SMC_CPU_ISENSE SMC_CPU_VSENSE SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_NB_MISC_ISENSE SMC_WAKE_SCI_L
OUT
19 39 57
5% 1/20W MF 201
C4907 1
20% 4V CERM-X5R-1 2 201
0.47UF
IN IN IN IN IN IN IN IN IN IN OUT
39 39
39
SMC_P20
NC NC NC NC NC
43 42 39 39 43 42 43
20% 10V CERM 2 402 BYPASS=U4900.M12:L9:5 mm
AVCC
VCC
VCL AVREF NC
H8S2117
LGA-HF (3 OF 3)
U4900
R49091
E5
NC
5% 1/20W MF 201 2
10K
R4901
10K
5% 1/20W MF 2 201
39
SMC_P24 SMC_BMON_MUX_SEL
OMIT_TABLE
50 40 39 7
IN
39
SMC_RESET_L SMC_XTAL SMC_EXTAL
D3 A3 A2
RES* XTAL EXTAL
MD1 MD2
D1 H1
SMC_MD1 SMC_KBC_MDE
IN
7 40
43
39 39 19
NMI
E3
SMC_NMI
IN
7 40
68 40 19 7 68 40 19 7 68 40 19 7
BI BI BI BI IN IN IN BI OUT IN BI OUT
68 40 19 7 68 40 19 7 25 68 25 40 19 7
35 7 35 7 41 39
SMC_HDD_TEMP_CTL SMC_HDD_OOB_TEMP SMB_MGMT_DATA SMS_ONOFF_L
(OC)
NC NC
39 39
OUT OUT OUT IN BI
SMC_GFX_THROTTLE_L SMC_SYS_KBDLED SMC_TX_L SMC_RX_L SMB_0_S0_CLK
SMC_ONOFF_L SMC_BC_ACOK SMC_PME_S4_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L PM_CLK32K_SUSCLK (OC) SMB_0_S0_DATA
IN IN IN IN IN IN IN BI
7 39 46 7 9 37 39 39 46 7 19 39 57 7 19 57 19 25 68 41
D2 L3 F10 B11 C5
LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L SMC_LRESET_L LPC_CLK33M_SMC LPC_SERIRQ
PM_CLKRUN_L LPC_PWRDWN_L SMC_TX_L SMC_RX_L (OC) SMB_MGMT_CLK
NC
OUT IN OUT IN BI
7 19 40 7 19 40 7 36 38 39 40 7 36 38 39 40 41
ETRST AVSS VSS
H3 L9 1
SMC_TRST_L NO STUFF
IN
7 40
R4902
10K
R4998
10K
R4903
0
XW4900 SM
2 1
5% 1/20W MF 2 201
5% 1/20W MF 2 201
5% 1/20W MF 2 201
GND_SMC_AVSS
39 42 43
40 39 38 36 7 40 39 38 36 7 41
(OC)
(DEBUG_SW_1) (DEBUG_SW_2)
25 36 19
39 39
OUT OUT BI BI BI OUT
39 34 7 37 7 19
SMC_PA0 SMC_PA1 PM_SYSRST_L USB_DEBUGPRT_EN_L MEM_EVENT_L WIFI_EVENT_L SYS_ONEWIRE PM_BATLOW_L
U4900
(OC) (OC) (OC) (OC) (OC) (OC)
NC
N3 N1 M3 M2 N2 L1 K3 L2 B8 C9 B9 A10 C10 B10 C11 A11 G11 G13 F12 H13 G10 G12 H11 J13 M10 N9 K10 L8 M9 N8 K9 L7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
H8S2117
LGA-HF (2 OF 3)
OMIT_TABLE
PE0 PE1 PE2 PE3 PE4 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PH0 PH1 PH2 PH3 PH4 PH5
K1 J3 K2 J1 K4 K5 N5 M6 L5 M5 N4 L4 M4 M8 N7 K8 K7 K6 N6 M7 L6 E2 F2 J2 A4 B3 C4
SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS SMC_G3H_POWERON_L SMC_SYS_LED SMC_LID

NC NC NC NC NC
IN IN IN OUT IN IN OUT IN
39 7 39 40 7 39 40 7 39 40 7 39 40 39
39 7 39 46 49
19 39 39
OUT IN OUT
(EXCARD_CP) (EXCARD_OC_L)
39
SMC_RUNTIME_SCI_L SMC_ODD_DETECT SMC_SLPS5_L SMC_PB4 39

39
SMC_MCP_SAFE_MODE
OUT
39
IN OUT OUT OUT OUT IN IN IN IN IN IN IN IN IN IN IN IN
SMC_DP_HPD_L SMC_GFX_OVERTEMP_L
NC
45 39 39 39 45 39 39 39
SMC_FAN_0_CTL SMC_FAN_1_CTL SMC_FAN_2_CTL SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS SMC_ANALOG_ID SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE SMC_ADC14 SMC_ADC15
(OC) (OC) (OC) (OC) (OC) (OC)
=SMC_SMS_INT SMB_BSA_DATA SMB_BSA_CLK SMB_A_S3_DATA SMB_A_S3_CLK SMB_B_S0_DATA SMB_B_S0_CLK SMC_PROCHOT SMC_THRMTRIP
IN BI BI BI BI BI BI OUT OUT
39 41 41 41 41 41 41
NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.
39 39
NC NC NC
39 39 39 39 39
SMC_PH3
39
H8S2117-R: (SMC_PECI) (SMC_PECI_VREF) (SMC_PECI_VSTP)
39 39 42 39
SYNC_MASTER=K16_MLB
PAGE TITLE
SMC
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

49 OF 110
SHEET
38 OF 73
8
=PP3V3_S5_SMC =PPVIN_S5_SMCVREF Desktops: 5V Mobiles: 3.42V
1
3
8
2
=PP3V3_S0_SMC
SMC Reset "Button", Supervisor & AVREF Supply

39 38 8 8
SMC FSB to 3.3V Level Shifting

1
R5061
100K
R5060
10K
5% 1/20W MF
C5020 1
0.47UF
10% 6.3V CERM-X5R 2 402
R5000
1K
V+
VIN
U5010
VREF-3.3V-VDET-3.0V
(IPU) 6 MR1* 7 MR2* (IPU)
REFOUT 8 THRM 4 DELAY GND
DFN
5% 1/20W MF 2 201
5% 1/20W MF 2 201
2 201
TO SMC
OUT
38
SMC_PROCHOT_3_3_L SMC_RESET_L PP3V3_S5_AVREF_SMC

OUT
38 7 38 40 50
46 7 46 39 38 7
IN IN
SMC_TPAD_RST_L SMC_ONOFF_L SMC_MANUAL_RST_L OMIT

1
SN0903048
RESET* 5
6 D
D
Q5060
DMB53D0UV
SOT-563
PAD
CPU_PROCHOT_BUF
1
2 G
R5001
0
5% 1/10W MF-LF
C5001
0.01UF
OMIT_TABLE
C5025 1
10uF
20% 6.3V 2 X5R 603
C5026
0.01UF
TO CPU
65 14 10
2603
10% 10V 2 X5R 201
R5062
1
SILK_PART=SMC_RST PLACEMENT_NOTE=Place R5001 on BOTTOM side
10% 2 10V X5R 201
BI
CPU_PROCHOT_L
3.3K 2
5% 1/20W MF 201
CPU_PROCHOT_L_R
5 4
Q5060
DMB53D0UV
SOT-563
S 1
GND_SMC_AVSS
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=0V
38 42 43
6 D
Q5059
SSM6N37FEAPE
SOT563
MR1* and MR2* must both be low to cause manual reset. Used on mobiles to support SMC reset via keyboard. NOTE: Internal pull-ups are to VIN, not V+.
1 S
G 2
SMC_PROCHOT
IN
38
Debug Power "Buttons"

OMIT SMC_ONOFF_L OMIT
1 OUT
7 38 39 46 42
SMC Aliases
SMC_LCDBKLT_ISENSE
MAKE_BASE=TRUE
65 14 10
OUT
PM_THRMTRIP_L
3 D
SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS SMC_ADC14 SMC_ADC15 SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE SMC_NB_MISC_ISENSE SMC_ANALOG_ID SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_IG_THROTTLE_L
MAKE_BASE=TRUE
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
38
Q5059
SSM6N37FEAPE
SOT563
R50141
0
5% 1/10W MF-LF 603 2
R5015
0 SILK_PART=PWR_BTN PLACEMENT_NOTEs: Place R5014 on TOP side Place R5015 on BOTTOM side
42
SMC_WLAN_ISENSE
MAKE_BASE=TRUE
38
5% 1/10W MF-LF 2 603
42
SMC_HDD_ISENSE
MAKE_BASE=TRUE
38
SILK_PART=PWR_BTN
43
SMC_CSREG_ISENSE
MAKE_BASE=TRUE
38
4 S
G 5
SMC_LCDBKLT_VSENSE
MAKE_BASE=TRUE
43
SMC_THRMTRIP
38 42 38
IN
38
SMC_MCP_CORE_ISENSE
MAKE_BASE=TRUE
43
SMC_MCP_DDR_ISENSE
MAKE_BASE=TRUE
38
SMC Pull-ups
39 38 8
42
SMC_1V5S3_ISENSE
MAKE_BASE=TRUE
38
=PP3V3_S5_SMC
TP_SMC_ANALOG_ID
MAKE_BASE=TRUE
38
SMC Crystal Circuit

R5010
38
TP_SMC_GPU_ISENSE
MAKE_BASE=TRUE
42
38
38 38
SMC_MCP_VSENSE
MAKE_BASE=TRUE
38 38
SMC_PA0 SMC_PA1 SMC_PB4 SMC_ONOFF_L SMC_LID SMC_TX_L SMC_RX_L SMC_TMS SMC_TDO SMC_TDI SMC_TCK SMC_ODD_DETECT SMC_BIL_BUTTON_L SMC_BC_ACOK SMC_GFX_OVERTEMP_L SMC_G3H_POWERON_L SMS_INT_L
R5091 R5092 R5088 R5070 R5071 R5073 R5074 R5077 R5078 R5079 R5080 R5040 R5081 R5087 R5094 R5098 R5093
100K 100K 10K 10K 100K 10K 100K 10K 10K 10K 10K
1 1 1
2 2 2
C5010
15PF
2 5% 25V NPO 201
5% 5% 5%
1/20W 1/20W 1/20W
MF MF MF
201 201 201
38
IN
SMC_GFX_THROTTLE_L SMS_INT_L
MAKE_BASE=TRUE
OUT
19 46 39 38 7
SMC_XTAL
SMC_XTAL_R CRITICAL 20.00MHZ

5X3.2-SM
1 1
5% 1/20W MF 201
39
OUT
=SMC_SMS_INT SMC_G3H_POWERON_L
MAKE_BASE=TRUE
IN
38
49 46 38 7 40 38 36 7
Y5010
19
IN
MCP_WAKE_REQ_L
OUT
38 39
40 38 36 7
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF MF MF MF MF MF MF MF MF
201 201 201 201 201 201 201 201 201 201 201 201 201
2
38
C5011
15PF
2
38
40 38 7
SMC_EXTAL
1 5% 25V NPO 201
R5096
IN
40 38 7
SMC_MCP_SAFE_MODE
MCP_SPKR
40 38 7
OUT
19 40 38 7
5% 1/20W MF 201
38 38
DP_PWR:S0
38 37 9 7 38 39 38
R5020
57 38 19 7
IN
PM_SLP_S3_L DP_PWR:SMC
10K 1 10K 1 470K 1 10K 1 100K 2 10K

1
2
2 2 2 1
DP_PWR_EN
MAKE_BASE=TRUE
R5021
38
IN
SMC_SLPS5_L
5% 1/20W MF 201
=DP_PWR_EN
OUT
61
39
2 5%
34 7
1/20W
MF
201
PP3V3_WLAN_F
5% 1/20W MF 201
DP_PWR:SMC
System (Sleep) LED Circuit

8
R5022
1
38 34 7
WIFI_EVENT_L
R5089 R5076
NO STUFF 10K 1 2
5% 1/20W MF 201
8
39 38
OUT
SMC_DP_HPD_L
=PP5V_S3_SYSLED SIL SIL

1
5% 1/20W MF 201
DP_EXT_HPD_L IN 61 PLACE_NEAR=Q9441.2:5 mm
46 38
=PP3V3_SMC_PME
5% 1/20W MF 201
SMC_PME_S4_L
100K
R50311
523
1% 1/16W MF-LF 402 2
R5030
40.2
38
Unused Pins
IN
SMC Pull-downs
57 38 19 38
1% 1/16W MF-LF 2 402
SMS_ONOFF_L
TP_SMS_ONOFF_L
MAKE_BASE=TRUE
SMC_ADAPTER_EN SMC_CASE_OPEN SMC_DP_HPD_L
R5085 R5086 R5090
10K 10K
1 1
2 2
SYS_LED_ILIM SYS_LED_L_VDIV SIL
38
IN IN
SMC_SYS_KBDLED SMC_FAN_1_CTL TP_SMC_FAN_1_TACH

MAKE_BASE=TRUE
TP_SMC_SYS_KBDLED
MAKE_BASE=TRUE
5% 5%
1/20W 1/20W
MF MF
201 201
38
TP_SMC_FAN_1_CTL
MAKE_BASE=TRUE
39 38
DP_PWR:S0 100K 1 2
5% 1/20W MF 201
R50321
1.47K
SMC_FAN_1_TACH NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE NO_TEST=TRUE
OUT
38
1% 1/16W MF-LF 402 2
6 D
5 B
4 E
38
IN
SMC_FAN_2_CTL NC_SMC_FAN_2_TACH
SIL
SMC_FAN_2_TACH NC_SMC_FAN_3_CTL
OUT
38
SYS_LED_L
Q1 S 1 G 2 Q2 C 3
Q5030
DMB54D0UV
SOT-563
38
IN
SMC_FAN_3_CTL NC_SMC_FAN_3_TACH
SYNC_MASTER=K16_MLB
PAGE TITLE OUT
38
SMC_FAN_3_TACH TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
SMC Support
DRAWING NUMBER SIZE
38
IN IN IN IN IN
SMC_RSTGATE_L SMC_P10 SMC_P20 SMC_P24 SMC_PH3
Apple Inc.
R
051-8379
REVISION
38
TP_SMC_P10
MAKE_BASE=TRUE
4.4.0
BRANCH PAGE
38
TP_SMC_P20
MAKE_BASE=TRUE

38
IN
SMC_SYS_LED
SYS_LED_ANODE
OUT
49
38
TP_SMC_P24
MAKE_BASE=TRUE
38
TP_SMC_PH3
MAKE_BASE=TRUE
50 OF 110
SHEET
39 OF 73
LPC+SPI Connector
CRITICAL LPCPLUS
D
8 7 8 7
55909-0374
=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS
BI BI
J5100
M-ST-SM 31 32 1 2 4 6 8
D
LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3> SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO
IN BI BI
7 25 68 7 19 38 68 7 19 38 68
68 38 19 7 68 38 19 7
LPC_AD<0> LPC_AD<1> SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS LPCPLUS_RESET_L SMC_TDO SMC_TRST_L SMC_MD1 SMC_TX_L
3 5 7 9 11 13 15 17 19 21 23 25 27 29 33
68 40 7 68 40 7 68 38 19 7 38 19 7 39 38 7 25 7 39 38 7 38 7 38 7 39 38 36 7
10 12 14 16 18 20 22 24 26 28 30 34
OUT
7 40 68 7 40 68
7 19 47
IN OUT OUT IN OUT IN OUT IN
BI IN OUT OUT OUT OUT OUT OUT
7 19 38 7 19 38 7 38 39 7 38 39 7 38 39 50 7 38 7 36 38 39 7 19
516S0573
SPI Bus Series Termination

SPI_ALT_MISO SPI_ALT_MOSI SPI_ALT_CLK SPI_ALT_CS_L LPCPLUS
1
7 40 68 7 40 68 7 40 68 7 40 68
LPCPLUS
1
LPCPLUS
1
LPCPLUS
1
R5128
0
R5127
47
R5126
47
R5125
47
5% 1/20W MF 2 201
5% 1/20W MF 2 201
5% 1/20W MF 2 201
5% 1/20W MF 2 201
R5110
68 19
IN
SPI_CS0_R_L
15
R5120
68
SPI_CS0_L
47
SPI_MLB_CS_L
OUT
47 68
R5111
68 19
IN
SPI_CLK_R
15
5% 1/20W MF 201
68
R5121
SPI_CLK
1
47
5% 1/20W MF 201
SPI_MLB_CLK
OUT
47 68
R5112
68 19
IN
SPI_MOSI_R
15
5% 1/20W MF 201
68
R5122
SPI_MOSI
1
47
5% 1/20W MF 201
SPI_MLB_MOSI
OUT
47 68
B
68 19
5% 1/20W MF 201
OUT
R5123
1
SPI_MISO
15
5% 1/20W MF 201
SPI_MLB_MISO
B
IN
47 68
5% 1/20W MF 201
EFI Debug ROM

8
=PP3V3_S0_DEBUGROM EFI_DEBUG EFI_DEBUG

1
R51011
5% 1/20W MF 201 2
R5103
0
EFI_DEBUG
C5101
0.1UF
5% 1/20W MF 2 201
20% 10V CERM 2 402
EFI_DEBUG
VCC
U5101
3 E2 2 E1
NO STUFF
DEBUGROM_E2 DEBUGROM_E1 NO STUFF

1
M24M01-R
SO8N
SDA 5 6
=I2C_DEBUGROM_SDA =I2C_DEBUGROM_SCL
NC
BI IN
41
CRITICAL SCL
VSS 4
41
R51021
5% 1/20W MF 201 2
R5104
0
5% 1/20W MF
7 WC*
SYNC_MASTER=K16_MLB
PAGE TITLE
E0/NC0 1
LPC+SPI Debug Connector

DRAWING NUMBER SIZE
2 201
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE
Write: 0xAC/0xAE Read: 0xAD/0xAF

51 OF 110
SHEET
40 OF 73
MCP89 SMBus "0" Connections

8
SMC "0" SMBus Connections

8
SMC "Battery A" SMBus Connections

8
=PP3V3_S0_SMBUS_MCP_0
=PP3V3_S0_SMBUS_SMC_0_S0 NO STUFF NO STUFF

1
=PP3V42_G3H_SMBUS_SMC_BSA
MCP89
U1400 (MASTER)
R52001
5% 1/20W MF 201 2
R5201
1K
1K
LP8545 (Bklt)
U9701 (Write: 0x58 Read: 0x59) =I2C_BKL_1_SCL =I2C_BKL_1_SDA
62 38
SMC
U4900 (MASTER) SMB_0_S0_CLK SMB_0_S0_DATA
70
R52501
2.0K
5% 1/20W MF 201 2
R5251
2.0K
SMC
U4900 (MASTER)
38
R52801
2.61K
1% 1/20W MF 201 2
R5281
2.61K
Battery Charger
ISL6259 - U7000 (Write: 0x12 Read: 0x13) =SMBUS_CHGR_SCL =SMBUS_CHGR_SDA
50
5% 1/20W MF 2 201
5% 1/20W MF 2 201
1% 1/20W MF 2 201
68 19
SMBUS_MCP_0_CLK
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA
SMB_BSA_CLK SMB_BSA_DATA
70 7
SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
62 38 70 38
MAKE_BASE=TRUE
70 7 50
68 19
SMBUS_MCP_0_DATA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
XDP Connector
J1300 (MASTER)
13
DPI2C:MCP
DPI2C:SMC
DPI2C:SMC
1
R5241
2
R52421
5% 1/20W MF 201 2
71
R5243
0
Internal DP
J9000 (See Table) =I2C_TCON_SCL =I2C_TCON_SDA
7 59
Battery Battery
J6950 (See Table) =SMBUS_BATT_SCL =SMBUS_BATT_SDA
49
=I2C_XDP_SCL =I2C_XDP_SDA
5% 1/20W MF 201
5% 1/20W MF 2 201
I2C_TCON_SCL I2C_TCON_SDA
MAKE_BASE=TRUE
13
DPI2C:MCP
71
7 59
R5240
2
MAKE_BASE=TRUE
Battery Manager - (Write: 0x16 Read: 0x17) Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Temp - (Write: 0x90 Read: 0x91)
49
Vref DACs
U3900 (Write: 0x98 Read: 0x99)
33
5% 1/20W MF 201
Internal DP
Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) Parade T-con - (0x10-0x1F or 0x30-0x3F) DVR - (Write: 0x4E Read: 0x4F)
=I2C_VREFDACS_SCL =I2C_VREFDACS_SDA
K16 Samsung N Y Y
(* = Multiple K99 LGD Samsung Y * N * Y Y
options) LGD Y N Y AUO * * N
SMC "Management" SMBus Connections

The bus formerly known as "Battery B"
8
=PP3V3_S5_SMBUS_SMC_MGMT
33
Margin Control
SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state
8
SMC
U4900 (MASTER)
38
R52901
2.0K
5% 1/20W MF 201 2
R5291
2.0K
U3910 (Write: 0x30 Read: 0x31)

33
=PP3V3_S3_SMBUS_SMC_A_S3
5% 1/20W MF 2 201
SMB_MGMT_CLK SMB_MGMT_DATA
70
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
C
Trackpad
J5700 (Write: 0x90 Read: 0x91) =I2C_TPAD_SCL
7 46
=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA
MAKE_BASE=TRUE
70
33
SMC
U4900 (MASTER)
R52701
5% 1/20W MF 201 2
70
1K
R5271
1K
Left I/O Board

J4700 (See Table) =I2C_LIO_SCL =I2C_LIO_SDA
7 37
38
MAKE_BASE=TRUE
5% 1/20W MF 2 201
EFI Debug Serial

U5101 (Write: 0xAC/0xAE Read: 0xAD/0xAF) 40 =I2C_DEBUGROM_SCL
40
Mikey
J4700 (LIO Connector)
(Write: 0x72 Read: 0x73) =I2C_MIKEY_SCL =I2C_MIKEY_SDA
7 37 7 37
38
SMB_A_S3_CLK SMB_A_S3_DATA
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
70
38
MAKE_BASE=TRUE
7 37
=I2C_DEBUGROM_SDA
Left I/O Board

ALS - N/A (Feature Removed) Finstack Temp - (Write: 0x98 Read: 0x99)
=I2C_TPAD_SDA
7 46
MCP89 SMBus "1" Connections

8
SMC "B" SMBus Connections

8
=PP3V3_S0_SMBUS_MCP_1 NO STUFF NO STUFF

1
=PP3V3_S0_SMBUS_SMC_B_S0
MCP89
R52301
2.0K
5% 1/20W MF 201 2
R5231
2.0K
SMC
U4900 (MASTER)
38
R52601
4.7K
5% 1/20W MF 201 2
R5261
4.7K
CPU Temp
EMC1413: U5515 (Write: 0x98 Read: 0x99) =I2C_CPUTHMSNS_SCL =I2C_CPUTHMSNS_SDA
44
U1400 (Write: 0xE0 Read: 0xE1)

68 19
5% 1/20W MF 2 201
5% 1/20W MF 2 201
SMBUS_MCP_1_CLK
MAKE_BASE=TRUE
SMB_B_S0_CLK SMB_B_S0_DATA
70
SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
70
68 19
SMBUS_MCP_1_DATA
MAKE_BASE=TRUE
38
MAKE_BASE=TRUE
44
R5235
MCP89 SMBus 1 is slave port to access internal thermal diodes. Another slave port is available at 0x10/0x11, probably not used. 0
R5236
0
5% 1/20W MF 201 2
5% 1/20W MF 2 201
MCP Temp
EMC1413: U5535 (Write: 0xD8 Read: 0xD9) =I2C_MCPTHMSNS_SCL =I2C_MCPTHMSNS_SDA
44
44
SYNC_MASTER=K16_MLB
PAGE TITLE
K16/K99 SMus Connections

DRAWING NUMBER SIZE
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R
051-8379
REVISION
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BRANCH PAGE

52 OF 110
SHEET
41 OF 73
CPU Voltage Sense / Filter

8 7
DDR3 1V5R1V35 Current Sense / Filter

8
=PP3V3_S3_1V5S3ISNS
PPVCORE_S0_CPU
XW5309 SM
1 2
R5309
CPUVSENSE_IN
1
4.53K2
1% 1/20W MF 201
SMC_CPU_VSENSE
1
OUT
38
PLACE_NEAR=L7400.2:5 MM
C5309
0.22UF ISNS_1V5_S3_N ISNS_1V5_S3_P
5 IN4 IN+
71 52 38 39 42 43
C5360
0.1UF
V+
20% 2 6.3V X5R 201
U5360
INA210
SC70
IN
10% 2 6.3V X5R 201

6
R5365
1
GND_SMC_AVSS Place RC close to SMC
OUT
ISNS_1V5S3_IOUT
4.53K 2
1% 1/20W MF 201
SMC_1V5S3_ISENSE
1
OUT
39
71 52
IN
(500V/V)
GND
2
REF 1
GAIN: 200X
SCALE: 0.4A / V MAX VOUT: 3.5V (CLIPS AT 6.6A)
C5365
0.22UF
MCP Voltage Sense / Filter

8 7
EDP Current: 7 A Max Vdiff: 13.0 mV WF: Verify SO-DIMM current!
20% 2 6.3V X5R 201
GND_SMC_AVSS
38 39 42 43
PLACEMENT_NOTEs: Place close to SMC (For R and C)
PPVCORE_S0_MCP
XW5359 SM
1 2
R5359
MCPVSENSE_IN
1
4.53K2
1% 1/20W MF 201
SMC_MCP_VSENSE
1
OUT
39
PLACE_NEAR=R7525.2:5 MM
C5359
0.22UF
AirPort Current Sense / Filter

8
20% 2 6.3V X5R 201
=PP3V3_S3_WLANISNS
GND_SMC_AVSS Place RC close to SMC
38 39 42 43
C5370
0.1UF
10% 201
V+
U5370
2 6.3V X5R
6
PBUS Voltage Sense Enable & Filter

Q5315
71 34
IN
ISNS_AIRPORT_N ISNS_AIRPORT_P
5 IN4 IN+
INA210
SC70
OUT
ISNS_P5VWLAN_IOUT
14.53K 2
1% 1/20W MF 201
R5375
SMC_WLAN_ISENSE
1
OUT
39
71 34
IN
(200V/V)
GND
2
REF 1
Gain: 200x
Scale: 0.25A / V MAX VOUT: 3V (CLIPS AT 0.825A)
C5375
0.22UF
C
57
NTUD3169CZ
SOT-963
20% 2 6.3V X5R 201
N-CHANNEL
D
PBUSVSENS_EN_L
GND_SMC_AVSS
C
38 39 42 43
R53161
100K
1% 1/20W MF 201 2
IN
=PBUSVSENS_EN
2 1
G S
EDP Current: 0.727 A? Max Vdiff: 14.6 mV WF: Verify Airport current!
Enables PBUS VSense divider when high.
3
D
PBUS_G3H_VSENSE
HDD Current Sense / Filter

R5317
1
8
=PP3V3_S0_HDDISNS
5
49 8 7
G S
27.4K
3
1% 1/20W MF 201 2
PPBUS_G3H
4
RTHEVENIN = 4573 Ohms SMC_PBUS_VSENSE

OUT
38
C5380
0.1UF
10% 201
P-CHANNEL
V+
R5315
100K
1% 1/20W MF 201 2
R53181
5.49K PBUSVSENS_EN_L_DIV
1% 1/20W MF 201 2
U5380
1
2 6.3V X5R
6
C5315
0.22UF
71 35
IN
ISNS_HDD_N ISNS_HDD_P
5 IN4 IN+
INA211
SC70
OUT
ISNS_P5VHDD_IOUT
14.53K 2
1% 1/20W MF 201
R5385
SMC_HDD_ISENSE
1
OUT
39
20% 2 6.3V X5R 201
71 35
IN
(500V/V)
GND
2
REF 1
GAIN: 500X
SCALE: 0.667A / V MAX VOUT: 3.54V (CLIPS AT 2.2A)
C5385
0.22UF
GND_SMC_AVSS
38 39 42 43
Place RC close to SMC EDP Current: 1.2 A? Max Vdiff: 24.0 mV WF: Verify SSD current!
20% 2 6.3V X5R 201
GND_SMC_AVSS
38 39 42 43
LCD Backlight Driver Input Current Sense / Filter

8
=PP3V3_S0_BKLTISNS
C5390
0.1UF
10% 201
V+
U5390
71 62
6.3V 2 X5R
6
IN
ISNS_LCDBKLT_N ISNS_LCDBKLT_P
5 IN4 IN+
INA211
SC70
OUT
ISNS_LCDBKLT_IOUT
14.53K 2
1% 1/20W MF 201
R5395
SMC_LCDBKLT_ISENSE
1
OUT
39
71 62
IN
(500V/V)
GND
2
REF 1
GAIN: 500X
C5395
0.22UF
62 59 7
PPVOUT_SW_LCDBKLT
XW5310 SM
1 2
LCDBKLT_VSEN
PLACE_NEAR=D9701.2:5 MM
SCALE: 0.2A / V MAX VOUT: 3.33V (CLIPS AT 0.66A) PLACEMENT_NOTEs: Place close to SMC (For R and C)
20% 2 6.3V X5R 201
GND_SMC_AVSS
38 39 42 43
R53191
1M
1% 1/20W MF 2012
LCDBKLT_VSEN_DIV 1 226K 2
R5321 PLACE_NEAR=U4900:5
SMC_ADC15 OMIT_TABLE
1 2
1% 1/20W MF 201
MM
OUT
38 39
EDP Current: ??? A Max Vdiff: ??? mV WF: Verify LCD backlight current!
PLACE_NEAR=U4900:5 MM
R5320
47K
SYNC_MASTER=K16_MLB
PAGE TITLE
1% 1/20W MF 2012
C5310
2.2UF
20% 6.3V X5R 0402
Voltage & Current Sensing

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
DIVIDER: 1/22
4.4.0
BRANCH PAGE

53 OF 110
SHEET
42 OF 73
DCIN (AMON) Current Sense, RMUX & Filter
ISL6259 Gain: 20x

R5481
50
MCP MEM VDD Current Sense / Filter

8
IN
CHGR_AMON
150K 2
1% 201
=PP3V3_S0_MCPDDRISNS
SMC_DCIN_ISENSE
OUT
38
Sense R: R7020 Value: 20 mOhm MAX VOUT: 1.24V
1/20W From charger MF
R5482
133K
NOSTUFF 1
1% 1/16W MF-LF 402 2
C5487
C5400 1
0.1UF
10% 6.3V 2 X5R 201
D
1 3
5
+IN -IN
10% 2 25V CERM 402
0.0068UF
U5400 OPA330
SC70-5
21
IN
MCPDDRFET_KELVIN MCPDDRFET_SENSE
V+ V2
GND_SMC_AVSS 38 39 PLACEMENT_NOTEs:
MCPDDR_SENSE_AMP
42 43 21
IN
Place close to SMC (For Rs and C)
R54101
5% 1/20W MF 201 2
R54111
0
MCPDDR_SENSE_E
5% 1/20W MF 2012
Battery (BMON) Current Sense, MUX & Filter

8
NOSTUFF
1
CRITICAL
2
C5434
0.1UF
=PP3V42_G3H_BMON_ISNS BMON:ENG
1
For engineering, stuff BMON:ENG For production, stuff BMON:PROD BMON:ENG
Q5401
SOD 1
2SA2154MFV-YAE MCPDDR_SENSE_B
10% 2 6.3V X5R 201
PLACEMENT_NOTE=Place near sense resistor Charger/Load side

70 50
C5418
0.1UF
C5459 1
0.1UF
10% 6.3V 2 X5R 201
CRITICAL BMON:ENG
R5417
MCPDDR_SENSE_C
1
V+
IN
CHGR_CSO_R_P CHGR_CSO_R_N
5 4
70 50
IN
SC70 OUT 6 BMON:ENG IN+ REF 1 (100V/V)

IN-
U5403 INA214
GND
10% 2 6.3V X5R 201
U5413
NC7SB3157P6XG
1 B1 SC70
1 SEL 6
4.53K 2
1% 1/16W MF-LF 402
SMC_MCP_DDR_ISENSE
1
OUT
39
BMON_INA_OUT
SMC_BMON_MUX_SEL
IN
38
R5412
118
C5435
0.22UF
GAIN: 100X
SCALE: 1A / V MAX VOUT: 3.00V (CLIPS AT 3.3A)
2 GND
0
VCC 5
Battery side NOTE: Monitoring current from battery to PBUS (battery discharge) across R7050
50
R5401
4
ISL6259 Gain: 36x INA213 Gain: 50x

SMC_BATT_ISENSE
1 OUT
38
1% 1/16W MF-LF 402 2
20% 2 6.3V X5R 402
C
38 39 42 43
GND_SMC_AVSS
3
B0 A
BMON_AMUX_OUT BMON:ENG
1
300K 2
1% 1/20W MF 201
VER 1
BMON:PROD
R5423
100K
C5490
0.0033UF
R5431
IN
CHGR_BMON
Sense R: R7050 Value: 10 mOhm Max Vdiff: 80mV
From charger
Gain: 36x
Scale: 2.778A / V Max VOut: 2.88V
5% 1/20W MF 201
5% 1/20W MF 2 201
10% 50V 2 CERM 402
GND_SMC_AVSS 38 39 PLACEMENT_NOTEs: (For R and C)
42 43
R5431: PLACE_NEAR=U5413:2 mm
Chipset Regulators High-Side Current Sense / Filter

8
=PP3V3_S0_CSREGISNS
VERIFY ALL RESISTOR AND GAINS

3 1
=PPBUS_G3H_R_IN CRITICAL
C5417
0.1UF
R5492 1
0.002
V+
B
8
1% 1W MF 0612 2 4
U5402
71
ISNS_CSREG_N ISNS_CSREG_P
5 IN4 IN+
INA210
SC70
10% 2 6.3V X5R 201
R5418
1
OUT 6
REF 1
CSREG_IOUT
4.53K 2
1% 1/20W MF 201
SMC_CSREG_ISENSE
1
OUT
39
B
CPU VCore Load Side Current Sense / Filter
71
=PPBUS_G3H_R_OUT
(200V/V)
GND
2
GAIN: 200X
SCALE: 2.5A / V MAX VOUT: 3.352V
C5436
0.22UF
20% 2 6.3V X5R 402
42 43
R5471
53
Place close to SMC (For R and C)
IN
IMVP6_PMON
15.0K 2
1% 1/16W MF-LF 402
SMC_CPU_ISENSE
OUT
38
R5480
17.4K
NOSTUFF 1
1
C5470
0.068UF
PLACEMENT_NOTEs:
MCP VCore Current Sense Filter

R5416
8
Place close to SMC (For Rs and C)
1% 1/16W MF-LF 402 2
10% 2 10V CERM 402
GND_SMC_AVSS SMC_MCP_CORE_ISENSE
1
OUT
39
38 39 42 43
=PP3V3_S0_MCPCOREISNS
54
IN
MCPCORES0_IMON
4.53K 2
1% 1/20W MF 201
C5472
0.22UF
C5420
0.1UF
V+
(Sense R "output")
U5420
5 IN4 IN+
IN
=MCPCOREISNS_N =MCPCOREISNS_P (Sense R "input")
INA214
SC70
10% 2 6.3V X5R 201
20% 2 6.3V X5R 201
R5415
1
OUT 6
REF 1
MCPCORE_IOUT
42 43
Gain: 100x
Scale: 10A / V MAX VOUT: 2.38V
IN
(100V/V)
GND
2
5% 1/20W MF 201
Place close to SMC (For R and C)
SYNC_MASTER=K16_MLB
PAGE TITLE
Sense R is R7525, 1mOhm Max Vdiff = 24.8mV
NOTE: Do not stuff R5415 and R7593 at the same time!
Current Sensing
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

54 OF 110
SHEET
43 OF 73
CPU T-Diode Thermal Sensor

D
8
=PP3V3_S0_CPUTHMSNS
R5515
1
FIXME: OFFGRID PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V 1 VDD 1
D
C5515
0.1UF R5516 1
10K
1% 1/20W MF 201 1
47
5% 1/20W MF 201
71 10
BI
CPU_THERMD_P
C5521 1
CPU Thermal Diode CPU_THERMD_N DRAMTHMSNS_D2_P
3
10% 2 6.3V X5R 201
R5517
10K
5% 1/20W MF 201
2.2NF
U5515
EMC1413
DFN 2 DP1 THERM*/ADDR 3 DN1CRITICAL ALERT* 4 DP2/DN3 SMDATA SMCLK
THRM_PAD 11
10% 10V 2 X5R 201
7 8 9 10
CPUTHMSNS_THERM_L CPUTHMSNS_ALERT_L
71 10
BI
DRAM/SSD Temperature CRITICAL
=I2C_CPUTHMSNS_SDA =I2C_CPUTHMSNS_SCL
BI BI
41
C5520 1
1
Q5501
BC846BMXXH
SOT732-3 2
2.2NF
10% 10V 2 X5R 201
5 DN2/DP3 GND 6
Addr: 0x98(Wr)/0x99(Rd)
41
71
DRAMTHMSNS_D2_N
PLACEMENT_NOTE=Place U5515 near CPU Local sensor for CPU Proximity
PLACEMENT_NOTE=Place Q5501 near DRAMs below MCP
MCP T-Diode Thermal Sensor

8
=PP3V3_S0_MCPTHMSNS
R5535
1
47
PP3V3_S0_MCPTHMSNS_R
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V 1
5% 1/20W MF 201
71 19
C5535
0.1UF R5536 1
15K
1% 1/20W MF 201 1
BI
MCP_THMDIODE_P
C5522 1
MCP Thermal Diode 2.2NF
VDD
10% 2 6.3V X5R 201
R5537
10K
5% 1/20W MF 201
B
71 19
10% 10V 2 X5R 201
EMC1413
DFN
DP1 DN1
THERM*/ADDR
U5535
MCPTHMSNS_THERM_L MCPTHMSNS_ALERT_L
Addr: 0xD8(Wr)/0xD9(Rd)
BI
MCP_THMDIODE_N
71
CRITICAL
ALERT* SMDATA SMCLK
MLBR_THMDIODE_P
DP2/DN3 DN2/DP3 GND
=I2C_MCPTHMSNS_SDA =I2C_MCPTHMSNS_SCL
BI BI
41
CRITICAL
C5523 1
1
41
THRM_PAD
Q5535 BC846BMXXH
SOT732-3 2
71
2.2NF
10% 10V 2 X5R 201
PLACEMENT_NOTE=Place U5535 near MCP Local sensor for MCP Proximity
MLBR_THMDIODE_N
PLACEMENT_NOTE=Place Q5535 near J9000
SYNC_MASTER=K16_MLB
PAGE TITLE
Thermal Sensors
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

55 OF 110
SHEET
44 OF 73
FAN CONNECTOR
C
8
C
=PP5V_S0_FAN =PP3V3_S0_FAN
38
SMC_FAN_0_TACH 1
R56601 47K R5665 2 47K

5% 1/20W MF 201
7
CRITICAL
FF14A-4C-R11DL-B-3H F-RT-SM
J5600
5 1 2 3 4
NC
2 FAN_RT_TACH NC
5% 1/20W MF 201
5V DC TACH MOTOR CONTROL GND
R56611
1/20W MF 201
1
100K 5%
Q5660
D
7
518S0793
2
2
SSM3K15FV
SOD-VESM-HF
38
SMC_FAN_0_CTL
FAN_RT_PWM
SYNC_MASTER=K16_MLB
PAGE TITLE
Fan
DRAWING NUMBER SIZE
Apple Inc.
R
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REVISION
4.4.0
BRANCH PAGE

56 OF 110
SHEET
45 OF 73
IPD Flex Connector

IPD_3V3:S5
R5730
8
=PP3V3_S5_TPAD
D
CRITICAL PP3V3_TPAD_CONN
MIN_NECK_WIDTH=0.20mm
7
5% 1/16W MF-LF 402
IPD_3V3:S3
R5731
0
2
1 8 =PP3V3_S3_TPAD
FF14A-14C-R11DL-B-3H F-RT-SM
MIN_LINE_WIDTH=0.5 mm
J5700
15 1 2 3 4 5 6 7 8 9 10 mm11 12 13 14 16
5% 1/16W MF-LF 402
VOLTAGE=3.3V
C5700 1
0.1UF
10% 6.3V X5R 201
39 38
OUT
SMC_PME_S4_L
71 46 7 71 46 7
BI BI
USB_TPAD_CONN_P USB_TPAD_CONN_N
BI BI
L5720
FERR-120-OHM-1.5A
56 46 41 7 46 41 7
=I2C_TPAD_SDA =I2C_TPAD_SCL
PP5V_S5_LDO
1 0402-LF
PP5V_TPAD_FILT
49 46 39 38 7
C5710 1
0.1uF
20% 10V CERM 402
VOLTAGE=5V MIN_NECK_WIDTH=0.20mm MIN_LINE_WIDTH=0.5 SMC_ONOFF_L 46 39 38 7 OUT IN
SMC_LID SMC_TPAD_RST_L
2
46 39 7
OUT
8 7
=PP3V42_G3H_TPAD C5720 1
0.1UF
10% 6.3V X5R
518S0794
201 PLACE_NEAR=J5700.13:1.5MM
L5710 90-OHM
DLP0NS SYM_VER-1
71 68 18
BI
USB_TPAD_P USB_TPAD_N
4 1
3 2
USB_TPAD_CONN_P USB_TPAD_CONN_N =I2C_TPAD_SDA =I2C_TPAD_SCL
BI
7 46 71
71 68 18
BI
BI
7 46 71
7 41 46
7 41 46
C5732 1
100PF PLACE_NEAR=J5700.8:1.5MM100PF
10% 25V X7R-CERM 10% 25V X7R-CERM 201
SMC_ONOFF_L C5733 1
2 C5734 1
25V X7R-CERM 201
7 38 39 46
B
39 46
SMC_LID
7 38 39 46 49
SMC_TPAD_RST_L 7
201 PLACE_NEAR=J5700.9:1.5mm100PF 10%
2 C5735 1
25V X7R-CERM
100PF PLACE_NEAR=J5700.11:1.5MM 10%
2 C5736 1
25V X7R-CERM
201 100PF PLACE_NEAR=J5700.12:1.5MM 10%
201 PLACE_NEAR=J5700.14:1.5MM
SYNC_MASTER=K16_MLB
PAGE TITLE
WELLSPRING 1
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

57 OF 110
SHEET
46 OF 73
=PP3V3_S5_ROM SPI:41MHZ&SPI:62MHZ 3.3K

5% 1/20W MF 2 201
SPI:31MHZ&SPI:62MHZ
R61501
C
68 40
10K
5% 1/20W MF 201 2
IN
R6101
C6100 1
0.1UF
10% 6.3V 2 X5R 201 6 SCLK
CRITICAL
R6151
10K
VCC
U6100
32MBIT
SOP SI/SIO0 5 MX25L3205DM2I-12G
5% 1/20W MF 2 201
C
IN
40 68
SPI_MLB_CLK SPI_MLB_CS_L SPI_WP_L SPIROM_USE_MLB SPI:25MHZ&SPI:41MHZ
SPI_MLB_MOSI
68 40
IN
1 CE*
OMIT_TABLE
SO/SIO1 2
3 WP*/ACC
7 HOLD*
SPI_MLB_MISO
OUT
40 68
40 19 7
IN
NOTE: If HOLD* is asserted ROM will ignore SPI cycles.
R61521
10K
5% 1/20W MF 201 2
GND 4
SPI:25MHZ&SPI:31MHZ
1
R6153
10K
5% 1/20W MF 2 201
MCP89 SPI Frequency Select

Frequency SPI_MOSI SPI_CLK 25.0 MHz 31.2 MHz 0 0 1 1 0 1 0 1
41.7 MHz 62.5 MHz
NOTE: 42 & 62 MHz use FAST_READ command.
SYNC_MASTER=K16_MLB
PAGE TITLE
SPI ROM
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

61 OF 110
SHEET
47 OF 73
SPEAKER AMPLIFIERS
APN:353S2888
SPEAKER LOWPASS
80 HZ < FC < 132 HZ
D
GAIN 6DB
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25MM
R6614
1
=PP5V_S3_AUDIO_AMP
MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V
PP5V_S3_U6610 0.1UF
A1
5% 1/16W MF-LF 402
C6607 1
10% 6.3V 2 X5R 201
NOSTUFF
CRITICAL
1
R66131
100K
5% 1/20W MF 201 2
C6601
47UF
PVDD
CRITICAL
C6610
0.1UF
1 2 10% 6.3V X5R 201
U6610
MAX98300
A3 IN+ B3 INC2 SHDN* B2 NC WLP
OUT+ B1 OUT- C1 GAIN C3
20% 2 6.3V POLY-TANT 2012-LLP
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_P_OUT
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
7 49
71 37 7
IN
SPKRAMP_INR_P CRITICAL
71 71
MAX98300_R_P MAX98300_R_N
SPKRAMP_R_N_OUT R_AMP_GAIN NOSTUFF

1
7 49
C6611
0.1UF
1 2 10% 6.3V X5R 201
R_SPKRAMP_SHDN
71 37 7
IN
SPKRAMP_INR_N
R6610
1
R6612
100K
R6611
100K
5% 1/20W MF 201
5% 1/20W MF 2 201
A2
37 7
IN
AUD_GPIO_3
PGND
5% 1/20W MF 2 201
SYNC_MASTER=AUDIO
PAGE TITLE
AUDI0: SPEAKER AMP

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

66 OF 110
SHEET
48 OF 73
MLB TO LIO POWER CABLE CONNECTOR

J6900
WTB-PWR-M82
M-RT-SM
1 2 3 4 5
=PP18V5_DCIN_CONN
MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V
7 8
C6905
0.01UF
20% 50V CERM 603
APN:518S0519
CRITICAL
J6903
78171-0002
M-RT-SM 3
=PP5V_S3_LIO_CONN
7 8
518S0508
1 C6906
0.01UF
10% 10V X5R 201
48 7 48 7
IN IN
SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT
1 2
SPKR
8
=PP3V3_S3_DBGLEDS S3_S0_LED
1 1
R6940
1K
R6941
1K
S3_S0_LED
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
ITS_ALIVE
CORE_VOLTAGES_ON_R
C
A
SIL ON MLB FOR DEVELOPMENT ONLY SIL D6900

SYS_LED_ANODE
39
C
998-3029
S3_S0_LED
D6910
GREEN-3.6MCD 2.0X1.25MM-SM
S3_S0_LED
D6920
GREEN-3.6MCD 2.0X1.25MM-SM
GREEN-3.6MCD
2.0X1.25MM-SM
J6955
HALL-SENSOR-MLB-PADS-K99
SM
NC
8 7
8 7 6 5
1 2 3 4
NC
=PP3V42_G3H_HALL
CORE_VOLTAGES_ON
NC
NC
R6961
3
Q6940
2N7002DW-X-G
SOT-363
OMIT_TABLE
SMC_LID 7 38 39 46
S3_S0_LED
D 5
7 SMC_LID_R
S 4
ALL_SYS_PWRGD
25 38 57
5% 1/20W MF 201
NOSTUFF
C6955
10% 50V CERM 402
0.001UF
2
S3 AND S0 INDICATOR LEDS FOR DEVELOPMENT ONLY
HALL EFFECT PADS
B
CRITICAL
B
D6905
BAT30CWFILM
SOT-323
3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator
42 8 7
PPBUS_G3H
R6905
10
50
3
2
PPVIN_G3H_P3V42G3H
PPDCIN_G3H_OR_PBUS
1 5% 1/8W MF-LF 805
PPDCIN_G3H_OR_PBUS_R
VOLTAGE=18.5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
P3V42G3H_BOOST
DIDT=TRUE
C6990
2.2UF
C6994
VIN
2
BOOST
0.22UF
20% 6.3V X5R 201 2
CRITICAL
J6950
BAT-K99
F-RT-TH
BATTERY CONNECTOR
50 7 PPVBAT_G3H_CONN
10% 25V X5R-CERM 603
CRITICAL
U6990
LT3470A
8
L6995
33UH-20%-0.39A-0.435OHM
=PP3V42_G3H_REG
SHDN* NC
DFN CRITICAL
SW
BIAS
4 2
P3V42G3H_SW
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE
1 DP418C-SM
Vout = 3.425V 60MA MAX OUTPUT <Ra>
POS POS POS SCL SDA SYS_DETECT NEG NEG NEG SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN
1 2 3 4 5 6 7 8 9 10 11 12 13
=SMBUS_BATT_SCL CRITICAL
NC
7 SYS_DETECT_L
GND
5
FB THRM PAD
9
1
1
C6995
22PF
5% 50V CERM 201
R6995
348K
1% 1/20W MF 201
(Switcher limit)
=SMBUS_BATT_SDA
41 41
CRITICAL
2 1
OMIT_TABLE
C6999
10UF
20% 6.3V X5R 603-1
D6950
1 2
P3V42G3H_FB
RCLAMP2402B
SC-75
R6950
10K
5% 1/20W MF 201
C6950
0.1UF
10% 25V X5R 402
C6951 1
1UF
10% 16V X5R 402
<Rb>
R6996
1
SYNC_MASTER=K84_MLB
PAGE TITLE
NOSTUFF
200K
1% 1/20W MF 201
DC-In & Battery Connectors

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE
518-0369
Vout = 1.25V * (1 + Ra / Rb)
69 OF 110
SHEET
49 OF 73
6
This node is powered through body diodes:
Reverse-Current Protection
Inrush Limiter
* DCIN through Q7080. * PBUS through Q7085, Charger TOP FETs and
FROM ADAPTER
CRITICAL
8
Q7055. CRITICAL PPDCIN_G3H_OR_PBUS

=PPDCIN_S5_CHGR
Q7080 SI5419DU
POWERPAK
49
Q7085 SI5419DU
POWERPAK PPDCIN_G3H_INRUSH
R7080
100K
5% 1/20W MF 201
C7085
0.1UF
10% 25V X5R 402
R7085
470K
1% 1/20W
2 2 201
MF
CHGR_SGATE_DIV
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm 1
R7081
62K
5% 1/20W MF 201
CRITICAL
D7005
BAT30CWFILM
SOT-323 1
(CHGR_SGATE)
R7005
20
3
CHGR_DCIN_D_R
(CHGR_DCIN)
1
ACIN pin threshold is 3.2V, +/- 50mV DIVIDER SETS ACIN THRESHOLD AT 12.18V Input impedance of ~40K meets 30mA max load sparkitecture requirements PP5V1_CHGR_VDD
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=5.1V 1 5% 1/16W MF-LF 402
5% 1/20W MF 201
1
C7020
0.047UF
10% 16V
X7R 402
R7001
4.7
2
PP5V1_CHGR_VDDP
57 8
=PP3V42_G3H_CHGR
C7001
1UF
10% 10V X5R 402
C7022
0.1UF
10% 25V X5R 402
R7010
30.1K
1% 1/20W MF 201
C7002
1UF
10% 10V X5R 402
1 2
NO STUFF GND_CHGR_AGND
50
R7002
19
100K
5% 1/20W MF 201 12
20
R7000
0
40 39 38 7
2
2
IN
SMC_RESET_L
CHGR_RST_L
41 41 57
13 11 10 4 6
ISL6259HRTZ
5% 1/20W MF 201
IN BI IN
=SMBUS_CHGR_SCL =SMBUS_CHGR_SDA CHGR_VFRQ CHGR_CELL
Float CELL for 1S CHGR_ACIN CHGR_ICOMP
5 7 8 18 17
R7013
100
1% 1/20W MF 201
CHGR_VCOMP CHGR_VNEG
1 2
VDD VDDP OMIT_TABLE CRITICAL VHST DCIN SMB_RST_N SGATE SCL U7000 AGATE TQFN SDA CSIP VFRQ CSIN CELL BOOT ACIN UGATE ICOMP PHASE VCOMP LGATE VNEG CSOP CSON THRM_PAD BGATE AMON 36V/V BMON (OD) ACOK
20V/V
CHGR_DCIN CHGR_SGATE CHGR_AGATE

70 70
1
PLACE_NEAR=U7000.25:2mm
26 1 28 27
CHGR_CSI_P CHGR_CSI_N CHGR_BOOT

DIDT=TRUE
25 24 23
CHGR_UGATE
GATE_NODE=TRUE DIDT=TRUE
CHGR_PHASE CHGR_LGATE
21
R7015
220K
5% 1/20W MF 201
70 CHGR_CSO_P 70 CHGR_CSO_N
16 9 15 14
CHGR_BGATE CHGR_AMON CHGR_BMON =CHGR_ACOK
OUT OUT OUT
43 43
PGND
(AGND)
R7011
10.5K
1% 1/20W MF 201
C7050
0.47UF
10% 10V
CHGR_VCOMP_R
2
X5R
29
22
402
C7015
470PF
10% 16V X5R-X7R 201
353S2392
B
R7016
3.01K
1% 1/20W MF 201 1 1
XW7000
SM 2
(GND)
PPVBAT_G3H_CHGR_R CHGR_VNEG_R
3 2
PLACE_NEAR=U7000.29:1mm PLACE_NEAR=U7000.22:1mm
C7016
470PF
10% 16V X5R-X7R 201
(CHGR_CSO_P) (CHGR_CSO_N)
2.2 0
70 43 CHGR_CSO_R_P
5% 1/20W MF 201
R7052
70 43 CHGR_CSO_R_N
4 5% 1/20W MF 201
(PPVBAT_G3H_CHGR_R)
(PPVBAT_G3H_CHGR_R) (CHGR_BGATE)
C7042
0.1UF
10% 6.3V X5R 201
C7011
0.01UF
10% 10V X5R 201
C7000
1UF
10% 10V X5R 402-1
C7005
0.22UF
20% 25V X5R 603
C7026
1000PF
10% 16V X7R 201
* R7051 HAS 2.2OHM TO COMPENSATE UNVALANCED VOLTAGE

2
DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

C7012 1
0.01UF
10% 10V X5R 201
50
GND_CHGR_AGND
C7013 1
0.1UF
10% 25V X5R 402
1 C7014
1UF
10% 25V X5R 603-1
1 C7017
10UF
10% 25V X5R 805
K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT
(CHGR_AGATE)
C7025
0.22UF
10% 10V
CERM 402
1
CHGR_AGATE_DIV
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm
5A
5A 5 1
R7086
332K
1% 1/20W MF 201
R7021
10
2
CRITICAL
5% 1/20W MF 201
70 CHGR_CSI_R_P
R7020
0.020
0.5% 1W
R7022
10
1 5% 1/20W MF 201 2
70 CHGR_CSI_R_N
4 2
MF-LF 0612
PPDCIN_G3H_CHGR
CRITICAL
1
CRITICAL
1
PLACE_NEAR=Q7030.5:1.5mm
1
C7030
33UF-0.06OHM
20% 25V POLY-TANT CASE-D3L
C7031
33UF-0.06OHM
20% 25V POLY-TANT CASE-D3L
C7035
1UF
10% 25V
C7036
1UF
10% 25V
C7037
0.001UF
10% 50V X7R 402
C7021
0.1UF
10% 25V X5R 402 2
X5R 603-1
X5R 603-1
D
4
CRITICAL
Max Current = 8A
Q7030
RJK0332DPB-01
LFPAK-SM
f = 400 kHz S
CRITICAL CRITICAL
L7030
1 2 3
4.7UH-9.5A
1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE
DIDT=TRUE
F7040
7AMP-24V
2
TO SYSTEM
=PPBUS_G3H 1206-1
IHLP4040DZ-SM
PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 MM VOLTAGE=8.4V 5
CRITICAL
CRITICAL
1
CRITICAL
PLACE_NEAR=L7030.2:1.5mm
1
C7040
62UF
20% 11V ELEC CASE-B2
C7041
62UF
C7043
62UF
C7045
1000PF
10% 16V X7R 201
CRITICAL
Q7035
RJK0305DPB
LFPAK-HF
R7050
0.01
0.5% 1W MF 0612-3
CRITICAL
2 4
B
TO/FROM BATTERY
1 3
Q7055
SI7615DN
PWRPK-1212-8
PPVBAT_G3H_CONN
7 49
R7051
SYNC_MASTER=K6_MLB
PAGE TITLE
PBus Supply & Battery Charger

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

70 OF 110
SHEET
50 OF 73
=PPVIN_S5_P5VP3V3
PLACE_NEAR=Q7220.5.2:1.5mm
CRITICAL
56
P5VP3V3_VREG5
CRITICAL
1
C7240 1
62UF
20% 11V 2 ELEC CASE-B2
C7270
1000PF
C7241
1UF
10% 16V X5R 402
51 8
C7282 1
=PP5V_S3_REG
51
C7281
1UF
10% 16V X5R 402
C7283
1000PF
10% 2 16V X7R 201
P5VP3V3_VREG3
62UF
10% 2 16V X7R 201
C7200
1UF
10% 16V X5R 402
51
P5VP3V3_VREF2
C7201
0.22UF
10% 10V CERM 402
OMIT_TABLE C7203
1UF
10% 6.3V CERM 402
OMIT_TABLE C7205
10UF
20% 6.3V X5R 603
23
29
22
VREG5
VREG3
VREF2
V5SW
VIN
CRITICAL
D G 4
P5VS3_VBST_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

1
13
F=400KHZ
Q7220
RJK03E0DNS
=PP5V_S3_REG
HWSON-8
C7224
0.1UF
10% 25V X5R 402
R72451
0
5% 1/16W MF-LF 402 2
TPS51980
51 8
6 SKIPSEL1 19 SKIPSEL2 14 OCSEL P5VS3_VBST 31 VBST1 1 DRVH1 32 SW1 30 DRVL1 7 CSP1 8 CSN1
R7264
0
P3V3S5_VBST_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE
CRITICAL
C7264
0.1UF
10% 25V X5R 402
VIN/D1
U7201
QFN
EN 12 =P5V3V3_REG_EN VBST2 26 DRVH2 24 SW2 25 DRVL2 27 CSP2 18 CSN2 17 RF 3 VFB2 16 COMP2 15 P3V3S5_RF
IN
57
Vout = 5.0V 5.6A MAX OUTPUT

PLACE_NEAR=L7220.1:3mm
1 PCMC063T-SM
5% 1/16W MF-LF 1 402
Q7260
8
CRITICAL
=PP3V3_S5_REG
8 57
SIZ700DT POWERPAIR-6X3.7
GHS/G1 VSW/S1/D2
Vout = 3.3V 5.3A MAX OUTPUT F=400KHZ

2
CRITICAL
P3V3S5_VBST DIDT=TRUE P3V3S5_DRVH GATE_NODE=TRUE DIDT=TRUE P3V3S5_LL SWITCH_NODE=TRUE DIDT=TRUE P3V3S5_DRVL GATE_NODE=TRUE DIDT=TRUE P3V3S5_CSP2 P3V3S5_CSN2 MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2 MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2 MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2 MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2 mm mm mm mm mm mm mm mm
L7220
2.5UH-14A
2
3 2 1
CRITICAL
2
1
C7252
150UF
C7250
10UF
20% 10V X5R 805
XW7220
SM
20% 6.3V 2 POLY-TANT CASE-B2-SM
Q7225
HWSON-8
2 10% 16V X5R 402
51
P5VP3V3_VREG3
1 0
2
201
C7271
1000PF
RJK03E0DNS
S 3 2 1
5% 1/20W MF
PLACE_NEAR=L7220.1:3mm 10% 2 16V 2 X7R 201 XW7222 PLACE_NEAR=L7220.1.2:1.5mm SM
P5VS3_FUNC 11 MODE 9 VFB1 P5VS3_VFB1 P5VS3_COMP1 10 COMP1 P5VS3_EN_R 4 EN1 5 PGOOD1
XW7221 SM CRITICAL
5 D
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE P5VS3_DRVH GATE_NODE=TRUE P5VS3_LL DIDT=TRUE SWITCH_NODE=TRUE P5VS3_DRVL DIDT=TRUE GATE_NODE=TRUE P5VS3_CSP1 P5VS3_CSN1 NO STUFF DIDT=TRUE
CRITICAL L7260
2.5UH-14A
1 PCMC063T-SM
2 2
CRITICAL 150UF-0.018OHM-1.8A OMIT 1 1 C7290 10UF C7292

2 20% 6.3V X5R 603
GLS/G2 GND/S2
C7272
1000PF
XW7260
SM
XW7261
SM
C7218
0.1UF
R7248
C7288
0.1UF
1 2 10% 16V X5R 402
PLACE_NEAR=L7260.1:3mm1 1
20% 6.3V 2 TANT CASE-B2-SM
10% 2 16V X7R 201
P3V3S5_VFB2 P3V3S5_COMP2
R7247
1.87K 1 2
1% 1/20W MF 201
2 1
EN2 21 P3V3S5_EN_R PGOOD2 20 GND 28 THRM_PAD 33

1
R7246
1
1
P5VS3_VFB1-R
R7236 1 NO STUFF R7237 6.04K

1% 1/20W MF 201 2
20K
R7256
3.16K
P5VS3_COMP1_R
1% 1/20W MF 201
XW7200
SM 1 2
R7249
0
5% 1/20W MF 201
353S2678
R7238 1 NO STUFF R7239 6.04K

1% 1/20W MF 201 2
1.87K2
1% 1/20W MF 201
XW7262
SM 1
R7206
249K
1% 1/20W MF 201 2
20K
1% 1/20W MF 201
R7216
3.16K
1
PLACE_NEAR=L7260.2:3mm P3V3S5_VFB2_R
R7220
41.2K
C7236 1
0.01UF
10% 10V X5R 201
C7237 1
100PF
10% 25V X7R-CERM 201
P3V3S5_COMP2_R
1
1% 1/20W MF 2 201
1% 1/20W MF 201 2
C7238
0.01UF
10% 10V X5R 201
C7239
100PF
10% 25V X7R-CERM 201
1% 1/20W MF 2 201
R7260
23.2K
1% 1/20W MF
P3V3S5_CSP2_R
2
2 201
P5VS3_CSP1_R
51
B
1
P5VP3V3_VREF2
51
P5VP3V3_VREF2
1
B
R7261
10K
1% 1/20W MF
R7221
10K
1% 1/20W MF
57
OUT OUT
P5VS3_PGOOD P3V3S5_PGOOD GND_P5VP3V3_SGND MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0V
2 201
57
2 201
R7251
0
5% 1/16W MF-LF 402
R7252
0
5% 1/16W MF-LF
2 402
57
IN
=P5VS3_EN
57
IN
=P3V3S5_EN
SYNC_MASTER=K16_MLB
PAGE TITLE
5V / 3.3V Power Supply

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

72 OF 110
SHEET
51 OF 73
8 8
=PPVIN_S3_DDRREG =PPVIN_S0_DDRREG_LDO
OMIT_TABLE
C7355
10UF
CRITICAL
CRITICAL
20% 6.3V 2 X5R 603
C7330 1
62UF
C7331 1
C7332
1UF
C7333
1000PF
62UF
10% 16V 2 X5R 402
10% 2 16V X7R 201
=PP5V_S3_DDRREG
R7305
1
4.7
PP5V_S3_DDRREG_V5FILT
5% 1/16W MF-LF 402
R73101
12K
14 23
1% 1/20W MF 201 2
=PP3V3_S3_PDCISENS
R7380
100K
4.7UF
C
57 57
5% 1/20W MF 201 2
IN IN OUT
33 8
10% 10V 2 X5R 805
10% 10V 2 X5R 402-1
1UF
15
C7300
C7305
CRITICAL
Q7330
(DDRREG_DRVH)
4
SIS426DN
G S
1 2 3 PWRPK-12128
V5IN 6 COMP
V5FILT
VLDOIN VDDQSNS 8
DDRREG_VDDQSNS
CRITICAL
10 S3 VTT Enable 11 S5 VDDQ/VTTREF Enable 13 PGOOD VDDQ PGOOD
CRITICAL 0.82UH-20%-13A-0.0067OHM 1 2 PPDDR_S3_REG_R

IHLP2525CZ-SM
=DDRVTT_EN =DDRREG_EN DDRREG_PGOOD 10mA max load Vout = VDDQSNS/2
MODE 4 VBST 22 DRVH 21 LL 20 DRVL 19
C7325
0.1UF DDRREG_VBST
DIDT=TRUE
L7330
C
U7300
QFN
(DDRREG_VBST)
1 10% 16V X5R 402
=PPVTT_S3_DDR_BUF =PPVTT_S0_DDR_LDO
TPS51116
5 VTTREF 24 VTT SYM (2 OF 2)
DDRREG_DRVH
CRITICAL CRITICAL
DDRREG_LL
SWITCH_NODE=TRUE DIDT=TRUE
(DDRREG_LL)
R7350 2
0.002
1% 1/4W MF-LF 1206
ISNS_1V5_S3_P ISNS_1V5_S3_N
XW7360 SM
1 2
Vout = VTTREF DDRREG_VTTSNS

NC NC
2 VTTSNS 7 NC0 12 NC1 VTTGND 1 THRM_PAD GND 25 3
OUT OUT
42 71
Q7335
4
DDRREG_DRVL
(DDRREG_DRVL)
SIS426DN
G S
1 2 3 PWRPK-12128
42 71
1 3
=PPDDR_S3_REG CRITICAL
CS 16 VDDQSET 9 PGND CS_GND 18 17

33
DDRREG_CS DDRREG_FB
OMIT_TABLE
OMIT_TABLE
1
PLACE_NEAR=R7350.1:1.5MM
C7360
22UF
C7361
22UF
C7346 1
1000PF
10% 16V X7R 201
C7341 1
330UF
20% 2.5V 2 TANT CASE-B2-SM
20% 6.3V X5R-CERM-1 2 603
20% 2 6.3V X5R-CERM-1 603
XW7335 SM
DDRREG_CSGND (DDRREG_CSGND)
1 2
Vout = 1.501V / 1.352V 13A Max Output f = 400 kHz

OMIT_TABLE
1
XW7300 SM
PLACE_NEAR=U7300.3:1 mm
1 2
MIN_LINE_WIDTH=0.1 mm MIN_NECK_WIDTH=0.1 mm PLACE_NEAR=U7300.25:1 mm
CRITICAL
1
PLACE_NEAR=L7330.2:1 MM
2
C7340
330UF
C7345
10UF
20% 2 2.5V TANT CASE-B2-SM
20% 2 6.3V X5R 603
XW7345 SM
1
LVDDR3:YES
B
C7350
33000PF
1
C7320
1000PF (DDRREG_VDDQSNS) (DDRREG_FB) GND_DDRREG_SGND
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0V MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm
1 1
R7320
15K
10% 16V X7R 2 201
1% 1/20W MF 2 201
10% 6.3V X5R 2 201
<Ra>
LVDDR3:YES
(GND_DDRREG_SGND)
R7321
18.7K
Vout = 0.75V * (1 + Ra / Rb)
1% 1/20W MF 2 201
<Rb>
Use LVDDR3:YES for fixed 1.35V operation or LVDDR3:NO for fixed 1.5V operation.
PART NUMBER 114S0331
QTY 1
DESCRIPTION
RES,15K,1%,1/16W,MF-LF,0402
REFERENCE DES R7321
CRITICAL
BOM OPTION LVDDR3:NO
SYNC_MASTER=K16_MLB
PAGE TITLE
1.5V/1.35V LVDDR3 Supply

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

73 OF 110
SHEET
52 OF 73
IMVP6 CPU VCORE REGULATOR

D D
8
=PP3V3_S0_IMVP
8
=PPVIN_S5_CPU_IMVP
CRITICAL
1
8
CRITICAL
1
CRITICAL
1
C7458
62UF
C7459
62UF
C7456
62UF
C7457
1UF
10% 16V X5R 402
C7453
1UF
10% 16V X5R 402
C7454
1000PF
10% 16V X7R 201
=PP5V_S0_CPU_IMVP
53
53
PP5V_S0_IMVP6_V5FILT
VOLTAGE=5V
1
IMVP6_VBST_RC
DIDT=TRUE
CRITICAL
C7412
4.7UF
1
10% 6.3V X5R-CERM 603
Q7400 IRF6710
1
20% 2 11V ELEC CASE-B2
R74101
0
5% 1/20W MF 201
R74201
0
5% 1/20W MF 201
R7411
0
5% 1/20W MF 201
53
C7413
2.2UF
20% 6.3V CERM1 603
1 2 2
R7415
0
5% 1/16W MF-LF 402
C7414
1UF
10% 16V X5R-X7R 603-2
S1
D
1 2 5
NC NC
PWM FREQ. = 400KHZ MAX CURRENT = 18A

CRITICAL
2 4
G S
2 2
VOLTAGE=1.7V
CRITICAL
21
PP1V7_S0_IMVP6_VREF
1
R74141
3.01K
1% 1/20W MF 201
C7415
100PF
5% 25V CERM 201
53
V5IN
DIDT=TRUE GATE_NODE=TRUE DIDT=TRUE
U7400
TPS51982RHB
32 28 6 5 1
R7480
0.001
1% 1W MF-1 0612 2
CRITICAL
2 2
QFN
DROOP TONSEL VSNS GNDSNS VREF VID0 VID1 VID2 VID3 VID4 VID5 VID6 ISLEW CSP CSN GND
0.36UH-30A-1.05MOHM
(CPUIMVP_LL)
DIDT=TRUE SWITCH_NODE=TRUE
1 PCMC104T-SM
L7400
IMVP6_DROOP
V5FILT 31 VBST DRVH LL DRVL PGOOD CLK_EN* VR_ON DPRSLPVR DPRSTP* PWRMON TRIPSEL OSRSEL VR_TT* THERM 18 53 IMVP6_VBST 17 53 IMVP6_DRVH 19 53 IMVP6_LL 20 53 IMVP6_DRVL 22 24 25 23
9
PPVCORE_S0_CPU_REG_R
VOLTAGE=1.25V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 MM
IMVP6_TONSEL
2 4
1 3
=PPVCORE_S0_CPU_REG
8
NCNC
1 2 6 7
PLACE_NEAR=R7480.1:1.5MM
65 12 11 65 12 11 65 12 11
IN IN IN IN IN IN IN
R7422
2.0K
5% 1/20W MF 201
NO STUFF
1R7421
65 12 11 65 12 11 65 12 11 65 12 11
10K
5% 1/20W MF 201
CPU_VID<0> CPU_VID<1> CPU_VID<2> CPU_VID<3> CPU_VID<4> CPU_VID<5> CPU_VID<6>

53
16 15 14 13 12 11 10 30 4 3
VR_PWRGOOD_DELAY
OUT
25
D
38 R7453
NC IMVP_VR_ON IMVP6_DPRSLPVR CPU_DPRSTP_L
Q7451
IN 1 IN 5
CRITICAL
C7455
1000PF
10% 16V X7R 201
G S
3 4
IRF6795
DIRECTFET-MX
499
1/20W
1% 201 MF
DIDT=TRUE GATE_NODE=TRUE
2 2
IMVP6_ISLEW
71
PGND
IMVP6_CS_P 71 IMVP6_CS_N
26 27 29 8 7
IMVP6_PMON
OUT
43
PM_DPRSLPVR
IN
14 65
NC
NO STUFF
C7450
100PF
5% 50V CERM 402
33
R7451 R7452
470 470
1 1
2
5% 1/20W 1/20W MF MF 201
71
IMVP6_CS_R_P IMVP6_CS_R_N IMVP6_VSEN_P IMVP6_VSEN_N
2
5% 201
71
R7491
1
0
5% 1/20W MF 201
CPU_VCCSENSE_P
11 65
C7460
0.22UF
10% 10V CERM 402
53
65
IMVP6_THERM
1
65
R7492
1
R74251
124K
1% 1/20W MF 201
0
5% 1/20W MF 201
R7426
150K
5% 1/20W MF 201
53
C7452
100PF
10% 25V X7R-CERM 201
1 1 2 2
CPU_VCCSENSE_N
11 65
C7451
100PF
10% 25V X7R-CERM 201
2 2
GND_IMVP6_SGND
VOLTAGE=0V
XW7400
SM
OCP = 21.5MV / R7480 + 3.1A VPMON = 90 X R7480 X VO X IO 18A @ 1V = 1.62V LOAD LINE = R7480 X 6 / (500U X R7414)
IMVP6_TRIPSEL IMVP6_OSRSEL
MIN_LINE_WIDTH
MIN_NECK_WIDTH
53
GND_IMVP6_SGND IMVP6_DROOP
0.50 MM
0.20 MM
53
0.25 MM
0.20 MM
A
MIN_LINE_WIDTH
53 53 53 53 53
SYNC_MASTER=POWER
MIN_NECK_WIDTH 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM
I787
53 53 53 53
IMVP6_LL IMVP6_VBST IMVP6_DRVH IMVP6_DRVL IMVP6_VBST_RC
1.5 MM 0.25 MM 1.5 MM 1.5 MM 1.5 MM
IMVP6_THERM IMVP6_ISLEW PP1V7_S0_IMVP6_VREF PP5V_S0_IMVP6_V5FILT
0.25 MM 0.25 MM 0.25 MM 0.25 MM
0.20 MM 0.20 MM 0.20 MM 0.20 MM
PAGE TITLE
IMVP6 CPU VCore Regulator

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

74 OF 110
SHEET
53 OF 73
D
PP5V_S0_MCPREG_VDD
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V
=PPVIN_S0_MCPCORE =PP5V_S0_MCPREG CRITICAL
D
CRITICAL MCPCORES0_BOOT_R
1
R7560
1
CRITICAL
1
2.2
5% 1/10W MF-LF 603
C7540
62UF
1 20% 11V ELEC CASE-B2
C7541
62UF
C7561
1UF
10% 16V X5R 402
PLACE_NEAR=Q7560.5:1.5mm 1
C7563
1000PF
10% 16V X7R 201
R7561
1K
5% 1/20W MF 201
1 1 16
C7562
1UF
10% 16V X5R 402
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE 2
R7565
0
5% 1/10W MF-LF 603
1UF
2 2 10% 16V X5R 402
22
C7550
C7564
0.22UF
5% 10V CERM-X7R 603
D
2
VDD
PVCC
CRITICAL
U7500
ISL9563B
MCPCORES0_RBIAS MCPCORES0_SOFT
1 2
Q7560
4
RBIAS SOFT IMON PGOOD VID0 VID1 VID2 VID3

NC
QFN
VIN UGATE BOOT PHASE
14
(MCPCORES0_UGATE)
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
SIS426DN
G S
1 2 3 PWRPK-12128
CRITICAL
18 17 19
MCPCORES0_UGATE MCPCORES0_BOOT
DIDT=TRUE
CRITICAL
R7525
0.001
2
43
OUT OUT IN IN IN IN
MCPCORES0_IMON MCPCORES0_PGOOD MCP_VID<0> MCP_VID<1> MCP_VID<2> MCP_VID<3>
R7593 R7590 R7591 R7592 R7594
NOSTUFF
2
L7560
0.47UH-20%-0.0021OHM-26A
1
MCPCORES0_IMON_R
5% 1/20W MF 201
28 31
57 19 19 19 19
MCPCORES0_PHASE
SWITCH_NODE=TRUE DIDT=TRUE
PPMCPCORE_S0_R
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1V 1 3
1% 1W MF-1 0612
=PPMCPCORE_S0_REG
2 4 1
8 54
(MCPCORES0_PHASE)
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
0 0 0 0
PCMB103T-SM
1 1 1 1
5%
2 2 2
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
201 201 201 201
5% 5% 5%
MCP_VID0_REG MCP_VID1_REG MCP_VID2_REG MCP_VID3_REG
24 25 26 27
CRITICAL
CRITICAL
D CRITICAL
C7566
10UF
20% 4V X5R 603
C7565
270UF
20% 2V TANT CASE-B4-SM
MAX CURRENT: 15A (Q7560 Limit) f = 300 kHz
D CRITICAL
PLACE_NEAR=R7525.1:1.5MM 2
NC
57
23 29
Q7565
4
IN
=MCPCORES0_EN =PPMCPCORE_S0_REG 54 8
1
MCPCORES0_FDE
30 32
R7563
100
MCPCORES0_VSEN MCPCORES0_RTN MCPCORES0_VW
8 9 4
C
R7566
71 22
VR_ON AF_EN FDE VSEN RTN VW
SIS426DN
G S
1 2 3 1 2 3 PWRPK-12128 4
Q7566
SIS426DN
G S
PWRPK-12128
C7569
1000PF
10% 16V 201
CRITICAL
LGATE
21
MCPCORES0_LGATE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE
2 X7R
C7567
10UF
20% 4V X5R 603
C7568
270UF
1% 1/20W MF 2 201
IN
MCPCORES0_VSEN_P
20
1% 1/20W MF 201
(MCPCORES0_VSEN) MCPCORES0_COMP
1 5
VO COMP FB VDIFF PGND

20
1
12 3
MCPCORES0_VO MCPCORES0_OCSET MCPCORES0_ISP MCPCORES0_ISN MCPCORES0_ICOMP
(MCPCORES0_VO)
OCSET
ISP ISN ICOMP
R7569
9.76K
1 2 1% 1/20W MF 201
C7570
1000PF
10% 16V X7R 201
MCPCORES0_FB MCPCORES0_VDIFF
6 7
13 11 10
R7568
71 22
R7573
10K
IN
MCPCORES0_VSEN_N
20
1% 1/20W MF 201
C7573
47PF
5% 25V NP0-C0G 201
(MCPCORES0_RTN)
VSS
15
THRM_PAD
33
C7577
1000PF
10% 16V X7R 201
1
1% 1/20W MF 2 201
R7500
100
1 2 1% 1/16W MF-LF 402
9
R7571
100
R7572
147K
1 1
C7576
0.1UF
2
C7578
1000PF
10% 16V X7R 201
MCPCORES0_ISP_R
(MCPCORES0_ISN)
1
1% 1/20W MF 2 201
1% 1/20W MF 201 2
10% 16V X7R-CERM 402
R7575
22.1K
C7575
47PF
5% 25V NP0-C0G 201
(MCPCORES0_VW)
1
XW7561
SM
1% 1/20W MF 2 201
GND_MCPCORES0_AGND
(MCPCORES0_ICOMP)
C7579
0.001UF
R7576
6.98K
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V
C7580
560PF
1 10% 50V CERM 402 2
10% 50V X7R 402
1% 1/20W MF 2 201
R7577
150K
1 1% 1/20W MF 201 2
C7581
100PF
1 5% 50V CERM 402 2
Vimon = 31 * Io * R7525 * (1 + R7575/R7573)

(MCPCORES0_COMP)
MCPCORES0_COMP_C
OCP = R7569 X 10UA / ( R7525 X (1 + R7575 / R7573) )

VID<3:0> VOLTAGE 0.9750V 0.9625V 0.9500V 0.9375V 0.9250V 0.9125V 0.9000V 0.8875V 0.8750V 0.8625V 0.8500V 0.8375V 0.8250V 0.8125V 0.8000V 0.7875V
SYNC_MASTER=K6_MLB
PAGE TITLE
(MCPCORES0_FB)
1100
R7578
1
C7582
4700PF MCPCORES0_VDIF_C
1 10% 100V CERM 402 2
200
1% 1/20W MF 201
1101
(MCPCORES0_VDIFF)
1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011
R7579
1
3.01K
1% 1/20W MF 201
MCP VCore Regulator

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

K6 NOTES : XOR AND INVERTER IS REMOVED, CANNOT SYNC THIS PAGE FROM T27
75 OF 110
SHEET
54 OF 73
8 8
=PPVIN_S0_CPUVTTS0 =PP5V_S0_CPUVTTS0 CRITICAL CRITICAL
Place XW7610, XW7611 at desired location for remote sensing.

55 8
R76011
2.2
5% 1/10W MF-LF 603 2
C7601
10UF CPUVTTS0_VBST
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE 1
C7620 1
20% 11V 2 ELEC CASE-B2 5 D 4 G
=PPCPUVTT_S0_REG
XW7610 SM
1 1 SM 2 2
71
20% 10V 2 X5R 603
62UF
C7621 1
C7622
1000PF
62UF
CPU_VTTSENSE_P CPU_VTTSENSE_N
PP5V_S0_CPUVTTS0_VCC
13 14
C7630
1UF
10% 2 16V X7R 201 PLACE_NEAR=Q7630.1:1.5mm
71
10% 16V 2 X5R 402
CRITICAL
XW7611
VCC
PVCC
CPUVTTS0_DRVH
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE BOOT 12 UGATE 11 PHASE 10 LGATE 15
Q7630
RJK03E0DNS
HWSON-8
R76041
3.01K
1% 1/20W MF 201 2
R7644
3.01K
57
U7600
ISL95870
IN
1% 1/20W MF 1 201
S 1 2 3
CRITICAL CRITICAL 0.82UH-20%-13A-0.0067OHM 1 2 PPCPUVTT_S0_REG_R

IHLP2525CZ-SM
=CPUVTTS0_EN CPUVTTS0_FB CPUVTTS0_SREF CPUVTTS0_VO CPUVTTS0_OCSET
3 6 4 8 7 9 2 5
EN FB SREF VO OCSET
UTQFN
R7640
0.001
1% 1W MF-1 0612
<Ra>
CRITICAL
L7630
C
57
=PPCPUVTT_S0_REG
1 3
8 55
CPUVTTS0_LL
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE 5 D
2 4
CRITICAL
CRITICAL
C7623 1
1000PF
10% 16V 2 X7R 201
OUT
CPUVTTS0_PGOOD CPUVTTS0_RTN
PGOOD
CPUVTTS0_DRVL
RTN FSEL
Q7635
RJK03E0DNS
HWSON-8
C7649 1 270UF 20% 2V 2 TANT

CASE-B4-SM
Vout = 1.05V 11.5A Max Output f = 300 kHz

OMIT_TABLE
1
R7605
2.74K
R7645
2.74K
CPUVTTS0_FSEL
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE GND PGND

16 1
CRITICAL
1 2
C7648
270UF
C7647
10UF
20% 603
S 1 2 3
1% 1/20W MF 201 2
1% 1/20W MF 2 201
C7602
2.2UF
R7603
0
2 6.3V X5R
<Rb>
C7604
1000PF
1 1
10% 16V X5R 2 603
5% 1/20W MF 2 201
71
C7605
1000PF
C7603
0.047UF
CPUVTTS0_CS_P CPUVTTS0_CS_N
10% 16V 2 X7R 201
10% 2 16V X7R 201
10% 2 16V X7R 402
XW7600 SM
CPUVTTS0_AGND
1 2
R7641
1.78K
71
1% 1/20W MF 201 2
C7640
1000PF
2 1 1 5% 25V NP0-C0G 402
R7642
1.78K
(CPUVTTS0_OCSET) (CPUVTTS0_VO)
1% 1/20W MF 2 201
OCP = R7641 x 8.5uA / R7640 Vout = 0.5V * (1 + Ra / Rb)
SYNC_MASTER=K16_MLB
PAGE TITLE
CPUVTT (1.05V) Power Supply

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

76 OF 110
SHEET
55 OF 73
1.5V S0 Regulator
8
=PP3V3_S0_P1V5S0
1
PLACE_NEAR=U7710.1:1.5mm PLACE_NEAR=U7710.1:1.5mm
C7710
20% CERM 6.3V 805
C7712
1000PF
10% 201
1 IHLP1616BZ-SM
D
1 VIN
22UF
2 16V X7R
CRITICAL 2.2UH-3.25A
D
=PP1V5_S0_REG
8
L7710
P1V5S0_SW
2 1
U7710
ISL8009B
DFN
57
C7711 1
5% 25V NP0-C0G 2 201
R7711
100K
47PF
IN OUT
P1V5S0_EN P1V5S0_PGOOD
2 EN 3 POR
CRITICAL
LX 8 VFB 6 RSI 5
1% 1/20W MF 2 201
Vout = 1.508V MAX CURRENT = 1.5A f = 1.6MHZ

1
57
P1V5S0_FB
<Ra>
C7715
22UF
1
4 SKIP GND 7
C7716
1000PF
10% 201
THRM_PAD 9
R7712
113K
1% 1/20W MF 2 201
20% 6.3V 2 CERM 805
2 16V X7R
<Rb>
Vout = 0.8V * (1 + Ra / Rb)

IPD_5V:S5_INT
8
1.05V S0 MCP PLL LDO

=PP3V3_S0_MCP_PLL_VLDO MCPPLL_R:LDO MCPPLL_R:REG
8
=PP1V05_S0_MCP_PLL_UF_R
R7745
1
5.0V S5 IPD LDO

C
8
R7761
1
R77431
8
P5VP3V3_VREG5
5% 1/16W MF-LF 402
=PP1V5_S0_MCP_PLL_VLDO MCPPLL_R:LDO
5% 1/16W MF-LF 402 2
100
5% 1/16W MF-LF 402
MCPPLL_R:LDO PP3V3_S0_MCP_PLL_LDO_BIAS
4 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
=PP1V05_S0_MCP_PLL_OR
IPD_5V:S3 =PP5V_S3_TPAD
R77501
0
5% 1/16W MF-LF 402 2
R7744
CRITICAL MCPPLL_LDO
OUT0 OUT1 9 10 BIAS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
R7760
1
PP1V05_S0_MCP_PLL_REG MCPPLL_LDO
=PPBUS_5V_S5
1 IN
57
U7760
MIC5235-2.5V
SOT23-5
5% 1/16W MF-LF 402
PP1V5_S0_MCPPLLLDO PP5V_S5_LDO
46
OUT 5 NC 4 GND 2
VOLTAGE=5V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20mm
MCPPLL_LDO
C7741 1
1UF
10% 6.3V 2 CERM 402
1 2
R7746
1.37K
5% 1/16W MF-LF 402
IN0 IN1
U7740
5 EN SON SS PG FB 8
OMIT_TABLE
IN
P5V_S5_EN IPD_5V:S5_EXT
3 EN
IPD_5V:S5_EXT
NC
1
MCPPLLLDO_FB
<Ra>
R7747
4.42K
1% 1/20W MF 201 2
Vout = 1.05V Max Current = 0.5A
MCPPLL_LDO
1
C7742
4.7UF
C7760
2.2UF
C7761 1
1UF
10% 16V 2 X5R 402
20% 10V 2 X5R-CERM 402
Vout = 5.0V MAX CURRENT = 0.016A
TPS74701
MCPPLL_LDO MCPPLLLDO_SS MCPPLL_LDO
1 1
MCPPLL_LDO
3
1 1% 1/20W MF 201 2
20% 2 4V X5R 402
C7740
1UF
C7743
2.2NF
GND THRML_PAD 11 6
10% 6.3V 2 CERM 402
10% 2 10V X5R 201
<Rb>
Vout = 0.8V * (1 + Ra / Rb)

MCPPLL_LDO
PART NUMBER 353S3034
QTY 1
DESCRIPTION
IC,LDO,MIC5235,5V,1%,150MA,SOT23-5
REFERENCE DES
U7760
CRITICAL
BOM OPTION IPD_5V:S5_EXT
R7748
BOMOPTIONs:
MCPPLLLDO_PGOOD_R
MCPPLLLDO_PGOOD
OUT
57
MCPPLL_R:LDO - 1.05V S0 USED FOR MCP PLL LDO POWER. MCPPLL_LDO - STUFFS U7740 AND RELATED CIRCUITRY. TO USE U7740, MCPPLL_R:LDO AND MCPPLL_LDO MUST BE ACTIVE. TO USE 1.05V S0, MCPPLL_R:REG MUST BE ACTIVE, MCPPLL_LDO CAN BE ACTIVE, MCPPLL_R:LDO MUST BE INACTIVE.
5% 1/20W MF 201
MCP 0.9V S5 (AUXC) Switcher

57 8
=PP3V3_S5_P0V9S5
PLACE_NEAR=U7750.1:1.5mm PLACE_NEAR=U7750.1:1.5mm CRITICAL
C7750
22UF
6.3V 20% CERM 805
1 C7752
1000PF
16V 2 X7R 201 10%
CRITICAL 2.2UH-3.25A
L7750
=PP0V9_S5_REG
1 VIN
P0V9S5_SW
1 IHLP1616BZ-SM
2 1
U7750
ISL8009B DFN
57
C7751
47PF
R7751
2.55K
1
IN OUT
=P0V9S5_EN P0V9S5_PGOOD
2 EN
3 POR
CRITICAL
LX 8 VFB 6 RSI 5
5% 25V NP0-C0G 2 201
1% 1/20W MF 2 201
Vout = 0.902V MAX CURRENT = 1.5A f = 1.6MHZ

CRITICAL
57
P0V9S5_FB
<Ra>
R7752
20K
C7755
22UF
1 C7756
10% 2 16V X7R 201
4 SKIP
GND 7
THRM_PAD 9
20% 2 6.3V CERM 805
1000PF
SYNC_MASTER=K16_MLB
PAGE TITLE
1% 1/20W MF 2 201
Misc Power Supplies

DRAWING NUMBER SIZE
<Rb>
R
Apple Inc.
051-8379
REVISION
Vout = 0.8V * (1 + Ra / Rb)
4.4.0
BRANCH PAGE
77 OF 110
SHEET
56 OF 73
4
8
3
=PP3V3_S0_PWRCTL
2
10K State Run (S0) Sleep (S3) Soft-Off (S5) SMC_PM_G2_ENABLE 1 1 1 0
1
PM_SLP_S4_L 1 1 0 0 PM_SLP_S3_L 1 0 0 0
S5 Rail Enables & PGOOD

8
S0 Rail PGOOD Circuitry

R7840
51
R78201
5% 1/20W MF 201 2
Power Control Signals
=PP3V42_G3H_PWRCTL U7750 EN tied to VIN

IN
P5VS3_PGOOD
C7840 1
0.1UF
38 7
CRITICAL
=PP3V3_S5_P0V9S5 =P0V9S5_EN
OUT
8 56
IN
SMC_PM_G2_EN
MAKE_BASE=TRUE
10% 6.3V X5R 2 201
VDD
5% 1/20W MF 201
51
R7841
1
U7840
SLG4AP012
TDFN 2 IN_A
(IPD)
56
IN
P3V3S5_PGOOD
Battery Off (G3Hot)
51
OUT
=P5V3V3_REG_EN
1
S0 Rail PGOOD (ISL Version)

Internal pull-ups 100K +/- 20% P3V3S5_EN_L OUT 57 P3V3S5_EN
MAKE_BASE=TRUE
1
R7846
0
71 8 7
OUT_A* 4
(OD,IPU)
PP5V_S0 8 7 S0PGOOD_ISL
51
R7842
56
IN
P1V5S0_PGOOD
5% 1/20W MF 201
D
2
5% 1/16W MF-LF 2 402

56
PP3V3_S5 Threshold: ?? DLY > 10 ms S5PGOOD_DLY

1
6 IN_B 2:1 + 1.3V 7 DLY_1C DLY
OUT_A 3
(OD,IPU)
=P3V3S5_EN NO STUFF
OUT
R78701
10K
1% 1/16W MF-LF 402 2
54
5% 1/20W MF 201
IN
R7843
1
C7801
33000PF
MCPCORES0_PGOOD
OUT
P5V_S5_EN
1
NO STUFF
OUT_B 8
(OD,IPU)
C7846
0.47UF
10% 2 6.3V X5R 201
PP3V3_S0_VMON S0PGOOD_ISL
55
R7844
IN
CPUVTTS0_PGOOD
5% 1/20W MF 201
10% 2 10V X5R 402
C7841
220PF
GND 5
THRM PAD 9
10% 2 25V X7R-CERM 201
R7871
20.0K
S0PGOOD_ISL
1% 1/16W MF-LF 402 2
C7870
0.1uF
CRITICAL S0PGOOD_ISL
56
5% 1/20W MF 201
R7845
1
20% 10V CERM 2 402
VDD
VDDA
IN
MCPPLLLDO_PGOOD
U7870
3 V2MON 5 V3MON 6 V4MON
56
IN
P0V9S5_PGOOD
RSMRST_PWRGD
MAKE_BASE=TRUE
71 57 8 7
OUT
38 71 57 8 7 57 8 7
PP3V3_S0 PP1V5_S0 PP1V05_S0 Worst-Case Thresholds: VDD: 2.9140V V2MON: 3.000V V3MON: 0.610V V4MON: 0.610V
ISL88042IRTJJZ TDFN (IPU)

MR*
5% 1/20W MF 201
1 8
S0PGOOD_ISL
NC
R7872
1
RST*
S0PGOOD_RST_L
10
ALL_SYS_PWRGD
MAKE_BASE=TRUE
OUT
25 38 49
S3 Rail Enables
R7813
57 38 19 7
GND 4
THRM_PAD 9
353S2718
5% 1/20W MF 201
IN
PM_SLP_S4_L
P5VS3_EN
MAKE_BASE=TRUE
=P5VS3_EN
OUT
51
5% 1/20W MF 201
NO STUFF
1
C7813
10% 2 10V CERM 402
0.068UF
S0 Rail PGOOD (BJT Version)

8
=PP3V3_S5_VMON S0PGOOD_BJT
R7812
1
71 57 8 7
PP3V3_S0 S0PGOOD_BJT
1
R78261
150K
P3V3S3_EN
MAKE_BASE=TRUE
=P3V3S3_EN
OUT
58
R7821
15K
5% 1/20W MF 201
NO STUFF
1
C7812
0.47UF Need to re-characterize for power sequencing!
1% 1/20W MF 2 201
1% 1/20W MF 201 2
S0PGOOD_BJT
R7828
S0PGOOD_BJT_L
6 4
S0PGOOD_BJT
10% 2 10V X5R 402
R7823
1
S0PGOOD_BJT
10
VMON_3V3_DIV
1K
VMON_Q2_BASE
R7811
1
5% 1/20W MF 201
5% 1/20W MF 201
Q1 5 Q2 8 7 Q3
ISL6259 Frequency Select

=PP3V42_G3H_CHGR 50 8 VFRQ:SLPS4&VFRQ:SLPS3&VFRQ:HIGH
5.1K 2
5% 1/20W MF 201
DDRREG_EN
MAKE_BASE=TRUE
1
=DDRREG_EN =USB_PWR_EN
OUT OUT
52
S0PGOOD_BJT
R7810
100K
7 36 37 71 57 8 7
R7824
PP1V5_S0
1
C7810
0.47UF
1K
NC
CRITICAL S0PGOOD_BJT
VMON_Q3_BASE
NC
Q7820
ASMCC0179
DFN2015H4-8
R78611
10K
5% 1/20W MF 201 2
5% 1/20W MF 201 2
10% 2 10V X5R 402
Need to re-characterize for power sequencing!
5% 1/20W MF 201
2 1 Q4
S0PGOOD_BJT
VFRQ:SLPS4&VFRQ:SLPS3
CHGR_VFRQ
D 3
OUT
50
R7825
57 8 7
PP1V05_S0 S0PGOOD_BJT
1
1K
Q7860
VMON_Q4_BASE Worst-Case Thresholds: Q2: 0.XXXV Q3: 0.640V Q4: 0.660V 3.3V w/Divider: 2.345V 353S2809 VMON_EMITTER S0PGOOD_BJT
57 38 19 7
VFRQ:SLPS4
SSM3K15FV
SOD-VESM-HF
VFRQ:LOW
1
B
19
ENET Rail Enables

IN
R7822
7.15K
5% 1/20W MF 201
R7864
PM_SLP_S4_L
1
R7860
10K
2 1 G
PM_SLP_RMGT_L
MAKE_BASE=TRUE
=P3V3ENET_EN =P0V9ENET_EN
OUT OUT
58 58
1% 1/20W MF 2 201
R78271
100
5% 1/20W MF 201 2
57 39 38 19 7
5% 1/20W MF 201
S 2
5% 1/20W MF 2 201
VFRQ:SLPS3
CHGR_VFRQ_GATE
R7863
PM_SLP_S3_L
1
S0 Rail Enables
R7859
57 39 38 19 7
5% 1/20W MF 201
IN
PM_SLP_S3_L
100
1
2
PM_SLP_S3_R_L
MAKE_BASE=TRUE
=P5VS0_EN =PBUSVSENS_EN
OUT OUT
58
WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal. NOTE: "AC" term valid only when Q7891 is stuffed
5% 1/20W MF 201
R7881
33K
R7880
22K
R7882
15K
R7884
5.1K
42
R78791
100K
5% 1/20W MF 201 2
5% 1/20W MF 1 201
5% 1/20W MF 1 201
5% 1/20W MF 1 201
5% 1/20W MF 1 201
P3V3S0_EN
MAKE_BASE=TRUE
56
=P3V3S0_EN =P1V5S0_EN =MCPCORES0_EN =CPUVTTS0_EN
OUT OUT OUT OUT
58
P1V5S0_EN
MAKE_BASE=TRUE
PM_WLAN_EN_L
54
OUT
34
Pull-up is with power FET.
MCPCORES0_EN
MAKE_BASE=TRUE
Q7890
SSM6N37FEAPE
SOT563
D 6
CPUVTTS0_EN
MAKE_BASE=TRUE
1
55
C7881
0.47UF
C7880
0.47UF
C7882
0.47UF
C7884
0.47UF
34 19
51 8
=PP3V3_S5_REG
NO STUFF
1
10% 10V 2 X5R 402
10% 10V 2 X5R 402
10% 2 10V X5R 402
10% 10V 2 X5R 402
2 G
IN
S 1
R7899
0
5% 1/10W MF-LF
AP_PWR_EN WLAN_PCTL:HW
AC_OR_S0_L WLAN_PCTL:SW
D 3
1
SYNC_MASTER=K16_MLB
PAGE TITLE
Q7891
SSM6N37FEAPE
SOT563
R7891
0
6 D
WLAN_PCTL:HW
Q7891
SSM6N37FEAPE
SOT563
P3V3_BLEED
2 603
Power Sequencing
DRAWING NUMBER SIZE
VTT Rail Enable

21 19
VTT rail must ramp up in about the same time as MEMVDD rail (Q2300). =DDRVTT_EN
39 38 19
5% 1/16W MF-LF 2 402
Q7890
SSM6N37FEAPE
SOT563
D 3
R
Apple Inc.
051-8379
REVISION
5 G
IN
IN
MCP_MEM_VDD_EN
MAKE_BASE=TRUE
SMC_ADAPTER_EN
S 4
1 S
G 2
BRANCH
4.4.0
PAGE
OUT
52
5 G
57
IN
P3V3S5_EN_L
S 4
78 OF 110
SHEET
57 39 38 19 7
IN
PM_SLP_S3_L
57 OF 73
6
CRITICAL
3.3V S3 FET
8
Q7910
FDC638P_G
SM
3.3V ENET Switch

=PP3V3_S3_FET
6 5 2 1
8 8
=PP3V3_S5_P3V3ENETFET
A2 B2
TPS22924
CSP VIN VOUT A1 B1
U7980
=PP3V3_ENET_FET
=PP3V3_S5_P3V3S3FET
4
Q7910
MOSFET Type FDC638P
57
CRITICAL
IN
U7980
Part TPS22924C Load Switch 18 mOhm Typ 50 mOhm Max 2 A 0.4 A (EDP) Type R(on) I(max) Loading
R79121
10K
C7911
0.033UF
3
5% 1/20W MF 201 2
P-Channel 65 mOhm @2.5V 2.0 A @85C 1.274 A (EDP)
=P3V3ENET_EN OMIT_TABLE
C2 ON GND C1
R7910
P3V3S3_EN_L
1
10% 16V 2 X5R 402
C7910
0.01UF
1 10% 10V X5R 201 2
Rds(on) ID(max) Loading
C7980 1
1UF
10% 6.3V CERM 2 402
47K
P3V3S3_SS
Q7903
SSM3K15FV
SOD-VESM-HF
D 3
5% 1/20W MF 201
1 G
57
S 2
IN
=P3V3S3_EN
0.9V ENET FET 3.3V S0 FET

8
CRITICAL
=PP0V9_ENET_P0V9ENETFET
Q7930
TPCP8102
23V1K-SM
=PP3V3_S0_FET
5 6 7 8
C7990 1
0.1UF
8
1 2 3
=PP3V3_S5_P3V3S0FET
Q7930
MOSFET Type TPCP8102 P-Channel 14 mOhm @4.5V 7.2 A @85C 3.294 A (EDP) Rds(on) ID(max) Loading
=PP3V3_S5_P0V9ENETFET
R7990
1
10% 6.3V X5R 2 201 1
D G S
CRITICAL
100K 2
5% 1/20W MF 201
Q7990
SI2312BDS
SOT23 2
P0V9ENET_SS
100K
5% 1/20W MF 201 2
R7930
P3V3S0_EN_L
1
10% 2 16V X5R 402
0.033UF
R7932
C7931
R79921
69.8K
1% 1/20W MF 201 2
Q7991
SSM6N37FEAPE
SOT563
D 6
C7930
0.01UF
1 10% 10V X5R 201 2
=PP0V9_ENET_FET
47K
P3V3S0_SS
Q7905
SSM3K15FV
SOD-VESM-HF
D 3
5% 1/20W MF 201
R7991
P0V9ENET_EN_L
1
2 G
10K
S 1
C7991
0.01UF
Q7990
1
MOSFET Type Rds(on) ID(max) Loading
SI2312BDS N-Channel 37 mOhm @2.5V 3.25 A @85C 0.140 A (EDP)
Q7991
SSM6N37FEAPE
1 G
57
D 3
1% 1/20W MF 201
10% 10V 2 X5R 201
P0V9ENET_EN_L_RC
S 2
SOT563
IN
=P3V3S0_EN
5 G
57
S 4
IN
=P0V9ENET_EN
5V S0 FET
8
CRITICAL
Q7940
FDC638P_G
SM
=PP5V_S3_P5VS0FET
6 5 2 1 3
=PP5V_S0_FET
Q7940
Part Type FDC638P P-Channel 65 mOhm @2.5V 2.0 A @85C 0.100 A (EDP) Rds(on) ID(max) Loading
R7942
47K
C7941 1
0.033UF
10% 16V 2 X5R 402
5% 1/20W MF 201 2
R7940
P5VS0_EN_L
1
C7940
0.01UF P5VS0_SS
1 2 10% 16V CERM 402
47K
Q7945
SSM3K15FV
SOD-VESM-HF
D 3
5% 1/20W MF 201
1 G
57
S 2
IN
=P5VS0_EN
SYNC_MASTER=K16_MLB
PAGE TITLE
Power FETs
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

79 OF 110
SHEET
58 OF 73
LCD Connector
Internal DP Connector: 518S0787
CRITICAL
J9000
CABLINE-CA
Pull-ups on panel side, 4.7 kOhm to 3.3V
41 7 62 42 7
PPVOUT_SW_LCDBKLT
NC
F-RT-SM 31 1 2 3 4
BI
=I2C_TCON_SDA
62 7
OUT OUT OUT OUT OUT OUT
41 7
IN
=I2C_TCON_SCL
62 7 62 7 62 7
CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

CRITICAL
8
62 7 62 7
LED_RETURN_6 LED_RETURN_5 LED_RETURN_4 LED_RETURN_3 LED_RETURN_2 LED_RETURN_1
NC
5 6 7 8 9 10 11
LED Backlight I/F
R9060
9
NC
7
12 13 14 15 16 17
=PP3V3_S0_LCD LCD_IG_PWR_EN
1 ON
FPF1009
MFET-2X2
17 9
U9000
OUT
DP_INT_HPD FERR-120-OHM-1.5A
DP_INT_HPD_CONN
L9004
0402-LF
IN
5% 1/20W MF 201
7
DisplayPort I/F
2 VIN_1 3 VIN_2
VOUT_1 4 VOUT_2 5 THRM PAD 7
PP3V3_SW_LCD_UF
PP3V3_SW_LCD
18 19 20 21 22 23
C9015 C9024
1000PF 0.1uF
71 9
R9070
100K

71 7 71 7
GND
R90141
1K
5% 1/20W MF 201 2
C9009
0.1UF
OMIT_TABLE
C9011
0.1UF
C9012
10UF
BI
DP_INT_AUX_CH_N
1 10% 16V X5R 402
(DP_INT_AUX_CH_C_N)
10% 16V X7R 2 201
5% 1/20W MF 2 201
DP_INT_AUX_CH_C_N DP_INT_AUX_CH_C_P DP_INT_ML_F_P<0> DP_INT_ML_F_N<0> DP_INT_ML_F_P<1> DP_INT_ML_F_N<1>
10% 6.3V 2 X5R 201
10% 6.3V X5R 2 201
20% 6.3V 2 X5R 603
71 7
24 25 26
C9025
0.1uF
1 10% 16V X5R 402
71
71 7
71 9
BI
DP_INT_AUX_CH_P
(DP_INT_AUX_CH_C_P) CRITICAL
71 7 71 7
27 28 29 30
C9020
0.1uF
71 9
FL9000
DP_INT_ML_C_P<0>
1 12-OHM-100MA TCM1210-4SM
SYM_VER-2
IN
DP_INT_ML_P<0>
1 10% 16V X5R 402
4 33 34
C9021
0.1uF
1 10% 16V X5R 402
71
71 9
IN
DP_INT_ML_N<0>
71
DP_INT_ML_C_N<0>
3 35 36
B
71 9
C9022
0.1uF
1 10% 16V X5R 402 2 IN
CRITICAL
FL9001 12-OHM-100MA
DP_INT_ML_C_P<1>
1 TCM1210-4SM
SYM_VER-2
37 38 39 4 40 41
DP_INT_ML_P<1>
C9023
0.1uF
1 10% 16V X5R 402 2
71
71 9
IN
DP_INT_ML_N<1>
DP_INT_ML_C_N<1>
3 32
R90501
100K
5% 1/20W MF 201 2
R9080
100K
PLACEMENT_NOTE=PLACE CLOSE TO J9000
5% 1/20W MF 2 201
C9017
1000PF
5% 50V C0G-CERM 2 603
SYNC_MASTER=K16_MLB
PAGE TITLE
Internal DisplayPort Connector

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REVISION
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SHEET
59 OF 73
C9300
0.1UF
1 2 10% 6.3V X5R 201
9
BI
DP_EXT_AUX_CH_P
DP_AUX_CH_C_P
BI
S 4
1 S
D 3
6 D
DP_EXT_DDC_CLK
CKPLUS_WAIVE=PdifPr_badTerm SIGNAL_MODEL=DP_AUXCH_FET
CKPLUS_WAIVE=PdifPr_badTerm SIGNAL_MODEL=DP_AUXCH_FET
5 G
SSM6N37FEAPE
SOT563
Q9300
(DP_CA_DET_RC)
Q9300
SOT563
G 2
SSM6N37FEAPE
C9301
0.1UF
9
BI
DP_EXT_AUX_CH_N
DP_AUX_CH_C_N
BI
10% 6.3V X5R 201
S 4
1 S
D 3
6 D
DP_EXT_DDC_DATA
SIGNAL_MODEL=DP_AUXCH_FET
SIGNAL_MODEL=DP_AUXCH_FET
5 G
SSM6N37FEAPE
SOT563
Q9302
DP_CA_DET_RC
Q9302
SOT563
R9302
1
G 2
SSM6N37FEAPE
22
DP_CA_DET
IN
C9302 1
3300PF
5% 1/20W MF 201
NOTE: Pulled up to 5V on DP connector page. FET speced for 1.5V Vgs operaiton.
10% 10V X7R 2 201
SYNC_MASTER=K16_MLB
PAGE TITLE
External DisplayPort Support

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Port Power Switch

CRITICAL =PP3V3_S5_DP_PORT_PWR
39
TPS2051B
5 IN SOT23 OUT 1 OC* 3 GND 2 4 EN
U9480
61
PP3V3_SW_DPILIM TP_DPPWR_OC_L OMIT_TABLE
FERR-120-OHM-3A 1 2 7 PP3V3_SW_DPPWR
0603
1
L9400
IN
=DP_PWR_EN CRITICAL OMIT_TABLE
C9400
0.01UF
10% 10V 201
2 X5R
C9487 1
100UF
20% 6.3V 2 POLY-TANT CASE-B2-SM
C9480 1
20% 6.3V X5R-CERM-1 2 603
C9481
0.1UF
C9485
0.1UF
C9486
10UF
22UF
10% 2 6.3V X5R 201
10% 6.3V 2 X5R 201
20% 2 6.3V X5R 603
CRITICAL DP_ESD RCLAMP0524P

SLP2510P8
D9410
GND
HDMI_CEC
1
CRITICAL
CRITICAL
R9425
1M
J9400
MINIDSPLYPRT-K99
F-RT-TH 1
FL9400
12-OHM-100MA TCM1210-4SM
SYM_VER-2
71
DP_EXT_ML_C_P<0> DP_EXT_ML_C_N<0>
C
CRITICAL
5% 1/20W MF 2 201
C9410 C9411
1 10 2 9 4 7 5 6
2 2 4 6 8 3
71
0.1UF
1
2 DP_EXT_ML_P<0> 10% 6.3V X5R 201 2 DP_EXT_ML_N<0> 10% 6.3V X5R 201
NC IO NC IO NC IO NC IO
IN
9 71
IN
9 71
FL9403 12-OHM-100MA
71 9
R94201
100K
1
IN
DP_EXT_ML_P<3> DP_EXT_ML_N<3>
C9414 C9415
0.1UF
71 9
2 71 DP_EXT_ML_C_P<3> 10% 6.3V X5R 201 2 71 DP_EXT_ML_C_N<3> 10% 6.3V X5R 201
TCM1210-4SM
SYM_VER-2
5% 1/20W MF 201 2
71
HOT_PLUG_DETECT GND CONFIG1 ML_LANE0P CONFIG2
1 3 5 7 9 11 13 15 17 19 1
71 71 71 71 71 71
CRITICAL DP_EXT_ML_F_P<0> DP_EXT_ML_F_N<0>

1
0.1UF
FL9401
SYM_VER-2
IN
71
DP_EXT_ML_F_P<3> DP_EXT_ML_F_N<3>
10 12 14 16 18
GND ML_LANE3P ML_LANE3N GND AUX_CHP AUX_CHN DP_PWR
0.1UF
71 9 71 9
BI BI
DP_EXT_AUX_CH_C_P DP_EXT_AUX_CH_C_N
61 8 8
=PP3V3_S0_DPCONN =PP5VR3V3_S0_DPCADET
CRITICAL DP_ESD
20
ML_LANE0N GND ML_LANE1P ML_LANE1N GND ML_LANE2P ML_LANE2N RETURN
71
C9412 C9413
DP_EXT_ML_F_P<1> DP_EXT_ML_F_N<1> DP_EXT_ML_F_P<2> DP_EXT_ML_F_N<2>
0.1UF
2 3
71
IN
9 71
IN
9 71
CRITICAL
0.1UF
FL9402
SYM_VER-2
71
C9416 C9417
R94211 R94421
100K
5% 1/20W MF 201 2
D9411
RCLAMP0524P
SLP2510P8
SHIELD PINS
22 21 2 3
71
0.1UF
1
IN
9 71
R94431
100K
5% 1/20W MF 201 2
100K
5% 1/20W MF 201 2
IN
9 71
CRITICAL DP_ESD
2 IO 9 NC
0.1UF
GND
OUT
DP_EXT_CA_DET
IO 1 NC 10
D9411
RCLAMP0524P
SLP2510P8
2N7002DW-X-G
SOT-363
Q9440
1
2N7002DW-X-G
SOT-363
Q9440
4
NOTE: Q9440 must have Drain to Gate leakage of < 500 nA and gate to Source resistance of > 5 MOhm.
G
D9400
RCLAMP0504F
SC70-6-1 1 6
GND
DP_CA_DET_Q_L
CRITICAL DP_ESD
4 IO 7 NC
IO 5 NC 6
DP_CA_DET_Q
R9422
1M
5% 1/20W MF 201 2
DP to DVI/HDMI Cable Adapter (CA) has 100k pull-up to DP_PWR.
5 4
61 8
=PP3V3_S0_DPCONN
R94451
5% 1/20W MF 201 2
9
10K
PP3V3_SW_DPILIM
61
OUT
DP_EXT_HPD
6
R94441
2N7002DW-X-G
SOT-363
Q9441
1
5% 1/20W MF 201 2
G
10K
2 3
39
OUT
DP_EXT_HPD_L
2N7002DW-X-G
SOT-363
Q9441
4
SYNC_MASTER=K16_MLB
S G
DP_HPD_Q
PAGE TITLE
R94231
100K
5% 1/20W MF 201 2
DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a).
DisplayPort Connector
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REVISION
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SHEET
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*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER. *PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE. *LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
CRITICAL
D
63 62
R9700 0.01
PPBUS_SW_LCDBKLT_PWR 1 3
0.5% 1W MF 0612
8
=PP5V_S0_BKL
R9701
1
D
CRITICAL 22UH-2.5A
1 2
2 4
PPBUS_SW_BKL
MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.25mm VOLTAGE=12.6V PLACE_NEAR=L9701.1:3mm PLACE_NEAR=L9701.1:3mm 1
5% 1/20W MF 201
CRITICAL
L9701
D9701 SOD-123
PPBUS_SW_LCDBKLT_PWR_SW
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=24V SWITCH_NODE=TRUE DIDT=TRUE 1 2
PPVOUT_SW_LCDBKLT
PLACE_NEAR=U9701.21:3mm 1 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=24V 1
7 42 59
71 42
OUT OUT
ISNS_LCDBKLT_P ISNS_LCDBKLT_N
CRITICAL
IHLP2525CZ-SM
C9712 1
10UF
10% 25V 2 X5R 805
C9713
0.1UF
RB160M-60G
NO STUFF
1
C9796
220PF
C9797
10UF
C9799
10UF
71 42
10% 2 25V X5R 402
R9703
0
R9702
0
5% 1/20W MF 2 201
5% 1/20W MF 201 2
10% 2 50V X7R-CERM 402
10% 2 50V X5R 1210-1
10% 2 50V X5R 1210-1
PPVIN_SW_BKL_R
PLACE_NEAR=U9701.22:5mm PLACE_NEAR=U9701.8:4mm
8
PP5V_S0_BKL_VLDO
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V PLACE_NEAR=U9701.22:3mm 1
=PP3V3_S0_BKL_VDDIO
C9711 1
0.1UF
10% 6.3V 2 X5R 201
C9710 1
10% 25V 2 X5R 603-1
C9714
0.01UF
1UF
10% 2 10V X7R 0201
22
23
C
CRITICAL OMIT_TABLE
NC
C
24
VDDIO
VLDO
VIN
U9701
LP8545SQX
LLP
SW FB OUT1 OUT2 OUT3 OUT4 OUT5 OUT6
6 GD 5 FSET 20 FILTER 3 ISET 10 SCLK 11 SDA 2 PWM 7 FAULT
BKLT:PROD
21 12 13 14 16 17 18 19
R9741 R9753
41
BKL_FSET BKL_FLTR BKL_ISET BKL_SCL BKL_SDA BKL_PWM
10K
R9717
BKL_ISEN1 BKL_ISEN2 BKL_ISEN3 BKL_ISEN4 BKL_ISEN5 BKL_ISEN6 BKL_VSYNC_R
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
1
LED_RETURN_1
OUT
7 59
IN
=I2C_BKL_1_SCL
R9757
41
BI
=I2C_BKL_1_SDA
5% 1/20W MF 201
5% 1/20W MF 201
5% 1/16W MF-LF 402
BKLT:PROD
R9718
1
Addr: 0x58(Wr)/0x59(Rd)
5% 1/20W MF 201
LED_RETURN_2
OUT
7 59
R9731
1
TP_BKL_FAULT BKL_EN
1
63 62
PPBUS_SW_LCDBKLT_PWR
200K 2
1% 1/20W MF 201
4 EN 1 GND_SW
5% 1/16W MF-LF 402
VSYNC
BKLT:PROD
R9704
9
9 GND_S
IN
LCD_BKLT_PWM
15 GND_L
33
2 1
R9715
100K
NO STUFF
1
C9723
0.1UF
R97551
10K
THRM PAD 25
5% 1/20W MF 201 2
R9719
1
LED_RETURN_3
5% 1/20W MF 201
C9704
33PF
1% 1/20W MF 2 201
10% 2 25V X5R 402
OUT
7 59
5% 1/16W MF-LF 402
5% 2 25V NP0-C0G 201
BKLT:PROD
R97161
90.9K 1% Fpwm=9.62kHz 1/20W MF see spec for others 201 2
R9714
18.2K 1% 1/20W I_LED=23.2mA
R9720
1
LED_RETURN_4
MF 2 201
XW9710 SM
1 2
OUT
7 59
GND_BKL_SGND
5% 1/16W MF-LF 402
BKLT:PROD
R9721
1
I_LED=369/Riset (EEPROM should set EN_I_RES=1)
LED_RETURN_5
OUT
7 59
5% 1/16W MF-LF 402
BKLT:PROD
R9722
1
LED_RETURN_6
OUT
7 59
5% 1/16W MF-LF 402
FOR LP8543: STUFF R9741 NO STUFF R9740, C9740, C9741, R9754
PART NUMBER 103S0198 103S0198 353S2896
QTY 3 3 1 1
DESCRIPTION
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM IC,LP8545,LED BKLT CTRLR,PRODUCTIO,LLP24 IC,LP8545,LED BKLT CTRLR,LLP24,K99 VER
REFERENCE DES
R9717,R9718,R9719 R9720,R9721,R9722
CRITICAL
BOM OPTION BKLT:ENG BKLT:ENG
10.2 ohm resistors for current measurement on LED strings.

SYNC_MASTER=K16_MLB
PAGE TITLE
U9701 U9701
CRITICAL CRITICAL
PROJ:K16 PROJ:K99
353S2967
LCD Backlight Driver

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REVISION
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SHEET
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D
CRITICAL
8
CRITICAL
Q9806
FDC638APZ_SBMS001
SSOT6-HF 1 2 5 6
D
PPBUS_SW_LCDBKLT_PWR
62
=PPBUS_S0_LCDBKLT
F9800
2AMP-32V
1 0603 2
PPBUS_S0_LCDBKLT_FUSED
1
PPBUS S0 LCDBkLT FET

MOSFET CHANNEL RDS(ON) LOADING FDC638APZ P-TYPE 43 mOhm @4.5V 0.4 A (EDP)
R9808
301K
C9802
0.1UF
1 3
1% 1/20W MF 2 201
10% 16V X5R 2 402
LCDBKLT_EN_DIV
1
R9809
147K
1% 1/20W MF 2 201
LCDBKLT_EN_L
Q9807
SSM6N37FEAPE
SOT563
D 3
5 G
S 4
IN
LCD_BKLT_EN
1
LCDBKLT_DISABLE
C
D 6
R9810
10K
Q9807
SSM6N37FEAPE
SOT563
5% 1/20W MF 2201
2 G
25
S 1
IN
BKLT_PLT_RST_L
SYNC_MASTER=K16_MLB
PAGE TITLE
LCD Backlight Support

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REVISION
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ADDITIONAL CPU VCORE HF DECOUPLING

40x 1uF 0402
=PPVCORE_S0_CPU
12 11 8
OMIT_TABLE
CRITICAL 20% 6.3V CERM 402-LF
OMIT_TABLE
C9900 C9901 C9902 C9903 C9904 C9905 C9906 C9907 C9908 C9909 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 6.3V CERM 402-LF 20% 6.3V CERM 402-LF 20% 6.3V CERM 402-LF 20% 6.3V CERM 402-LF 20% 6.3V CERM 402-LF 20% 6.3V CERM 402-LF 20% 6.3V CERM 402-LF 20% 6.3V CERM 402-LF 20% 6.3V CERM 402-LF
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE OMIT_TABLE
CRITICAL
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
C
C
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
OMIT_TABLE
CRITICAL
SYNC_MASTER=K16_MLB
PAGE TITLE
Additional CPU/GPU Decoupling

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8
PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH
7
MINIMUM NECK WIDTH MAXIMUM NECK LENGTH
6
TABLE_PHYSICAL_RULE_HEAD
5
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
4
CPU / FSB Net Properties
ELECTRICAL_CONSTRAINT_SET FSB_DATA_GROUP0 FSB_DATA_GROUP0 FSB_DSTB0 FSB_DSTB0 FSB_DATA_GROUP1 FSB_DATA_GROUP1 FSB_DSTB1 FSB_DSTB1 FSB_DATA_GROUP2 FSB_DATA_GROUP2 FSB_DSTB2 FSB_DSTB2 FSB_DATA_GROUP3 FSB_DATA_GROUP3 FSB_DSTB3 FSB_DSTB3 FSB_ADDR_GROUP0 FSB_ADDR_GROUP0 FSB_ADSTB0 FSB_ADDR_GROUP1 FSB_ADSTB1 FSB_1X FSB_BREQ0_L FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_CPURST_L FSB_1X FSB_1X CPU_ASYNC CPU_BSEL CPU_FERR_L CPU_ASYNC CPU_INIT_L CPU_ASYNC_R CPU_ASYNC_R CPU_PROCHOT_L CPU_PWRGD CPU_ASYNC CPU_ASYNC PM_THRMTRIP_L FSB_CPUSLP_L CPU_FROM_SB CPU_DPRSTP_L CPU_ASYNC FSB_CLK_CPU FSB_CLK_CPU FSB_CLK_ITP FSB_CLK_ITP FSB_CLK_MCP FSB_CLK_MCP CPU_IERR_L PM_DPRSLPVR NET_TYPE PHYSICAL SPACING FSB_55S FSB_55S FSB_DSTB_55S FSB_DSTB_55S FSB_55S FSB_55S FSB_DSTB_55S FSB_DSTB_55S FSB_55S FSB_55S FSB_DSTB_55S FSB_DSTB_55S FSB_55S FSB_55S FSB_DSTB_55S FSB_DSTB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S FSB_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CPU_55S CPU_55S CPU_55S MCP_50S MCP_50S MCP_50S MCP_50S CPU_50S CPU_50S CPU_27P4S CPU_50S CPU_27P4S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_AGTL CPU_AGTL MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_8MIL CPU_8MIL CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_ADDR FSB_ADDR FSB_ADSTB FSB_ADDR FSB_ADSTB FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB
FSB (Front-Side Bus) Constraints

DIFFPAIR PRIMARY GAP
FSB_55S FSB_DSTB_55S
* *
=55_OHM_SE
=55_OHM_SE =55_OHM_SE
TABLE_SPACING_RULE_HEAD
=STANDARD =1:1_DIFFPAIR
=STANDARD
=55_OHM_SE
=1:1_DIFFPAIR
FSB 4X Signal Groups
FSB_D_L<15..0> FSB_DINV_L<0> FSB_DSTB_L_P<0> FSB_DSTB_L_N<0> FSB_D_L<31..16> FSB_DINV_L<1> FSB_DSTB_L_P<1> FSB_DSTB_L_N<1> FSB_D_L<47..32> FSB_DINV_L<2> FSB_DSTB_L_P<2> FSB_DSTB_L_N<2> FSB_D_L<63..48> FSB_DINV_L<3> FSB_DSTB_L_P<3> FSB_DSTB_L_N<3> FSB_A_L<16..3> FSB_REQ_L<4..0> FSB_ADSTB_L<0> FSB_A_L<35..17> FSB_ADSTB_L<1> FSB_ADS_L FSB_BREQ0_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L<2..0> FSB_TRDY_L CPU_A20M_L CPU_BSEL<2..0> CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L FSB_DPWR_L FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N CPU_IERR_L PM_DPRSLPVR IMVP_DPRSLPVR MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND CPU_GTLREF CPU_COMP<3> CPU_COMP<2> CPU_COMP<1> CPU_COMP<0> XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L<4..0> XDP_BPM_L<5> XDP_CPURST_L CPU_VID<6..0> IMVP6_VID<6..0> CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N
7 10 14 7 10 14 7 10 14 7 10 14
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SPACING_RULE_SET
LAYER
WEIGHT
FSB_DATA FSB_DSTB
* * * * *
=2x_DIELECTRIC =3x_DIELECTRIC =STANDARD =2x_DIELECTRIC =STANDARD
?
FSB_DATA FSB_DSTB
TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM
=4x_DIELECTRIC =5x_DIELECTRIC =3x_DIELECTRIC =4x_DIELECTRIC =3x_DIELECTRIC
?
7 10 14 7 10 14 7 10 14 7 10 14
? ?
?
FSB_ADDR FSB_ADSTB FSB_1X
FSB_ADDR FSB_ADSTB
?
? ?
?
7 10 14 7 10 14 7 10 14 7 10 14
FSB_1X
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended. FSB 4X signals / groups shown in signal table on right. Signals within each 4x group should be matched within 5 ps of strobe. DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 135 ps. Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s. FSB 2X signals / groups shown in signal table on right. Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 270 ps. Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#. FSB 1X signals shown in signal table on right. Intel Design Guide recommends FSB signals be routed only on internal layers. NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
7 10 14 7 10 14 7 10 14 7 10 14
FSB 2X Signals
7 10 14 7 10 14 7 10 14
7 10 14 7 10 14
7 10 14 10 14 10 14 10 14 10 14 10 14 10 14 7 10 14 7 10 14 7 10 14 10 13 14 10 14 10 14
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1 SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

CPU_55S
* *
=55_OHM_SE
=27P4_OHM_SE
=55_OHM_SE =27P4_OHM_SE
=STANDARD 7 MIL
=STANDARD
FSB 1X Signals
CPU_27P4S
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
10 14 9 10 10 14 10 14 10 14 10 14 10 14 10 14 39 10 13 14 10 14 10 14 10 14 39 10 14 10 14 10 14 53 10 14
CPU_AGTL CPU_8MIL CPU_COMP CPU_GTLREF CPU_ITP CPU_VCCSENSE
* * * * * *
=STANDARD 8 MIL 25 MIL 25 MIL =2:1_SPACING 25 MIL
?
CPU_AGTL
TOP,BOTTOM
=2x_DIELECTRIC
?
?
?
SR DG recommends at least 25 mils, >50 mils preferred

? ?
Most CPU signals with impedance requirements are 55-ohm single-ended. Some signals require 27.4-ohm single-ended impedance. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP FSB COMP Signal Constraints

10 14 10 14 13 14 13 14 14 14
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MCP_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_FSB_COMP
8 MIL
10
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1.4
14 53
FSB Clock Constraints

(See above)
MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER? =100_OHM_DIFF
MINIMUM LINE WIDTH
CLK_FSB_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
MCP_CPU_COMP MCP_CPU_COMP MCP_CPU_COMP MCP_CPU_COMP CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L5
14 14 14 14
10 33 10 10 10 10
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
CLK_FSB
=3x_DIELECTRIC
CLK_FSB
TOP,BOTTOM
=4x_DIELECTRIC
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
10 13 10 13 10 13 10 13 10 13 10 13 10 13 13
(FSB_CPURST_L)
11 12 53 12 11 53 11 53 53 53
CPU_VCCSENSE CPU_VCCSENSE
(CPU_VCCSENSE) (CPU_VCCSENSE)
SYNC_MASTER=K16_MLB
PAGE TITLE
CPU/FSB Constraints
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

100 OF 110
SHEET
65 OF 73
8
Memory Bus Constraints
7
6
5
DIFFPAIR NECK GAP
4
Memory Net Properties
ELECTRICAL_CONSTRAINT_SET MEM_A_CLK MEM_A_CLK MEM_A_CKE MEM_A_CNTL MEM_A_CNTL MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7 MEM_B_CLK MEM_B_CLK MEM_B_CKE MEM_B_CNTL MEM_B_CNTL MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7 MCP_MEM_COMP MCP_MEM_COMP NET_TYPE PHYSICAL SPACING MEM_70D MEM_70D MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_55S MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MCP_MEM_COMP MCP_MEM_COMP MEM_CLK MEM_CLK MEM_CTRL MEM_CTRL MEM_CTRL MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_CLK MEM_CLK MEM_CTRL MEM_CTRL MEM_CTRL MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MCP_MEM_COMP MCP_MEM_COMP
MEM_50S MEM_55S MEM_70D
* * *
=70_OHM_DIFF
=50_OHM_SE =55_OHM_SE =70_OHM_DIFF
=STANDARD =STANDARD =70_OHM_DIFF
=STANDARD
=STANDARD
MEM_A_CLK_P<5..0> MEM_A_CLK_N<5..0> MEM_A_CKE<3..0> MEM_A_CS_L<3..0> MEM_A_ODT<3..0> MEM_A_A<15..0> MEM_A_BA<2..0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56> MEM_A_DM<0> MEM_A_DM<1> MEM_A_DM<2> MEM_A_DM<3> MEM_A_DM<4> MEM_A_DM<5> MEM_A_DM<6> MEM_A_DM<7> MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_B_CLK_P<5..0> MEM_B_CLK_N<5..0> MEM_B_CKE<3..0> MEM_B_CS_L<3..0> MEM_B_ODT<3..0> MEM_B_A<15..0> MEM_B_BA<2..0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56> MEM_B_DM<0> MEM_B_DM<1> MEM_B_DM<2> MEM_B_DM<3> MEM_B_DM<4> MEM_B_DM<5> MEM_B_DM<6> MEM_B_DM<7> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7> MCP_MEM_COMP_VDD MCP_MEM_COMP_GND
9 15 26 27 32 9 15 26 27 32
=70_OHM_DIFF
15 21 26 27 32 15 26 27 32 15 26 27 32
9 15 26 27 32 15 26 27 32 15 26 27 32 15 26 27 32 15 26 27 32
SPACING_RULE_SET
LAYER
WEIGHT
MEM_CLK2MEM MEM_CTRL2CTRL MEM_CTRL2MEM MEM_CMD2CMD MEM_CMD2MEM MEM_DATA2DATA MEM_DATA2MEM MEM_DQS2MEM MEM_2OTHER
* * * * * * * * *
=4:1_SPACING =2:1_SPACING =2.5:1_SPACING =1.5:1_SPACING =3:1_SPACING =1.5:1_SPACING =3:1_SPACING =3:1_SPACING 25 MIL
?
NV DG says 3x inner, 4x outer NV DG says 2x inner, 4x outer

? ?

15 26 15 26 15 26 15 26 15 27 15 27 15 27 15 27
? ?

? ?

? ?
15 26 15 26 15 26 15 26 15 27 15 27 15 27 15 27
Memory Bus Spacing Group Assignments

TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK MEM_CLK MEM_CLK MEM_CLK MEM_CLK
MEM_CLK MEM_CTRL MEM_CMD MEM_DATA MEM_DQS
* * * * *
MEM_CLK2MEM
MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD
* * * * *
MEM_CMD2MEM
MEM_CLK2MEM
MEM_CMD2MEM
15 26 15 26 15 26 15 26 15 26 15 26 15 26 15 26 15 27 15 27 15 27 15 27 15 27 15 27 15 27 15 27
MEM_CLK2MEM
MEM_CMD2CMD
MEM_CLK2MEM
MEM_CMD2MEM
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
MEM_CMD2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL MEM_CTRL MEM_CTRL MEM_CTRL MEM_CTRL
* * * * *
MEM_CTRL2MEM
MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA
* * * * *
MEM_DATA2MEM
MEM_CTRL2CTRL
MEM_DATA2MEM
MEM_CTRL2MEM
MEM_DATA2MEM
MEM_CTRL2MEM
MEM_DATA2DATA
MEM_CTRL2MEM
MEM_DATA2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
9 15 28 29 32 9 15 28 29 32
MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS
* * * * *
MEM_DQS2MEM
* * * * *
* * * * *
MEM_2OTHER
MEM_DQS2MEM
MEM_2OTHER
15 21 28 29 32 15 28 29 32 15 28 29 32
MEM_DQS2MEM
MEM_2OTHER
MEM_DQS2MEM
MEM_2OTHER
9 15 28 29 32 15 28 29 32 15 28 29 32 15 28 29 32 15 28 29 32
MEM_DQS2MEM
MEM_2OTHER
DDR3:
Need to support MEM_*-style wildcards!
DQ signals should be matched within 5 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 360 ps No DQS to clock matching requirement. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. CMD/CTRL signals should be matched within 150 ps. All memory signals maximum length is 1.030 ps. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
15 28 15 28 15 28 15 28 15 29 15 29 15 29 15 29
MCP MEM COMP Signal Constraints

15 28 15 28 15 28 15 28 15 29 15 29 15 29 15 29
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MCP_MEM_COMP
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_MEM_COMP
=2x_DIELECTRIC
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.2
15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29
SYNC_MASTER=K16_MLB
PAGE TITLE
Memory Constraints
DRAWING NUMBER SIZE
15 15
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

MEM_A/B_CKE EC SET NAME IS CHANGED ON K6, CANNOT SYNC THIS PAGE FROM T27
101 OF 110
SHEET
66 OF 73
8
PCI-Express
PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? =90_OHM_DIFF =100_OHM_DIFF MINIMUM LINE WIDTH
7
6
5
DIFFPAIR NECK GAP
4
MCP89 Net Properties
ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE MCP_PEX_COMP CRT CRT CRT CRT_SYNC CRT_SYNC MCP_DAC_COMP MCP_DAC_COMP DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
PCIE_90D CLK_PCIE_100D
* *
=90_OHM_DIFF =100_OHM_DIFF
=90_OHM_DIFF
=100_OHM_DIFF
PEG_R2D
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
PEG_D2R
PCIE CLK_PCIE
* * *
=3X_DIELECTRIC 20 MIL 8 MIL
?
PCIE
TOP,BOTTOM
=4X_DIELECTRIC
?
PEG_R2D_P<15..0> PEG_R2D_N<15..0> PEG_R2D_C_P<15..0> PEG_R2D_C_N<15..0> PEG_D2R_P<15..0> PEG_D2R_N<15..0> PEG_D2R_C_P<15..0> PEG_D2R_C_N<15..0> PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N MCP_PEX0_TERMP CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC MCP_TV_DAC_RSET MCP_TV_DAC_VREF DP_IG_ML1_P<1..0> DP_IG_ML1_N<1..0> DP_IG_AUX_CH1_P DP_IG_AUX_CH1_N DP_IG_ML0_P<3..0> DP_IG_ML0_N<3..0> DP_IG_AUX_CH0_P DP_IG_AUX_CH0_N MCP_TMDS0_RSET MCP_TMDS0_VPROBE
9 17 9 17 9 17 9 17 9 16 9 16 7 16 34 7 16 34 7 34 7 34 16 34 16 34 7 16 34 7 16 34
MCP_PEX_COMP
?
PCIE_AP_R2D
SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.3
NEED PCIe Gen1/Gen2 notes!

Analog Video Signal Constraints
PCIE_AP_D2R
PCIE_ENET_R2D PCIE_ENET_D2R
MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
CRT_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CRT CRT_2CRT CRT_2CLK CRT_2SWITCHER CRT_SYNC
* * * * * *
20 MIL 15 MIL 50 MIL 250 MIL =4x_DIELECTRIC =2x_DIELECTRIC
?
CRT
CRT
CRT_2CRT
PCIE_FW_R2D PCIE_FW_D2R
?
?
?
?
MCP_PE0_REFCLK MCP_PE1_REFCLK MCP_PE2_REFCLK MCP_PE3_REFCLK MCP_PEX_CLK_COMP CRT_RED CRT_GREEN CRT_BLUE CRT_SYNC CRT_SYNC MCP_DAC_RSET MCP_DAC_VREF DP_INT_ML DP_INT_ML DP_INT_AUX_CH DP_INT_AUX_CH DP_EXT_ML DP_EXT_ML DP_EXT_AUX_CH DP_EXT_AUX_CH MCP_TMDS0_RSET MCP_TMDS0_VPROBE LVDS_IG_A_CLK LVDS_IG_A_CLK LVDS_IG_A_DATA LVDS_IG_A_DATA LVDS_IG_A_DATA3 LVDS_IG_A_DATA3 LVDS_IG_B_CLK LVDS_IG_B_CLK LVDS_IG_B_DATA LVDS_IG_B_DATA LVDS_IG_B_DATA3 LVDS_IG_B_DATA3 MCP_IFPAB_RSET MCP_IFPAB_VPROBE SATA_HDD_R2D
MCP_DAC_COMP
CRT signal single-ended impedence varies by location: - 37.5-ohm from MCP to first termination resistor. - 50-ohm from first to second termination resistor. - 75-ohm from output of three-pole filter to connector (if possible). R/G/B signals should be matched as close as possible and < 10 inches. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.1.
16
Digital Video Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER? =90_OHM_DIFF =100_OHM_DIFF Y
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

DP_90D LVDS_100D MCP_DV_COMP
* * *
=90_OHM_DIFF =100_OHM_DIFF 20 MIL

=90_OHM_DIFF =100_OHM_DIFF 20 MIL
=90_OHM_DIFF =100_OHM_DIFF =STANDARD
=90_OHM_DIFF =100_OHM_DIFF =STANDARD
=90_OHM_DIFF
CRT_50S CRT_50S CRT_50S CRT_50S CRT_50S
=100_OHM_DIFF
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
DISPLAYPORT LVDS
* *
=3x_DIELECTRIC =3x_DIELECTRIC
?
DISPLAYPORT LVDS
TOP,BOTTOM TOP,BOTTOM
=4x_DIELECTRIC =4x_DIELECTRIC
?
DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D MCP_DV_COMP
9 17 9 17 9 17 9 17
LVDS intra-pair matching should be 5 mils. Pairs should be matched within 100 mils. NOTE: NV DG recommends 90 ohm differential for LVDS, but cable/display assume 100 ohm. DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 100 ps. DisplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals. Max trace length: LVDS 10 inches, DP 8.5 inches. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.2
17 24 17 24
SATA Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER? =90_OHM_DIFF
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SATA_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
SATA SATA_TERMP
* *
=3x_DIELECTRIC 8 MIL
?
SATA
TOP,BOTTOM
=4x_DIELECTRIC
SATA intra-pair matching should be 1 ps. Max trace length: 12 inches for SATA Gen1/Gen2, TBD for SATA Gen3. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.6
LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D MCP_DV_COMP
LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS
LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P<2..0> LVDS_IG_A_DATA_N<2..0> LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3> LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P<2..0> LVDS_IG_B_DATA_N<2..0> LVDS_IG_B_DATA_P<3> LVDS_IG_B_DATA_N<3> MCP_IFPAB_RSET MCP_IFPAB_VPROBE
17 24 17 24
SATA_HDD_D2R
SATA_ODD_R2D
A
SATA_ODD_D2R MCP_SATA_TERMP
SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D
SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA_TERMP
SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N MCP_SATA_TERMP
18 35 18 35 7 35 7 35 18 35 18 35 7 35 7 35 9 18 9 18 9 9 9 18 9 18
SYNC_MASTER=K16_MLB
PAGE TITLE
MCP Constraints 1
DRAWING NUMBER SIZE
Apple Inc.
18 R
051-8379
REVISION
4.4.0
BRANCH PAGE

102 OF 110
SHEET
67 OF 73
8
LPC Bus Constraints
7
6
5
DIFFPAIR NECK GAP
4
MCP89 Net Properties
ELECTRICAL_CONSTRAINT_SET LPC_AD LPC_FRAME_L LPC_RESET_L MCP_LPC_CLK0 NET_TYPE PHYSICAL SPACING LPC_55S LPC_55S LPC_55S CLK_LPC_55S CLK_LPC_55S CLK_LPC_55S USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D MCP_USB_RBIAS SMB_55S SMB_55S SMB_55S SMB_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S SMB SMB SMB SMB HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA MCP_HDA_COMP CLK_SLOW_55S CLK_SLOW_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S CLK_SLOW CLK_SLOW SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI LPC LPC LPC CLK_LPC CLK_LPC CLK_LPC USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB
LPC_55S CLK_LPC_55S
* *
=STANDARD =STANDARD
=STANDARD
=STANDARD
LPC_AD<3..0> LPC_FRAME_L LPC_RESET_L LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_MINI_P USB_MINI_N USB_EXTD_P USB_EXTD_N USB_CAMERA_P USB_CAMERA_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N USB_T57_P USB_T57_N USB_EXTC_P USB_EXTC_N USB_SDCARD_P USB_SDCARD_N USB_WM_P USB_WM_N MCP_USB_RBIAS_GND SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R MCP_HDA_PULLDN_COMP PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L SPI_MLB_CLK SPI_MLB_MOSI SPI_MLB_MISO SPI_MLB_CS_L SPI_ALT_CLK SPI_ALT_MOSI SPI_ALT_MISO SPI_ALT_CS_L
7 19 38 40 7 19 38 40 19 25
SPACING_RULE_SET
LAYER
WEIGHT
19 25 25 38 7 25 40
LPC CLK_LPC
* *
=1.5x_DIELECTRIC =2x_DIELECTRIC
?
USB_EXTA
18 36 18 36 36 71 36 71 9 18 9 18 7 18 37 7 18 37 7 18 37 7 18 37 7 18 34 7 18 34 18 46 71 18 46 71
USB 2.0 Interface Constraints

USB_MINI
MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MCP_USB_RBIAS USB_90D
* *
=STANDARD
=90_OHM_DIFF
8 MIL =90_OHM_DIFF
8 MIL =90_OHM_DIFF
=STANDARD =90_OHM_DIFF
=STANDARD =90_OHM_DIFF
=STANDARD
USB_EXTD USB_CAMERA USB_BT USB_TPAD USB_IR USB_EXTB
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
USB
=2x_DIELECTRIC
USB
TOP,BOTTOM
=4x_DIELECTRIC
SMBus Interface Constraints

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

USB_T57 USB_EXTC
SMB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
9 18 9 18 9 18 9 18
SPACING_RULE_SET
LAYER
WEIGHT
USB_SDCARD USB_WM
SMB
=2x_DIELECTRIC
C HD Audio Interface Constraints

PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP
MCP_USB_RBIAS
18
DIFFPAIR NECK GAP

HDA_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA (SMBUS_SMC_MGMT_SCL) (SMBUS_SMC_MGMT_SDA) HDA_BIT_CLK HDA_SYNC
19 41 19 41 19 41 19 41
SPACING_RULE_SET
LAYER
WEIGHT
7 19 37 19 7 19 37 19 19 7 19 37 7 19 37
HDA MCP_HDA_COMP
* *
=2x_DIELECTRIC 8 MIL
?
?
HDA_RST_L
SIO Signal Constraints

HDA_SDIN0 HDA_SDOUT
PHYSICAL_RULE_SET
LAYER
7 19 37 19
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

CLK_SLOW_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
MCP_HDA_PULLDN_COMP MCP_SUS_CLK
19
19 25 25 38
SPACING_RULE_SET
LAYER
WEIGHT
CLK_SLOW
=1.5x_DIELECTRIC
SPI_CLK SPI_MOSI SPI_MISO SPI_CS0
19 40 40 19 40 40 19 40 19 40 40
SPI Interface Constraints

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
40 47 40 47 40 47 40 47
SPACING_RULE_SET
LAYER
WEIGHT
SPI
=1.5x_DIELECTRIC
7 40 7 40 7 40 7 40
SYNC_MASTER=K16_MLB
PAGE TITLE
MCP Constraints 2
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

103 OF 110
SHEET
68 OF 73
8
7
6
5
DIFFPAIR NECK GAP
4
RGMII Net Properties
ELECTRICAL_CONSTRAINT_SET MCP_MII_COMP MCP_MII_COMP MCP_CLK25M_BUF0 NET_TYPE PHYSICAL SPACING MCP_MII_COMP MCP_MII_COMP ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S MCP_BUF0_CLK MCP_BUF0_CLK ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII
MCP RGMII (Ethernet) Constraints

MCP_MII_COMP ENET_MII_55S
* *
=STANDARD =55_OHM_SE
7.5 MIL =55_OHM_SE

7.5 MIL =55_OHM_SE
=STANDARD =55_OHM_SE
=STANDARD =STANDARD
=STANDARD
=STANDARD
MCP_MII_COMP_VDD MCP_MII_COMP_GND MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1 ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_CLK125M_RXCLK_R ENET_CLK125M_RXCLK ENET_RXD_R<3..0> ENET_RXD<0> ENET_RXD<3..1> ENET_RX_CTRL ENET_CLK125M_TXCLK ENET_TXD<0> ENET_TXD<3..1> ENET_TX_CTRL ENET_RESET_L
18 18
SPACING_RULE_SET
LAYER
WEIGHT
MCP_BUF0_CLK ENET_MII
* *
=3:1_SPACING 12 MIL
?
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_RXCLK

9 18
D
9 18 9 18 9 18 9 18
88E1116R (Ethernet PHY) Constraints

PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? =100_OHM_DIFF MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ENET_MDI_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
ENET_RXD_STRAP ENET_RXD_STRAP ENET_RXD ENET_TXCLK ENET_TXD ENET_TXD ENET_TXD
SPACING_RULE_SET
LAYER
WEIGHT
ENET_MDI
25 MIL
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4
SD Card Interface Constraints

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

Ethernet Net Properties

ELECTRICAL_CONSTRAINT_SET ENET_MDI NET_TYPE PHYSICAL SPACING ENET_MDI_100D ENET_MDI ENET_MDI_100D ENET_MDI
SD_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
ENET_MDI_P<3..0> ENET_MDI_N<3..0>
SD_INTERFACE
=3X_DIELECTRIC
SD Card Net Properties

ELECTRICAL_CONSTRAINT_SET NET_TYPE SPACING PHYSICAL SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_55S SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE SD_INTERFACE
SD_DATA
SD_D<4..0> SDCONN_DATA<4..0> BCM57765_CR_DATA<4> SD_D<7..5> SDCONN_DATA<7..5> BCM57765_CR_DATA<7..5> SD_CLK SD_CLK_R SDCONN_CLK SD_CMD SDCONN_CMD BCM57765_CR_CMD
SD_DATA_R
SD_CLK
SD_CMD
NOTE: SD_D<7..5> are different to support BCM5764M/BCM57765 co-layout.
SYNC_MASTER=K16_MLB
PAGE TITLE
Ethernet Constraints
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

104 OF 110
SHEET
69 OF 73
8
PHYSICAL_RULE_SET
1TO1_DIFFPAIR
7
LAYER
*
6
5
DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET
4
SMC SMBus Net Properties
NET_TYPE PHYSICAL SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SPACING SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB

=STANDARD
MINIMUM LINE WIDTH

=STANDARD
MINIMUM NECK WIDTH

=STANDARD
MAXIMUM NECK LENGTH

=STANDARD

0.1 MM
0.1 MM
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
41 41 41 41 41 41 7 41 7 41 41 41
SMBus Charger Net Properties

NET_TYPE ELECTRICAL_CONSTRAINT_SET CHGR_CSI PHYSICAL 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR SPACING
CHGR_CSI_P CHGR_CSI_N CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_P CHGR_CSO_N CHGR_CSO_R_P CHGR_CSO_R_N
50 50 50 50
50 50 43 50 43 50
SYNC_MASTER=K16_MLB
PAGE TITLE
SMC Constraints
DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

106 OF 110
SHEET
70 OF 73
8
7
6
5
Misc Net Properties
ELECTRICAL_CONSTRAINT_SET (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_TPAD) (USB_TPAD) (USB_TPAD) (USB_TPAD)
SMBUS_SMC_MGMT_SDA SMBUS_SMC_MGMT_SCL
4
NET_TYPE PHYSICAL SPACING USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S USB USB USB USB USB USB USB USB SMB SMB SMB SMB SMB SMB
3
ELECTRICAL_CONSTRAINT_SET
2
Power Net Properties
NET_TYPE PHYSICAL SPACING THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S THERM THERM THERM THERM THERM THERM THERM THERM SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE MEM_POWER
DIFFPAIR NECK GAP

SENSE_1TO1_55S THERM_1TO1_55S DIFFPAIR
* * *
=1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR
=55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR
=1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
SPACING_RULE_SET
LAYER
WEIGHT
SENSE THERM AUDIO
* * *
=1:1_SPACING =1:1_SPACING =1:1_SPACING
?
USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_LT1_P USB_LT1_N USB_TPAD_P USB_TPAD_N USB_TPAD_CONN_P USB_TPAD_CONN_N I2C_SMC_SMS_SDA_R I2C_SMC_SMS_SCL_R I2C_TCON_SCL I2C_TCON_SDA I2C_TCON_SCL_CONN I2C_TCON_SDA_CONN
36 68 36 68 36 36 18 46 68 18 46 68 7 46 7 46
CPUTHMSNS_D2 CPU_THERMD MCPTHMSNS_D2 MCP_THMDIODE
DRAMTHMSNS_D2_P DRAMTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N MLBR_THMDIODE_P MLBR_THMDIODE_N MCP_THMDIODE_P MCP_THMDIODE_N ISNS_1V5_S3_P ISNS_1V5_S3_N ISNS_AIRPORT_P ISNS_AIRPORT_N ISNS_CSREG_P ISNS_CSREG_N ISNS_HDD_P ISNS_HDD_N ISNS_LCDBKLT_P ISNS_LCDBKLT_N CPUVTTS0_CS_P CPUVTTS0_CS_N IMVP6_CS_P IMVP6_CS_N IMVP6_CS_R_P IMVP6_CS_R_N CPU_VTTSENSE_P CPU_VTTSENSE_N MCPCORES0_VSEN_P MCPCORES0_VSEN_N PP1V5R1V35_S3 PP3V3_S5 PP3V3_S0 PP1V5_S0 GND
44 44 10 44 10 44 44 44 19 44 19 44
?
SENSE_DIFFPAIR SENSE_DIFFPAIR
41 41
42 52 42 52 34 42 34 42 43 43 35 42 35 42 42 62 42 62
SENSE_DIFFPAIR SENSE_DIFFPAIR SENSE_DIFFPAIR
SPACING_RULE_SET
LAYER
WEIGHT
ENETCONN
25 MILS
?
Graphics Net Properties

ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D (DP_EXT_ML) DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
SPACING_RULE_SET
LAYER
WEIGHT
SENSE_DIFFPAIR
55 55 53 53 53 53
GND MEM_POWER
* *
=STANDARD =STANDARD
? ?
SPACING_RULE_SET
LAYER
WEIGHT
GND_P2MM PWR_P2MM
* *
0.20 MM 0.20 MM
1000
1000
DP_INT_ML_P<1..0> DP_INT_ML_N<1..0> DP_INT_ML_C_P<1..0> DP_INT_ML_C_N<1..0> DP_INT_ML_F_P<1..0> DP_INT_ML_F_N<1..0> DP_INT_AUX_CH_C_P DP_INT_AUX_CH_C_N DP_INT_AUX_CH_P DP_INT_AUX_CH_N DP_EXT_ML_P<3..0> DP_EXT_ML_N<3..0> DP_EXT_ML_C_P<3..0> DP_EXT_ML_C_N<3..0> DP_EXT_ML_F_P<3..0> DP_EXT_ML_F_N<3..0> DP_EXT_AUX_CH_C_P DP_EXT_AUX_CH_C_N
9 59 9 59 59 59 7 59 7 59
SENSE_DIFFPAIR SENSE_DIFFPAIR
SENSE_DIFFPAIR
7 59 7 59 9 59 9 59
55 55 22 54 22 54
SENSE_DIFFPAIR
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
7 8
MEM_CLK MEM_CMD
GND GND GND GND GND
* * * * *
GND_P2MM
MEM_CLK MEM_CMD MEM_CTRL MEM_DATA MEM_DQS
MEM_POWER MEM_POWER MEM_POWER MEM_POWER MEM_POWER
* * * * *
PWR_P2MM
9 61 9 61 61 61 61 61 9 61 9 61
GND_P2MM
PWR_P2MM
MEM_CTRL MEM_DATA MEM_DQS
GND_P2MM
PWR_P2MM
SB_POWER SB_POWER SB_POWER GND
7 8 57 7 8 57 7 8 57
GND_P2MM
PWR_P2MM
GND_P2MM
PWR_P2MM
(DP_EXT_AUX_CH)
Audio Net Properties

ELECTRICAL_CONSTRAINT_SET SPKRAMP_INR NET_TYPE PHYSICAL SPACING DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR AUDIO AUDIO AUDIO AUDIO
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CLK_PCIE PCIE SATA USB CLK_PCIE SATA USB
GND GND GND GND SB_POWER SB_POWER SB_POWER
* * * * * * *
GND_P2MM
CLK_FSB CPU_COMP CPU_GTLREF CPU_VCCSENSE
GND GND GND GND
* * * *
GND_P2MM
GND_P2MM
GND_P2MM
SPKRAMP_INR_P SPKRAMP_INR_N MAX98300_R_P MAX98300_R_N
7 37 48 7 37 48
GND_P2MM
GND_P2MM
MAX98300_R
48 48
GND_P2MM
GND_P2MM
PWR_P2MM
PWR_P2MM
PWR_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
LVDS
GND
GND_P2MM
ENET_MDI
GND
GND_P2MM
SD CARD READER LAYOUT RELAXATIONS

B
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SD_55S
OVERRIDE
*
OVERRIDE OVERRIDE
=STANDARD
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
MCP Fanout Constraint Relaxations

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MEM_40S
OVERRIDE
*
OVERRIDE OVERRIDE OVERRIDE
0.09 MM
OVERRIDE
5.8 MM
MCP_DV_COMP
OVERRIDE
TOP
0.1 MM
OVERRIDE
500 MIL
MCP_MEM_COMP
OVERRIDE
TOP
0.1 MM
OVERRIDE
500 MIL
MCP_MII_COMP
OVERRIDE
TOP
0.1 MM
OVERRIDE
500 MIL
MCP_USB_RBIAS
OVERRIDE
TOP
0.1 MM
OVERRIDE
500 MIL
MCP_DV_COMP
OVERRIDE
*
0.25 MM
OVERRIDE
250 MIL
SYNC_MASTER=K16_MLB
PAGE TITLE
K16/K99 Specific Constraints

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

108 OF 110
SHEET
71 OF 73
6
TABLE_BOARD_INFO
K99 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

BOARD LAYERS TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM BOARD AREAS NO_TYPE,BGA BOARD UNITS (MIL or MM) MM ALLEGRO VERSION 15.5.1
TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SPACING_RULE_SET
LAYER
WEIGHT SPACING_RULE_SET
LAYER
WEIGHT
DEFAULT STANDARD
* *
Y Y
0.100 MM =DEFAULT
0.076 MM =DEFAULT
30 MM 12.7 MM
0 MM =DEFAULT
0 MM
DEFAULT STANDARD BGA_P1MM

* * * * *
0.1 MM =DEFAULT 0.1 MM 0.2 MM 0.3 MM
?
2X_DIELECTRIC 3X_DIELECTRIC
* * * * *
0.140 MM 0.210 MM 0.280 MM 0.105 MM 0.350 MM
=DEFAULT
? ?
4X_DIELECTRIC 1.5X_DIELECTRIC
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

BGA_P2MM BGA_P3MM
? ?
27P4_OHM_SE 27P4_OHM_SE 27P4_OHM_SE
*
ISL3,ISL10 ISL4,ISL9
Y Y Y
=STANDARD 0.250 MM 0.250 MM
=STANDARD 0.250 MM
=STANDARD
=STANDARD
=STANDARD
5X_DIELECTRIC
? ? ? ? ?
0.250 MM
SPACING_RULE_SET
LAYER
WEIGHT
1:1_SPACING
PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
* * * * * * * *
0.1 MM 0.15 MM 0.18 MM 0.2 MM 0.228 MM 0.25 MM 0.3 MM 0.4 MM
?
1.5:1_SPACING 1.8:1_SPACING 2:1_SPACING
?
40_OHM_SE 40_OHM_SE
* TOP,BOTTOM
Y Y Y
=STANDARD 0.170 MM
=STANDARD
=STANDARD
=STANDARD
?
?
40_OHM_SE ISL3,ISL4,ISL9,ISL10
0.140 MM
2.28:1_SPACING 2.5:1_SPACING
?
?
PHYSICAL_RULE_SET
LAYER
3:1_SPACING 4:1_SPACING
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

?
50_OHM_SE 50_OHM_SE
* TOP,BOTTOM
Y Y Y
=STANDARD 0.110 MM
=STANDARD
=STANDARD
=STANDARD
?
SPACING_RULE_SET
LAYER
WEIGHT
0.090 MM
GND PP1V5_MEM
* *
=STANDARD =STANDARD
? ?
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP SPACING_RULE_SET

LAYER
WEIGHT
55_OHM_SE 55_OHM_SE
* TOP,BOTTOM
Y Y Y
=STANDARD 0.090 MM
=STANDARD
=STANDARD
=STANDARD
GND_P2MM PWR_P2MM
* *
0.2 MM 0.2 MM
1000 1000
WEIGHT
0.076 MM
SPACING_RULE_SET
LAYER
NB_STATIC
=STANDARD
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

70_OHM_DIFF 70_OHM_DIFF 70_OHM_DIFF 70_OHM_DIFF
*
TOP,BOTTOM
Y Y Y Y
=STANDARD 0.175 MM 0.135 MM 0.155 MM
=STANDARD 0.175 MM 0.135 MM 0.155 MM
=STANDARD
=STANDARD 0.130 MM 0.130 MM 0.130 MM
=STANDARD
0.130 MM
0.130 MM
0.130 MM
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

*
TOP,BOTTOM
Y Y Y Y
=STANDARD 0.140 MM 0.109 MM 0.125 MM
=STANDARD 0.140 MM 0.109 MM 0.125 MM
=STANDARD
=STANDARD 0.160 MM 0.160 MM 0.160 MM
=STANDARD
0.160 MM
0.160 MM
0.160 MM
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

*
TOP,BOTTOM
Y Y Y Y
=STANDARD 0.160 MM 0.120 MM 0.140 MM
=STANDARD 0.160 MM 0.120 MM 0.140 MM
=STANDARD
=STANDARD 0.160 MM 0.140 MM 0.140 MM
=STANDARD
0.160 MM
0.140 MM
0.140 MM
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

*
TOP,BOTTOM
ISL3,ISL10
ISL4,ISL9
Y Y Y Y
=STANDARD 0.115 MM 0.089 MM 0.105 MM
=STANDARD 0.115 MM 0.089 MM 0.105 MM
=STANDARD
=STANDARD 0.210 MM 0.210 MM 0.210 MM
=STANDARD
0.210 MM
0.210 MM
0.210 MM
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

*
TOP,BOTTOM
ISL3,ISL10
ISL4,ISL9
Y Y Y Y
=STANDARD 0.115 MM 0.089 MM 0.105 MM
=STANDARD 0.115 MM 0.089 MM 0.105 MM
=STANDARD
=STANDARD 0.210 MM 0.210 MM 0.210 MM
=STANDARD
0.210 MM
0.210 MM
0.210 MM
A
SYNC_MASTER=K16_MLB
PAGE TITLE PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
K99 RULE DEFINITIONS

DRAWING NUMBER SIZE
*
TOP,BOTTOM
ISL3,ISL10
ISL4,ISL9
Y Y Y Y
=STANDARD 0.091 MM 0.075 MM 0.085 MM
=STANDARD 0.091 MM 0.075 MM 0.085 MM
=STANDARD
=STANDARD 0.200 MM 0.300 MM 0.200 MM
=STANDARD
0.200 MM
Apple Inc.
R
051-8379
REVISION
0.300 MM
4.4.0
BRANCH PAGE
0.200 MM

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

109 OF 110
SHEET
1:1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
72 OF 73
1UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

SAMSUNG
PART NUMBER QTY DESCRIPTION
CAP, 1UF, 6.3V, 10%, 0402
MURATA
REFERENCE DES
C7203,C7980
TAIYO YUDEN
DESCRIPTION
CAP, 1UF, 6.3V, 10%, 0402
CRITICAL
BOM OPTION
PART NUMBER
QTY
REFERENCE DES
C7203,C7980
CRITICAL
BOM OPTION
PART NUMBER
QTY
DESCRIPTION
CAP, 1UF, 6.3V, 10%, 0402
REFERENCE DES
C7203,C7980
CRITICAL
BOM OPTION
138S0629
CRITICAL SS_CAP_1UF
138S0628
CRITICAL MU_CAP_1UF
138S0630
CRITICAL TY_CAP_1UF
2.2UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

SAMSUNG
CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402 CAP, 2.2UF, 6.3V, 20%, 0402
MURATA
REFERENCE DES CRITICAL BOM OPTION PART NUMBER QTY DESCRIPTION
TAIYO YUDEN
REFERENCE DES CRITICAL BOM OPTION PART NUMBER QTY DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
138S0632 138S0632 138S0632 138S0632 138S0632 138S0632 138S0632 138S0632 138S0632 138S0632 138S0632 138S0632
138S0632 138S0632
10 10 8 10 10 10 10 12 10 10 8 10 10 9
C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249
C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259
C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267
C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909
C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919
C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929
C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939
C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296
C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516
C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541
C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555
C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616
C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641
C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C5310
CRITICALSS_CAP_2_2UF CRITICALSS_CAP_2_2UF CRITICALSS_CAP_2_2UF CRITICALSS_CAP_2_2UF CRITICALSS_CAP_2_2UF CRITICALSS_CAP_2_2UF CRITICALSS_CAP_2_2UF CRITICALSS_CAP_2_2UF CRITICALSS_CAP_2_2UF CRITICALSS_CAP_2_2UF CRITICALSS_CAP_2_2UF CRITICALSS_CAP_2_2UF CRITICALSS_CAP_2_2UF CRITICALSS_CAP_2_2UF
138S0633 138S0633 138S0633 138S0633 138S0633 138S0633 138S0633 138S0633 138S0633 138S0633 138S0633 138S0633 138S0633 138S0633
10 10 8 10 10 10 10 12 10 10 8 10 10 9
C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249
C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259
C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267
C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909
C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919
C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929
C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939
C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296
C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516
C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541
C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555
C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616
C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641
C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C5310
CRITICALMU_CAP_2_2UF CRITICALMU_CAP_2_2UF CRITICALMU_CAP_2_2UF CRITICALMU_CAP_2_2UF CRITICALMU_CAP_2_2UF CRITICALMU_CAP_2_2UF CRITICALMU_CAP_2_2UF CRITICALMU_CAP_2_2UF CRITICALMU_CAP_2_2UF CRITICALMU_CAP_2_2UF CRITICALMU_CAP_2_2UF CRITICALMU_CAP_2_2UF CRITICALMU_CAP_2_2UF CRITICALMU_CAP_2_2UF
138S0634 138S0634 138S0634 138S0634 138S0634 138S0634 138S0634 138S0634 138S0634 138S0634 138S0634 138S0634 138S0634 138S0634
10 10 8 10 10 10 10 12 10 10 8 10 10 9
C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249
C1250,C1251,C1252,C1253,C1254,C1255,C1256,C1257,C1258,C1259
C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267
C9900,C9901,C9902,C9903,C9904,C9905,C9906,C9907,C9908,C9909
C9910,C9911,C9912,C9913,C9914,C9915,C9916,C9917,C9918,C9919
C9920,C9921,C9922,C9923,C9924,C9925,C9926,C9927,C9928,C9929
C9930,C9931,C9932,C9933,C9934,C9935,C9936,C9937,C9938,C9939
C1283,C1284,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296
C3500,C3501,C3504,C3505,C3510,C3511,C3512,C3514,C3515,C3516
C3520,C3521,C3524,C3525,C3530,C3531,C3534,C3535,C3540,C3541
C3542,C3544,C3545,C3546,C3550,C3551,C3554,C3555
C3600,C3601,C3604,C3605,C3610,C3611,C3612,C3614,C3615,C3616
C3620,C3621,C3624,C3625,C3630,C3631,C3634,C3635,C3640,C3641
C3642,C3644,C3645,C3646,C3650,C3651,C3654,C3655,C5310
CRITICALTY_CAP_2_2UF CRITICALTY_CAP_2_2UF CRITICALTY_CAP_2_2UF CRITICALTY_CAP_2_2UF CRITICALTY_CAP_2_2UF CRITICALTY_CAP_2_2UF CRITICALTY_CAP_2_2UF CRITICALTY_CAP_2_2UF CRITICALTY_CAP_2_2UF CRITICALTY_CAP_2_2UF CRITICALTY_CAP_2_2UF CRITICALTY_CAP_2_2UF CRITICALTY_CAP_2_2UF CRITICALTY_CAP_2_2UF

SAMSUNG
CAP, 10UF, 6.3V, 20%, 0603 CAP, 10UF, 6.3V, 20%, 0603 CAP, 10UF, 6.3V, 20%, 0603
MURATA
REFERENCE DES
C1280
TAIYO YUDEN
DESCRIPTION
CRITICAL
BOM OPTION
PART NUMBER
QTY
REFERENCE DES
C1280
CRITICAL
BOM OPTION
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
C1280
CRITICAL
BOM OPTION
138S0626 138S0626 138S0626
1 8 8
C4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647
C9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999
CRITICAL SS_CAP_10UF CRITICAL SS_CAP_10UF CRITICAL SS_CAP_10UF
138S0625 138S0625 138S0625
1 8 8
C4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647
C9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999
CRITICAL MU_CAP_10UF CRITICAL MU_CAP_10UF CRITICAL MU_CAP_10UF
138S0627 138S0627 138S0627
1 8 8
C4690,C4695,C5025,C7205,C7290,C7345,C7355,C7647
C9012,C9486,C2500,C2520,C2560,C2567,C2600,C6999
CRITICAL TY_CAP_10UF CRITICAL TY_CAP_10UF CRITICAL TY_CAP_10UF

SAMSUNG
MURATA
REFERENCE DES
C1210,C1214,C1217,C1218
TAIYO YUDEN
DESCRIPTION
CRITICAL
BOM OPTION
PART NUMBER
QTY
REFERENCE DES
C1210,C1214,C1217,C1218
CRITICAL
BOM OPTION
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
C1210,C1214,C1217,C1218
CRITICAL
BOM OPTION
138S0635 138S0635 138S0635
4 3 5
C1223,C1226,C1227
C1230,C4902,C7360,C7361,C9480
CRITICAL SS_CAP_22UF CRITICAL SS_CAP_22UF CRITICAL SS_CAP_22UF
138S0676 138S0676 138S0676
4 3 5
C1223,C1226,C1227
C1230,C4902,C7360,C7361,C9480
CRITICAL MU_CAP_22UF CRITICAL MU_CAP_22UF CRITICAL MU_CAP_22UF
138S0688 138S0688 138S0688
4 3 5
C1223,C1226,C1227
C1230,C4902,C7360,C7361,C9480
CRITICAL TY_CAP_22UF CRITICAL TY_CAP_22UF CRITICAL TY_CAP_22UF
SYNC_MASTER=K16_MLB
PAGE TITLE
Acoustic Cap BOM Config Tables

DRAWING NUMBER SIZE
Apple Inc.
R
051-8379
REVISION
4.4.0
BRANCH PAGE

110 OF 110
SHEET
73 OF 73

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8

System Block Diagram

SPI ROM AUDI0: SPEAKER AMP

Power Block Diagram

K99 BOM Variants

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K6_MLB 07/07/2010 K16_MLB 07/07/2010

1.5V/1.35V LVDDR3 Supply

IMVP6 CPU VCore Regulator MCP VCore Regulator

POWER 12/11/2009 K6_MLB 07/07/2010

CPUVTT (1.05V) Power Supply

CPU Power & Ground

Misc Power Supplies Power Sequencing

K16_MLB 07/07/2010 K16_MLB 07/07/2010

CPU Decoupling & VID

eXtended Debug Port (Micro-XDP)

Power FETs Internal DisplayPort Connector

K16_MLB 07/07/2010 K16_MLB 07/07/2010

MCP CPU Interface

MCP Memory Interface

External DisplayPort Support

MCP PCIe Interfaces

DisplayPort Connector LCD Backlight Driver

K16_MLB 03/31/2010 K16_MLB 07/07/2010

MCP SATA, USB & Ethernet

LCD Backlight Support

MCP HDA, LPC & MISC

Additional CPU/GPU Decoupling CPU/FSB Constraints

K16_MLB 07/07/2010 K16_MLB 07/07/2010

MCP Power & Ground

MCP89 Memory Rail Gating

MCP89 GFX Core Rail Gating

MCP Constraints 1 MCP Constraints 2

K16_MLB 07/07/2010 K16_MLB 07/07/2010

MCP Standard Decoupling

MCP Graphics Support

SMC Constraints K16/K99 Specific Constraints

K16_MLB 07/07/2010 K16_MLB 07/07/2010

DDR3 DRAM Channel A (0-31)

DDR3 DRAM Channel A (32-63)

K99 RULE DEFINITIONS

DDR3 DRAM Channel B (0-31)

Acoustic Cap BOM Config Tables

DDR3 DRAM Channel B (32-63)

Memory Active Termination

FSB/DDR3 Vref Margining

X21 WIRELESS CONNECTOR

External USB Connectors

LPC+SPI Debug Connector

K16/K99 SMus Connections

Voltage & Current Sensing

NOTICE OF PROPRIETARY PROPERTY:

FSB 64-BIT 800MHZ BASE FREQ.=200MHZ

CPU/MCP TEMP SENSOR

RTC XTAL 32.768KHZ

SATA 2.0 3GBIT/S

24.5X24.5MM 0.6MM PITCH FCPBGA 1244P

HALL EFFECT CONN

TRACKPAD (IPD) CONN

PE0[4,5]:X2,X1 GEN2,UP TO 2 LANES PE1[0,1]:X1,X1 GEN1,UP TO 2 LANES

RIGHT EXT USB