Advantages and disadvantages

Pipelining does not help in all cases. There are several possible disadvantages. An instruction pipeline is said to be fully pipelined if it can accept a new instruction every clock cycle. A pipeline that is not has wait cycles that delay the progress of the pipeline. Advantages of Pipelining: 1. The cycle time of the processor is reduced, thus increasing instruction issue-rate in most cases. 2. Some combinational circuits such as adders or multipliers can be made faster by adding more circuitry. If pipelining is used instead, it can save circuitry vs. a more complex combinational circuit. Disadvantages of Pipelining: 1. A non-pipelined processor executes only a single instruction at a time. This prevents branch delays (in effect, every branch is delayed) and problems with serial instructions being executed concurrently. Consequently the design is simpler and cheaper to manufacture. 2. The instruction latency in a non-pipelined processor is slightly lower than in a pipelined equivalent. This is because extra flip flops must be added to the data path of a pipelined processor. 3. A non-pipelined processor will have a stable instruction bandwidth. The performance of a pipelined processor is much harder to predict and may vary more widely between different programs.

Execution unit tells the bus interface unit from where to fetch instructions as well as to read data.EU gets the opcode of an instruction from an instruction queue.then the EU decodes it or executes it.BIU and EU operate independently.when the EU executing an instruction,then BIU fetches instruction codes from memory and stores them in the queue.this type of overlapping operation of the BIU and EU functional units of a microprocessor is called pipelining. Read more: http://wiki.answers.com/Q/How_is_pipelining_achieved_in_8086_microprocessor#ixzz1e39UR 9d3

What is the function of instruction queue in 8086 microprocessor?

Improve In: Microprocessors, Intel 8086 and 8088 [Edit categories] Pipe Support Products www.pipingtech.com Custom Designed and Fabricated Pipe Supports, Hangers, and More epdm tubing www.wmtubing.com tubing platinum-cured, pharma quality, lot code laser-etched Ads Answers.com > Wiki Answers > Categories > Technology > Computers > Computer Hardware > Microprocessors > What is the function of instruction queue in 8086 microprocessor? Answer: Improve The 8086/8088 instruction queue is a buffer that holds opcode bytes that have been prefetched by the bus interface unit. This speed up operations of the processor by helping to reduce fetches latency, i.e. to improve the probability that an opcode byte fetched by the processor is already available.

This works best when there is no branching, as a branch would invalidate the queue. Advanced processors attempt to "predict" the branch, making the probability even better.

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Instruction queue
The processor executes a program by fetching the instructions from memory and executing them. Usually the processor execution speed is much faster than the memory access speed. Instruction queue is used to prefetch the next instructions in a separate buffer while the processor is executing the current instruction. With a four stage pipeline, the rate at which instructions are executed is four times that of sequential execution.[5] The processor usually has two separate units for fetching the instructions and for executing the instructions.[6][7] The implementation of a pipeline architecture is possible only if the bus interface unit and the execution unit are independent. While the execution unit is decoding or executing an instruction which does not require the use of the data and address buses, the bus interface unit fetches instruction opcodes from the memory.

This process is much faster than sending out an address, reading the opcode and then decoding and executing it. Fetching the next instruction while the current instruction is being decoded or executed is called pipelining.[8] The 8086 architecture has a six-byte prefetch instruction pipeline. As the Execution Unit is executing the current instruction, the bus interface unit reads up to six bytes of opcodes in advance from the memory. The six byte long queue was chosen because the maximum number of bytes required for any instruction in 8086 is this long. An exception is encountered when the execution unit encounters a branch instruction i.e. either a jump or a call instruction. In this case, the entire queue must be dumped and the contents pointed to by the instruction pointer must be fetched from memory.

[edit] Drawbacks
Processors implementing the instruction queue prefetch algorithm are rather technically advanced. The design level complexity of the such processors is much higher than for regular processors. This is primarily because of the need to implement two separate units, the BIU and EU, operating separately. As the complexity of these chips increases, the cost also increases. These processors are relatively costlier than their counterparts without the prefetch input queue. However, these disadvantages are greatly offset by the improvement in processor execution time. After the introduction of prefetch instruction queue in the 8086 processor, all successive processors have incorporated this feature.

How does a queue speed up the processing of the 8086 microprocessor?

Improve In: Microprocessors, Intel 8086 and 8088 [Edit categories] Large inventory of MVME www.globaltechsourcing.com Motorola, Force, GE Fanuc Buy, Sell, Repair VME High Voltage Probes highvoltageprobes.com Wide Bandwidth to 300 kV North Star HV - Standard & Custom Ads Answers.com > Wiki Answers > Categories > Technology > Computers > Computer Hardware > Microprocessors > How does a queue speed up the processing of the 8086 microprocessor? Answer: Improve The instruction prefetch queue speeds up the processing of microprocessors by attempting to have the next opcode bytes available to the execution unit before it actually needs them. This works because, statistically, there is time spent by the execution unit in executing a particular instruction; time that the bus interface unit can use to go ahead and prefetch the next opcode bytes. Sometimes, this results in a loss of time, because the execution unit may branch to some other location. Modern processors attempt to sidestep that by using branch prediction algorithms.

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